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riscv-gcc-1
Commit 7fa4bf9b by Oleg Endo
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iterators.md: New file. 

	* config/sh/iterators.md: New file.
	* config/sh/sync.md (I124, I12, i124suffix): Delete.  Replace usage with
	new iterators QIHISI, QIHI, bw, bwl respectively throughout the file.
	* config/sh/sh.md: Include new file iterators.md.
	(zero_extendhisi2, zero_extendqisi2): Fold into zero_extend<mode>si2.
	(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Fold into
	*zero_extend<mode>si2_compact.
	(*zero_extendqisi2_disp_mem, zero_extendhisi2_disp_mem): Fold into
	*zero_extend<mode>si2_disp_mem.
	(extendhisi2, extendqisi2): Fold into extend<mode>si2.
	(*extendqisi2_compact_reg, *extendhisi2_compact_reg): Fold into
	*extend<mode>si2_compact_reg.
	(*extendqisi2_compact_mem_disp, *extendhisi2_compact_mem_disp): Fold
	into *extend<mode>si2_compact_mem_disp.
	(*extendqisi2_compact_snd, *extendhisi2_compact_snd): Fold into
	*extend<mode>si2_compact_snd.
	(*movsi_index_disp, *movhi_index_disp): Fold with iterators and rename
	to *movsi_index_disp_load, *movhi_index_disp_load,
	*mov<mode>_index_disp_store.
	(*movqi_reg_reg, *movhi_reg_reg): Fold into *mov<mode>_reg_reg.
	(*movqi_store_mem_disp04, *movhi_store_mem_disp05): Fold into
	*mov<mode>_store_mem_disp04.
	(*movqi_store_mem_disp12, *movhi_store_mem_disp13): Fold into
	*mov<mode>_store_mem_disp12.
	(*movqi_load_mem_disp, *movhi_load_mem_disp): Fold into
	*mov<mode>_load_mem_disp04 and *mov<mode>_load_mem_disp12.

From-SVN: r190781
parent de99ac70
Showing with 282 additions and 374 deletions
gcc/ChangeLog
2012-08-29 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/iterators.md: New file.
* config/sh/sync.md (I124, I12, i124suffix): Delete. Replace usage with
new iterators QIHISI, QIHI, bw, bwl respectively throughout the file.
* config/sh/sh.md: Include new file iterators.md.
(zero_extendhisi2, zero_extendqisi2): Fold into zero_extend<mode>si2.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Fold into
*zero_extend<mode>si2_compact.
(*zero_extendqisi2_disp_mem, zero_extendhisi2_disp_mem): Fold into
*zero_extend<mode>si2_disp_mem.
(extendhisi2, extendqisi2): Fold into extend<mode>si2.
(*extendqisi2_compact_reg, *extendhisi2_compact_reg): Fold into
*extend<mode>si2_compact_reg.
(*extendqisi2_compact_mem_disp, *extendhisi2_compact_mem_disp): Fold
into *extend<mode>si2_compact_mem_disp.
(*extendqisi2_compact_snd, *extendhisi2_compact_snd): Fold into
*extend<mode>si2_compact_snd.
(*movsi_index_disp, *movhi_index_disp): Fold with iterators and rename
to *movsi_index_disp_load, *movhi_index_disp_load,
*mov<mode>_index_disp_store.
(*movqi_reg_reg, *movhi_reg_reg): Fold into *mov<mode>_reg_reg.
(*movqi_store_mem_disp04, *movhi_store_mem_disp05): Fold into
*mov<mode>_store_mem_disp04.
(*movqi_store_mem_disp12, *movhi_store_mem_disp13): Fold into
*mov<mode>_store_mem_disp12.
(*movqi_load_mem_disp, *movhi_load_mem_disp): Fold into
*mov<mode>_load_mem_disp04 and *mov<mode>_load_mem_disp12.
2012-08-29 Martin Jambor <mjambor@suse.cz> 2012-08-29 Martin Jambor <mjambor@suse.cz>
* ipa-inline.h (estimate_edge_hints): Call do_estimate_edge_hints, not * ipa-inline.h (estimate_edge_hints): Call do_estimate_edge_hints, not
......
gcc/config/sh/iterators.md 0 → 100644
;; Iterator definitions for GCC SH machine description files.
;; Copyright (C) 2012
;; Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_mode_iterator QIHISI [QI HI SI])
(define_mode_iterator QIHI [QI HI])
(define_mode_iterator HISI [HI SI])
;; Mode attributes that can be used as the instruction suffix for mode
;; variant instructions.
(define_mode_attr bw [(QI "b") (HI "w")])
(define_mode_attr bwl [(QI "b") (HI "w") (SI "l")])
;; Sign/zero-extension code iterator.
(define_code_iterator SZ_EXTEND [sign_extend zero_extend])
;; Mode attributes for mov.b and mov.w displacement constraints.
(define_mode_attr disp04 [(QI "K04") (HI "K05")])
(define_mode_attr disp12 [(QI "K12") (HI "K13")])
gcc/config/sh/sh.md
...@@ -465,6 +465,7 @@ ...@@ -465,6 +465,7 @@
(include "shmedia.md") (include "shmedia.md")
(include "sh4.md") (include "sh4.md")
(include "iterators.md")
(include "predicates.md") (include "predicates.md")
(include "constraints.md") (include "constraints.md")
...@@ -928,6 +929,7 @@ ...@@ -928,6 +929,7 @@
(label_ref (match_dup 2)) (label_ref (match_dup 2))
(pc)))]) (pc)))])
;; FIXME: These could probably use code iterators for the compare op.
(define_split (define_split
[(set (pc) [(set (pc)
(if_then_else (le (match_operand:SI 0 "arith_reg_operand" "") (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
...@@ -5311,15 +5313,15 @@ label: ...@@ -5311,15 +5313,15 @@ label:
(const_string "user")] (const_string "user")]
(const_string "ignore")))]) (const_string "ignore")))])
(define_expand "zero_extendhisi2" (define_expand "zero_extend<mode>si2"
[(set (match_operand:SI 0 "arith_reg_dest" "") [(set (match_operand:SI 0 "arith_reg_dest")
(zero_extend:SI (match_operand:HI 1 "zero_extend_operand" "")))]) (zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))])
(define_insn "*zero_extendhisi2_compact" (define_insn "*zero_extend<mode>si2_compact"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))] (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
"TARGET_SH1" "TARGET_SH1"
"extu.w %1,%0" "extu.<bw> %1,%0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
(define_insn "*zero_extendhisi2_media" (define_insn "*zero_extendhisi2_media"
...@@ -5351,17 +5353,6 @@ label: ...@@ -5351,17 +5353,6 @@ label:
subreg_lowpart_offset (SImode, GET_MODE (op1))); subreg_lowpart_offset (SImode, GET_MODE (op1)));
}) })
(define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "arith_reg_dest" "")
(zero_extend:SI (match_operand:QI 1 "zero_extend_operand" "")))])
(define_insn "*zero_extendqisi2_compact"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"extu.b %1,%0"
[(set_attr "type" "arith")])
(define_insn "*zero_extendqisi2_media" (define_insn "*zero_extendqisi2_media"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))] (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
...@@ -5392,25 +5383,14 @@ label: ...@@ -5392,25 +5383,14 @@ label:
;; zero-displacement addresses might be generated during reload, wich are ;; zero-displacement addresses might be generated during reload, wich are
;; simplified to simple register addresses in turn. Thus, we have to ;; simplified to simple register addresses in turn. Thus, we have to
;; provide the Sdd and Sra alternatives in the patterns. ;; provide the Sdd and Sra alternatives in the patterns.
(define_insn "*zero_extendqisi2_disp_mem" (define_insn "*zero_extend<mode>si2_disp_mem"
[(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
(zero_extend:SI
(match_operand:QI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
"TARGET_SH2A"
"@
movu.b %1,%0
movu.b @(0,%t1),%0"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn "*zero_extendhisi2_disp_mem"
[(set (match_operand:SI 0 "arith_reg_dest" "=r,r") [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
(zero_extend:SI (zero_extend:SI
(match_operand:HI 1 "zero_extend_movu_operand" "Sdd,Sra")))] (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
"TARGET_SH2A" "TARGET_SH2A"
"@ "@
movu.w %1,%0 movu.<bw> %1,%0
movu.w @(0,%t1),%0" movu.<bw> @(0,%t1),%0"
[(set_attr "type" "load") [(set_attr "type" "load")
(set_attr "length" "4")]) (set_attr "length" "4")])
...@@ -5534,18 +5514,9 @@ label: ...@@ -5534,18 +5514,9 @@ label:
operands[1] = XEXP (operands[1], 0); operands[1] = XEXP (operands[1], 0);
}) })
;; FIXME: Maybe fold HImode and QImode stuff with mode iterator? (define_expand "extend<mode>si2"
(define_expand "extendhisi2" [(set (match_operand:SI 0 "arith_reg_dest")
[(set (match_operand:SI 0 "arith_reg_dest" "") (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
(sign_extend:SI (match_operand:HI 1 "general_extend_operand" "")))]
""
"")
(define_expand "extendqisi2"
[(set (match_operand:SI 0 "arith_reg_dest" "")
(sign_extend:SI (match_operand:QI 1 "general_extend_operand" "")))]
""
"")
(define_insn "*extendhisi2_media" (define_insn "*extendhisi2_media"
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
...@@ -5575,69 +5546,41 @@ label: ...@@ -5575,69 +5546,41 @@ label:
subreg_lowpart_offset (SImode, GET_MODE (op1))); subreg_lowpart_offset (SImode, GET_MODE (op1)));
}) })
(define_insn "*extendqisi2_compact_reg" (define_insn "*extend<mode>si2_compact_reg"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(sign_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))] (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
"TARGET_SH1" "TARGET_SH1"
"exts.b %1,%0" "exts.<bw> %1,%0"
[(set_attr "type" "arith")])
(define_insn "*extendhisi2_compact_reg"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(sign_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"exts.w %1,%0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute. ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
;; See movqi insns. ;; See movqi insns.
(define_insn "*extendqisi2_compact_mem_disp" (define_insn "*extend<mode>si2_compact_mem_disp"
[(set (match_operand:SI 0 "arith_reg_dest" "=z,r") [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
(sign_extend:SI (sign_extend:SI
(mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r") (mem:QIHI
(match_operand:SI 2 "const_int_operand" "K04,N")))))] (plus:SI
(match_operand:SI 1 "arith_reg_operand" "%r,r")
(match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
"TARGET_SH1 && ! TARGET_SH2A "TARGET_SH1 && ! TARGET_SH2A
&& sh_legitimate_index_p (QImode, operands[2], false, true)" && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
"@ "@
mov.b @(%O2,%1),%0 mov.<bw> @(%O2,%1),%0
mov.b @%1,%0" mov.<bw> @%1,%0"
[(set_attr "type" "load")]) [(set_attr "type" "load")])
(define_insn "*extendhisi2_compact_mem_disp" (define_insn "*extend<mode>si2_compact_mem_disp"
[(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
(sign_extend:SI
(mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
(match_operand:SI 2 "const_int_operand" "K05,N")))))]
"TARGET_SH1 && ! TARGET_SH2A
&& sh_legitimate_index_p (HImode, operands[2], false, true)"
"@
mov.w @(%O2,%1),%0
mov.w @%1,%0"
[(set_attr "type" "load")])
(define_insn "*extendqisi2_compact_mem_disp"
[(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r") [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
(sign_extend:SI (sign_extend:SI
(mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,r") (mem:QIHI
(match_operand:SI 2 "const_int_operand" "K04,N,K12")))))] (plus:SI
(match_operand:SI 1 "arith_reg_operand" "%r,r,r")
(match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
"TARGET_SH2A && sh_legitimate_index_p (QImode, operands[2], true, true)" "TARGET_SH2A && sh_legitimate_index_p (QImode, operands[2], true, true)"
"@ "@
mov.b @(%O2,%1),%0 mov.<bw> @(%O2,%1),%0
mov.b @%1,%0 mov.<bw> @%1,%0
mov.b @(%O2,%1),%0" mov.<bw> @(%O2,%1),%0"
[(set_attr "type" "load")
(set_attr "length" "2,2,4")])
(define_insn "*extendhisi2_compact_mem_disp"
[(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
(sign_extend:SI
(mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
(match_operand:SI 2 "const_int_operand" "K05,N,K13")))))]
"TARGET_SH2A && sh_legitimate_index_p (HImode, operands[2], true, true)"
"@
mov.w @(%O2,%1),%0
mov.w @%1,%0
mov.w @(%O2,%1),%0"
[(set_attr "type" "load") [(set_attr "type" "load")
(set_attr "length" "2,2,4")]) (set_attr "length" "2,2,4")])
...@@ -5645,18 +5588,12 @@ label: ...@@ -5645,18 +5588,12 @@ label:
;; modes than displacement addressing. They must be defined _after_ the ;; modes than displacement addressing. They must be defined _after_ the
;; displacement addressing patterns. Otherwise the displacement addressing ;; displacement addressing patterns. Otherwise the displacement addressing
;; patterns will not be picked. ;; patterns will not be picked.
(define_insn "*extendqisi2_compact_snd" (define_insn "*extend<mode>si2_compact_snd"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(sign_extend:SI (match_operand:QI 1 "movsrc_no_disp_mem_operand" "Snd")))]
"TARGET_SH1"
"mov.b %1,%0"
[(set_attr "type" "load")])
(define_insn "*extendhisi2_compact_snd"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(sign_extend:SI (match_operand:HI 1 "movsrc_no_disp_mem_operand" "Snd")))] (sign_extend:SI
(match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
"TARGET_SH1" "TARGET_SH1"
"mov.w %1,%0" "mov.<bw> %1,%0"
[(set_attr "type" "load")]) [(set_attr "type" "load")])
(define_insn "*extendqisi2_media" (define_insn "*extendqisi2_media"
...@@ -5887,9 +5824,8 @@ label: ...@@ -5887,9 +5824,8 @@ label:
;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
;; through the ashlsi3 expander in order to get the right shift insn -- ;; through the ashlsi3 expander in order to get the right shift insn --
;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift. ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
;; FIXME: Fold copy pasted patterns somehow.
;; FIXME: Combine never tries this kind of patterns for DImode. ;; FIXME: Combine never tries this kind of patterns for DImode.
(define_insn_and_split "*movsi_index_disp" (define_insn_and_split "*movsi_index_disp_load"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(match_operand:SI 1 "mem_index_disp_operand" "m")) (match_operand:SI 1 "mem_index_disp_operand" "m"))
(clobber (reg:SI T_REG))] (clobber (reg:SI T_REG))]
...@@ -5917,37 +5853,9 @@ label: ...@@ -5917,37 +5853,9 @@ label:
emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2])); emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
}) })
(define_insn_and_split "*movhi_index_disp" (define_insn_and_split "*movhi_index_disp_load"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(sign_extend:SI (match_operand:HI 1 "mem_index_disp_operand" "m")))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"#"
"&& can_create_pseudo_p ()"
[(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
(set (match_dup 0) (sign_extend:SI (match_dup 7)))]
{
rtx mem = operands[1];
rtx plus0_rtx = XEXP (mem, 0);
rtx plus1_rtx = XEXP (plus0_rtx, 0);
rtx mult_rtx = XEXP (plus1_rtx, 0);
operands[1] = XEXP (mult_rtx, 0);
operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
operands[3] = XEXP (plus1_rtx, 1);
operands[4] = XEXP (plus0_rtx, 1);
operands[5] = gen_reg_rtx (SImode);
operands[6] = gen_reg_rtx (SImode);
operands[7] =
replace_equiv_address (mem,
gen_rtx_PLUS (SImode, operands[6], operands[4]));
emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
})
(define_insn_and_split "*movhi_index_disp"
[(set (match_operand:SI 0 "arith_reg_dest") [(set (match_operand:SI 0 "arith_reg_dest")
(zero_extend:SI (match_operand:HI 1 "mem_index_disp_operand"))) (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
(clobber (reg:SI T_REG))] (clobber (reg:SI T_REG))]
"TARGET_SH1" "TARGET_SH1"
"#" "#"
...@@ -5970,6 +5878,13 @@ label: ...@@ -5970,6 +5878,13 @@ label:
emit_insn (gen_ashlsi3 (op_5, op_1, op_2)); emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
emit_insn (gen_addsi3 (op_6, op_5, op_3)); emit_insn (gen_addsi3 (op_6, op_5, op_3));
if (<CODE> == SIGN_EXTEND)
{
emit_insn (gen_extendhisi2 (operands[0], op_7));
DONE;
}
else if (<CODE> == ZERO_EXTEND)
{
/* On SH2A the movu.w insn can be used for zero extending loads. */ /* On SH2A the movu.w insn can be used for zero extending loads. */
if (TARGET_SH2A) if (TARGET_SH2A)
emit_insn (gen_zero_extendhisi2 (operands[0], op_7)); emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
...@@ -5980,39 +5895,14 @@ label: ...@@ -5980,39 +5895,14 @@ label:
gen_lowpart (HImode, operands[0]))); gen_lowpart (HImode, operands[0])));
} }
DONE; DONE;
}
else
FAIL;
}) })
(define_insn_and_split "*movsi_index_disp" (define_insn_and_split "*mov<mode>_index_disp_store"
[(set (match_operand:SI 0 "mem_index_disp_operand" "=m") [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
(match_operand:SI 1 "arith_reg_operand" "r")) (match_operand:HISI 1 "arith_reg_operand" "r"))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"#"
"&& can_create_pseudo_p ()"
[(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
(set (match_dup 7) (match_dup 1))]
{
rtx mem = operands[0];
rtx plus0_rtx = XEXP (mem, 0);
rtx plus1_rtx = XEXP (plus0_rtx, 0);
rtx mult_rtx = XEXP (plus1_rtx, 0);
operands[0] = XEXP (mult_rtx, 0);
operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
operands[3] = XEXP (plus1_rtx, 1);
operands[4] = XEXP (plus0_rtx, 1);
operands[5] = gen_reg_rtx (SImode);
operands[6] = gen_reg_rtx (SImode);
operands[7] =
replace_equiv_address (mem,
gen_rtx_PLUS (SImode, operands[6], operands[4]));
emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
})
(define_insn_and_split "*movsi_index_disp"
[(set (match_operand:HI 0 "mem_index_disp_operand" "=m")
(match_operand:HI 1 "arith_reg_operand" "r"))
(clobber (reg:SI T_REG))] (clobber (reg:SI T_REG))]
"TARGET_SH1" "TARGET_SH1"
"#" "#"
...@@ -6450,103 +6340,59 @@ label: ...@@ -6450,103 +6340,59 @@ label:
;; picked to load/store regs. If the regs regs are on the stack reload will ;; picked to load/store regs. If the regs regs are on the stack reload will
;; try other insns and not stick to movqi_reg_reg. ;; try other insns and not stick to movqi_reg_reg.
;; The same applies to the movhi variants. ;; The same applies to the movhi variants.
(define_insn "*movqi_reg_reg" (define_insn "*mov<mode>_reg_reg"
[(set (match_operand:QI 0 "arith_reg_dest" "=r") [(set (match_operand:QIHI 0 "arith_reg_dest" "=r")
(match_operand:QI 1 "register_operand" "r"))] (match_operand:QIHI 1 "register_operand" "r"))]
"TARGET_SH1"
"mov %1,%0"
[(set_attr "type" "move")])
(define_insn "*movhi_reg_reg"
[(set (match_operand:HI 0 "arith_reg_dest" "=r")
(match_operand:HI 1 "register_operand" "r"))]
"TARGET_SH1" "TARGET_SH1"
"mov %1,%0" "mov %1,%0"
[(set_attr "type" "move")]) [(set_attr "type" "move")])
;; FIXME: The non-SH2A and SH2A variants should be combined by adding ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
;; "enabled" attribute as it is done in other targets. ;; "enabled" attribute as it is done in other targets.
(define_insn "*movqi_store_mem_disp04" (define_insn "*mov<mode>_store_mem_disp04"
[(set (mem:QI (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r") [(set (mem:QIHI
(match_operand:SI 1 "const_int_operand" "K04,N"))) (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
(match_operand:QI 2 "arith_reg_operand" "z,r"))] (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
"TARGET_SH1 && sh_legitimate_index_p (QImode, operands[1], false, true)" (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
"TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
"@ "@
mov.b %2,@(%O1,%0) mov.<bw> %2,@(%O1,%0)
mov.b %2,@%0" mov.<bw> %2,@%0"
[(set_attr "type" "store")]) [(set_attr "type" "store")])
(define_insn "*movhi_store_mem_disp05" (define_insn "*mov<mode>_store_mem_disp12"
[(set (mem:HI (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r") [(set (mem:QIHI
(match_operand:SI 1 "const_int_operand" "K05,N"))) (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
(match_operand:HI 2 "arith_reg_operand" "z,r"))] (match_operand:SI 1 "const_int_operand" "<disp12>")))
"TARGET_SH1 && sh_legitimate_index_p (HImode, operands[1], false, true)" (match_operand:QIHI 2 "arith_reg_operand" "r"))]
"@ "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
mov.w %2,@(%O1,%0) "mov.<bw> %2,@(%O1,%0)"
mov.w %2,@%0"
[(set_attr "type" "store")])
(define_insn "*movqi_store_mem_disp12"
[(set (mem:QI (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
(match_operand:SI 1 "const_int_operand" "K12")))
(match_operand:QI 2 "arith_reg_operand" "r"))]
"TARGET_SH2A && sh_legitimate_index_p (QImode, operands[1], true, true)"
"mov.b %2,@(%O1,%0)"
[(set_attr "type" "store")
(set_attr "length" "4")])
(define_insn "*movhi_store_mem_disp13"
[(set (mem:HI (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
(match_operand:SI 1 "const_int_operand" "K13")))
(match_operand:HI 2 "arith_reg_operand" "r"))]
"TARGET_SH2A && sh_legitimate_index_p (HImode, operands[1], true, true)"
"mov.w %2,@(%O1,%0)"
[(set_attr "type" "store") [(set_attr "type" "store")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "*movqi_load_mem_disp" (define_insn "*mov<mode>_load_mem_disp04"
[(set (match_operand:QI 0 "arith_reg_dest" "=z,r") [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
(mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r") (mem:QIHI
(match_operand:SI 2 "const_int_operand" "K04,N"))))] (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
(match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
"TARGET_SH1 && ! TARGET_SH2A "TARGET_SH1 && ! TARGET_SH2A
&& sh_legitimate_index_p (QImode, operands[2], false, true)" && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
"@ "@
mov.b @(%O2,%1),%0 mov.<bw> @(%O2,%1),%0
mov.b @%1,%0" mov.<bw> @%1,%0"
[(set_attr "type" "load")]) [(set_attr "type" "load")])
(define_insn "*movhi_load_mem_disp" (define_insn "*mov<mode>_load_mem_disp12"
[(set (match_operand:HI 0 "arith_reg_dest" "=z,r") [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
(mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r") (mem:QIHI
(match_operand:SI 2 "const_int_operand" "K05,N"))))] (plus:SI
"TARGET_SH1 && ! TARGET_SH2A (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
&& sh_legitimate_index_p (HImode, operands[2], false, true)" (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
"@ "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
mov.w @(%O2,%1),%0
mov.w @%1,%0"
[(set_attr "type" "load")])
(define_insn "*movqi_load_mem_disp"
[(set (match_operand:QI 0 "arith_reg_dest" "=z,r,r")
(mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
(match_operand:SI 2 "const_int_operand" "K04,N,K12"))))]
"TARGET_SH2A && sh_legitimate_index_p (QImode, operands[2], true, true)"
"@
mov.b @(%O2,%1),%0
mov.b @%1,%0
mov.b @(%O2,%1),%0"
[(set_attr "type" "load")
(set_attr "length" "2,2,4")])
(define_insn "*movhi_load_mem_disp"
[(set (match_operand:HI 0 "arith_reg_dest" "=z,r,r")
(mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
(match_operand:SI 2 "const_int_operand" "K05,N,K13"))))]
"TARGET_SH2A && sh_legitimate_index_p (HImode, operands[2], true, true)"
"@ "@
mov.w @(%O2,%1),%0 mov.<bw> @(%O2,%1),%0
mov.w @%1,%0 mov.<bw> @%1,%0
mov.w @(%O2,%1),%0" mov.<bw> @(%O2,%1),%0"
[(set_attr "type" "load") [(set_attr "type" "load")
(set_attr "length" "2,2,4")]) (set_attr "length" "2,2,4")])
......
gcc/config/sh/sync.md
...@@ -132,10 +132,6 @@ ...@@ -132,10 +132,6 @@
UNSPECV_CMPXCHG_3 UNSPECV_CMPXCHG_3
]) ])
(define_mode_iterator I124 [QI HI SI])
(define_mode_iterator I12 [QI HI])
(define_mode_attr i124suffix [(QI "b") (HI "w") (SI "l")])
(define_mode_attr i124extend_insn [(QI "exts.b") (HI "exts.w") (SI "mov")]) (define_mode_attr i124extend_insn [(QI "exts.b") (HI "exts.w") (SI "mov")])
(define_code_iterator FETCHOP [plus minus ior xor and]) (define_code_iterator FETCHOP [plus minus ior xor and])
...@@ -155,10 +151,10 @@ ...@@ -155,10 +151,10 @@
(define_expand "atomic_compare_and_swap<mode>" (define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "register_operand" "") ;; bool success output [(match_operand:SI 0 "register_operand" "") ;; bool success output
(match_operand:I124 1 "register_operand" "") ;; oldval output (match_operand:QIHISI 1 "register_operand" "") ;; oldval output
(match_operand:I124 2 "memory_operand" "") ;; memory (match_operand:QIHISI 2 "memory_operand" "") ;; memory
(match_operand:I124 3 "atomic_arith_operand" "") ;; expected input (match_operand:QIHISI 3 "atomic_arith_operand" "") ;; expected input
(match_operand:I124 4 "atomic_arith_operand" "") ;; newval input (match_operand:QIHISI 4 "atomic_arith_operand" "") ;; newval input
(match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 5 "const_int_operand" "") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; success model (match_operand:SI 6 "const_int_operand" "") ;; success model
(match_operand:SI 7 "const_int_operand" "")] ;; failure model (match_operand:SI 7 "const_int_operand" "")] ;; failure model
...@@ -216,12 +212,12 @@ ...@@ -216,12 +212,12 @@
(define_insn "atomic_compare_and_swap<mode>_hard" (define_insn "atomic_compare_and_swap<mode>_hard"
[(set (match_operand:SI 0 "register_operand" "=&r") [(set (match_operand:SI 0 "register_operand" "=&r")
(unspec_volatile:SI (unspec_volatile:SI
[(mem:I12 (match_operand:SI 1 "register_operand" "r")) [(mem:QIHI (match_operand:SI 1 "register_operand" "r"))
(match_operand:I12 2 "register_operand" "r") (match_operand:QIHI 2 "register_operand" "r")
(match_operand:I12 3 "register_operand" "r")] (match_operand:QIHI 3 "register_operand" "r")]
UNSPECV_CMPXCHG_1)) UNSPECV_CMPXCHG_1))
(set (mem:I12 (match_dup 1)) (set (mem:QIHI (match_dup 1))
(unspec_volatile:I12 [(const_int 0)] UNSPECV_CMPXCHG_2)) (unspec_volatile:QIHI [(const_int 0)] UNSPECV_CMPXCHG_2))
(set (reg:SI T_REG) (set (reg:SI T_REG)
(unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3)) (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
...@@ -238,8 +234,8 @@ ...@@ -238,8 +234,8 @@
" add #-4,%1" "\n" " add #-4,%1" "\n"
"0: movli.l @%5,r0" "\n" "0: movli.l @%5,r0" "\n"
" mov.l r0,@-r15" "\n" " mov.l r0,@-r15" "\n"
" mov.<i124suffix> @%1,%0" "\n" " mov.<bw> @%1,%0" "\n"
" mov.<i124suffix> %3,@%1" "\n" " mov.<bw> %3,@%1" "\n"
" cmp/eq %4,%0" "\n" " cmp/eq %4,%0" "\n"
" bf{.|/}s 0f" "\n" " bf{.|/}s 0f" "\n"
" mov.l @r15+,r0" "\n" " mov.l @r15+,r0" "\n"
...@@ -252,12 +248,12 @@ ...@@ -252,12 +248,12 @@
(define_insn "atomic_compare_and_swap<mode>_soft" (define_insn "atomic_compare_and_swap<mode>_soft"
[(set (match_operand:SI 0 "register_operand" "=&u") [(set (match_operand:SI 0 "register_operand" "=&u")
(unspec_volatile:SI (unspec_volatile:SI
[(mem:I124 (match_operand:SI 1 "register_operand" "u")) [(mem:QIHISI (match_operand:SI 1 "register_operand" "u"))
(match_operand:I124 2 "register_operand" "u") (match_operand:QIHISI 2 "register_operand" "u")
(match_operand:I124 3 "register_operand" "u")] (match_operand:QIHISI 3 "register_operand" "u")]
UNSPECV_CMPXCHG_1)) UNSPECV_CMPXCHG_1))
(set (mem:I124 (match_dup 1)) (set (mem:QIHISI (match_dup 1))
(unspec_volatile:I124 [(const_int 0)] UNSPECV_CMPXCHG_2)) (unspec_volatile:QIHISI [(const_int 0)] UNSPECV_CMPXCHG_2))
(set (reg:SI T_REG) (set (reg:SI T_REG)
(unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3)) (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))
(clobber (match_scratch:SI 4 "=&u")) (clobber (match_scratch:SI 4 "=&u"))
...@@ -270,10 +266,10 @@ ...@@ -270,10 +266,10 @@
" .align 2" "\n" " .align 2" "\n"
" mov r15,r1" "\n" " mov r15,r1" "\n"
" mov #(0f-1f),r15" "\n" " mov #(0f-1f),r15" "\n"
"0: mov.<i124suffix> @%1,%0" "\n" "0: mov.<bwl> @%1,%0" "\n"
" cmp/eq %0,%4" "\n" " cmp/eq %0,%4" "\n"
" bf 1f" "\n" " bf 1f" "\n"
" mov.<i124suffix> %3,@%1" "\n" " mov.<bwl> %3,@%1" "\n"
"1: mov r1,r15"; "1: mov r1,r15";
} }
[(set_attr "length" "20")]) [(set_attr "length" "20")])
...@@ -282,9 +278,9 @@ ...@@ -282,9 +278,9 @@
;; read - write - return old value ;; read - write - return old value
(define_expand "atomic_exchange<mode>" (define_expand "atomic_exchange<mode>"
[(match_operand:I124 0 "register_operand" "") ;; oldval output [(match_operand:QIHISI 0 "register_operand" "") ;; oldval output
(match_operand:I124 1 "memory_operand" "") ;; memory (match_operand:QIHISI 1 "memory_operand" "") ;; memory
(match_operand:I124 2 "atomic_arith_operand" "") ;; newval input (match_operand:QIHISI 2 "atomic_arith_operand" "") ;; newval input
(match_operand:SI 3 "const_int_operand" "")] ;; memory model (match_operand:SI 3 "const_int_operand" "")] ;; memory model
"TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA"
{ {
...@@ -326,11 +322,11 @@ ...@@ -326,11 +322,11 @@
[(set_attr "length" "10")]) [(set_attr "length" "10")])
(define_insn "atomic_exchange<mode>_hard" (define_insn "atomic_exchange<mode>_hard"
[(set (match_operand:I12 0 "register_operand" "=&r") [(set (match_operand:QIHI 0 "register_operand" "=&r")
(mem:I12 (match_operand:SI 1 "register_operand" "r"))) (mem:QIHI (match_operand:SI 1 "register_operand" "r")))
(set (mem:I12 (match_dup 1)) (set (mem:QIHI (match_dup 1))
(unspec:I12 (unspec:QIHI
[(match_operand:I12 2 "register_operand" "r")] UNSPEC_ATOMIC)) [(match_operand:QIHI 2 "register_operand" "r")] UNSPEC_ATOMIC))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
(clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 3 "=&r"))
(clobber (match_scratch:SI 4 "=1"))] (clobber (match_scratch:SI 4 "=1"))]
...@@ -343,8 +339,8 @@ ...@@ -343,8 +339,8 @@
" add #-4,%1" "\n" " add #-4,%1" "\n"
"0: movli.l @%3,r0" "\n" "0: movli.l @%3,r0" "\n"
" mov.l r0,@-r15" "\n" " mov.l r0,@-r15" "\n"
" mov.<i124suffix> @%1,%0" "\n" " mov.<bw> @%1,%0" "\n"
" mov.<i124suffix> %2,@%1" "\n" " mov.<bw> %2,@%1" "\n"
" mov.l @r15+,r0" "\n" " mov.l @r15+,r0" "\n"
" movco.l r0,@%3" "\n" " movco.l r0,@%3" "\n"
" bf 0b"; " bf 0b";
...@@ -352,11 +348,11 @@ ...@@ -352,11 +348,11 @@
[(set_attr "length" "24")]) [(set_attr "length" "24")])
(define_insn "atomic_exchange<mode>_soft" (define_insn "atomic_exchange<mode>_soft"
[(set (match_operand:I124 0 "register_operand" "=&u") [(set (match_operand:QIHISI 0 "register_operand" "=&u")
(mem:I124 (match_operand:SI 1 "register_operand" "u"))) (mem:QIHISI (match_operand:SI 1 "register_operand" "u")))
(set (mem:I124 (match_dup 1)) (set (mem:QIHISI (match_dup 1))
(unspec:I124 (unspec:QIHISI
[(match_operand:I124 2 "register_operand" "u")] UNSPEC_ATOMIC)) [(match_operand:QIHISI 2 "register_operand" "u")] UNSPEC_ATOMIC))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
(clobber (reg:SI R1_REG))] (clobber (reg:SI R1_REG))]
"TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA"
...@@ -365,8 +361,8 @@ ...@@ -365,8 +361,8 @@
" .align 2" "\n" " .align 2" "\n"
" mov r15,r1" "\n" " mov r15,r1" "\n"
" mov #(0f-1f),r15" "\n" " mov #(0f-1f),r15" "\n"
"0: mov.<i124suffix> @%1,%0" "\n" "0: mov.<bwl> @%1,%0" "\n"
" mov.<i124suffix> %2,@%1" "\n" " mov.<bwl> %2,@%1" "\n"
"1: mov r1,r15"; "1: mov r1,r15";
} }
[(set_attr "length" "14")]) [(set_attr "length" "14")])
...@@ -375,12 +371,12 @@ ...@@ -375,12 +371,12 @@
;; read - add|sub|or|and|xor|nand - write - return old value ;; read - add|sub|or|and|xor|nand - write - return old value
(define_expand "atomic_fetch_<fetchop_name><mode>" (define_expand "atomic_fetch_<fetchop_name><mode>"
[(set (match_operand:I124 0 "register_operand" "") [(set (match_operand:QIHISI 0 "register_operand" "")
(match_operand:I124 1 "memory_operand" "")) (match_operand:QIHISI 1 "memory_operand" ""))
(set (match_dup 1) (set (match_dup 1)
(unspec:I124 (unspec:QIHISI
[(FETCHOP:I124 (match_dup 1) [(FETCHOP:QIHISI (match_dup 1)
(match_operand:I124 2 "<fetchop_predicate>" ""))] (match_operand:QIHISI 2 "<fetchop_predicate>" ""))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(match_operand:SI 3 "const_int_operand" "")] (match_operand:SI 3 "const_int_operand" "")]
"TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA"
...@@ -426,12 +422,12 @@ ...@@ -426,12 +422,12 @@
[(set_attr "length" "10")]) [(set_attr "length" "10")])
(define_insn "atomic_fetch_<fetchop_name><mode>_hard" (define_insn "atomic_fetch_<fetchop_name><mode>_hard"
[(set (match_operand:I12 0 "register_operand" "=&r") [(set (match_operand:QIHI 0 "register_operand" "=&r")
(mem:I12 (match_operand:SI 1 "register_operand" "r"))) (mem:QIHI (match_operand:SI 1 "register_operand" "r")))
(set (mem:I12 (match_dup 1)) (set (mem:QIHI (match_dup 1))
(unspec:I12 (unspec:QIHI
[(FETCHOP:I12 (mem:I12 (match_dup 1)) [(FETCHOP:QIHI (mem:QIHI (match_dup 1))
(match_operand:I12 2 "<fetchop_predicate>" "<fetchop_constraint>"))] (match_operand:QIHI 2 "<fetchop_predicate>" "<fetchop_constraint>"))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
(clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 3 "=&r"))
...@@ -445,10 +441,10 @@ ...@@ -445,10 +441,10 @@
" add #-4,%1" "\n" " add #-4,%1" "\n"
"0: movli.l @%3,r0" "\n" "0: movli.l @%3,r0" "\n"
" mov.l r0,@-r15" "\n" " mov.l r0,@-r15" "\n"
" mov.<i124suffix> @%1,r0" "\n" " mov.<bw> @%1,r0" "\n"
" mov r0,%0" "\n" " mov r0,%0" "\n"
" <fetchop_name> %2,r0" "\n" " <fetchop_name> %2,r0" "\n"
" mov.<i124suffix> r0,@%1" "\n" " mov.<bw> r0,@%1" "\n"
" mov.l @r15+,r0" "\n" " mov.l @r15+,r0" "\n"
" movco.l r0,@%3" "\n" " movco.l r0,@%3" "\n"
" bf 0b"; " bf 0b";
...@@ -456,14 +452,14 @@ ...@@ -456,14 +452,14 @@
[(set_attr "length" "28")]) [(set_attr "length" "28")])
(define_insn "atomic_fetch_<fetchop_name><mode>_soft" (define_insn "atomic_fetch_<fetchop_name><mode>_soft"
[(set (match_operand:I124 0 "register_operand" "=&u") [(set (match_operand:QIHISI 0 "register_operand" "=&u")
(mem:I124 (match_operand:SI 1 "register_operand" "u"))) (mem:QIHISI (match_operand:SI 1 "register_operand" "u")))
(set (mem:I124 (match_dup 1)) (set (mem:QIHISI (match_dup 1))
(unspec:I124 (unspec:QIHISI
[(FETCHOP:I124 (mem:I124 (match_dup 1)) [(FETCHOP:QIHISI (mem:QIHISI (match_dup 1))
(match_operand:I124 2 "register_operand" "u"))] (match_operand:QIHISI 2 "register_operand" "u"))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (match_scratch:I124 3 "=&u")) (clobber (match_scratch:QIHISI 3 "=&u"))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
(clobber (reg:SI R1_REG))] (clobber (reg:SI R1_REG))]
"TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA"
...@@ -472,21 +468,21 @@ ...@@ -472,21 +468,21 @@
" .align 2" "\n" " .align 2" "\n"
" mov r15,r1" "\n" " mov r15,r1" "\n"
" mov #(0f-1f),r15" "\n" " mov #(0f-1f),r15" "\n"
"0: mov.<i124suffix> @%1,%0" "\n" "0: mov.<bwl> @%1,%0" "\n"
" mov %0,%3" "\n" " mov %0,%3" "\n"
" <fetchop_name> %2,%3" "\n" " <fetchop_name> %2,%3" "\n"
" mov.<i124suffix> %3,@%1" "\n" " mov.<bwl> %3,@%1" "\n"
"1: mov r1,r15"; "1: mov r1,r15";
} }
[(set_attr "length" "18")]) [(set_attr "length" "18")])
(define_expand "atomic_fetch_nand<mode>" (define_expand "atomic_fetch_nand<mode>"
[(set (match_operand:I124 0 "register_operand" "") [(set (match_operand:QIHISI 0 "register_operand" "")
(match_operand:I124 1 "memory_operand" "")) (match_operand:QIHISI 1 "memory_operand" ""))
(set (match_dup 1) (set (match_dup 1)
(unspec:I124 (unspec:QIHISI
[(not:I124 (and:I124 (match_dup 1) [(not:QIHISI (and:QIHISI (match_dup 1)
(match_operand:I124 2 "atomic_logical_operand" "")))] (match_operand:QIHISI 2 "atomic_logical_operand" "")))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(match_operand:SI 3 "const_int_operand" "")] (match_operand:SI 3 "const_int_operand" "")]
"TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA"
...@@ -533,12 +529,12 @@ ...@@ -533,12 +529,12 @@
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "atomic_fetch_nand<mode>_hard" (define_insn "atomic_fetch_nand<mode>_hard"
[(set (match_operand:I12 0 "register_operand" "=&r") [(set (match_operand:QIHI 0 "register_operand" "=&r")
(mem:I12 (match_operand:SI 1 "register_operand" "r"))) (mem:QIHI (match_operand:SI 1 "register_operand" "r")))
(set (mem:I12 (match_dup 1)) (set (mem:QIHI (match_dup 1))
(unspec:I12 (unspec:QIHI
[(not:I12 (and:I12 (mem:I12 (match_dup 1)) [(not:QIHI (and:QIHI (mem:QIHI (match_dup 1))
(match_operand:I12 2 "logical_operand" "rK08")))] (match_operand:QIHI 2 "logical_operand" "rK08")))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
(clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 3 "=&r"))
...@@ -552,11 +548,11 @@ ...@@ -552,11 +548,11 @@
" add #-4,%1" "\n" " add #-4,%1" "\n"
"0: movli.l @%3,r0" "\n" "0: movli.l @%3,r0" "\n"
" mov.l r0,@-r15" "\n" " mov.l r0,@-r15" "\n"
" mov.<i124suffix> @%1,r0" "\n" " mov.<bw> @%1,r0" "\n"
" mov r0,%0" "\n" " mov r0,%0" "\n"
" and %2,r0" "\n" " and %2,r0" "\n"
" not r0,r0" "\n" " not r0,r0" "\n"
" mov.<i124suffix> r0,@%1" "\n" " mov.<bw> r0,@%1" "\n"
" mov.l @r15+,r0" "\n" " mov.l @r15+,r0" "\n"
" movco.l r0,@%3" "\n" " movco.l r0,@%3" "\n"
" bf 0b"; " bf 0b";
...@@ -564,14 +560,14 @@ ...@@ -564,14 +560,14 @@
[(set_attr "length" "30")]) [(set_attr "length" "30")])
(define_insn "atomic_fetch_nand<mode>_soft" (define_insn "atomic_fetch_nand<mode>_soft"
[(set (match_operand:I124 0 "register_operand" "=&u") [(set (match_operand:QIHISI 0 "register_operand" "=&u")
(mem:I124 (match_operand:SI 1 "register_operand" "u"))) (mem:QIHISI (match_operand:SI 1 "register_operand" "u")))
(set (mem:I124 (match_dup 1)) (set (mem:QIHISI (match_dup 1))
(unspec:I124 (unspec:QIHISI
[(not:I124 (and:I124 (mem:I124 (match_dup 1)) [(not:QIHISI (and:QIHISI (mem:QIHISI (match_dup 1))
(match_operand:I124 2 "register_operand" "u")))] (match_operand:QIHISI 2 "register_operand" "u")))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (match_scratch:I124 3 "=&u")) (clobber (match_scratch:QIHISI 3 "=&u"))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
(clobber (reg:SI R1_REG))] (clobber (reg:SI R1_REG))]
"TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA"
...@@ -580,11 +576,11 @@ ...@@ -580,11 +576,11 @@
" mov r15,r1" "\n" " mov r15,r1" "\n"
" .align 2" "\n" " .align 2" "\n"
" mov #(0f-1f),r15" "\n" " mov #(0f-1f),r15" "\n"
"0: mov.<i124suffix> @%1,%0" "\n" "0: mov.<bwl> @%1,%0" "\n"
" mov %2,%3" "\n" " mov %2,%3" "\n"
" and %0,%3" "\n" " and %0,%3" "\n"
" not %3,%3" "\n" " not %3,%3" "\n"
" mov.<i124suffix> %3,@%1" "\n" " mov.<bwl> %3,@%1" "\n"
"1: mov r1,r15"; "1: mov r1,r15";
} }
[(set_attr "length" "20")]) [(set_attr "length" "20")])
...@@ -593,13 +589,13 @@ ...@@ -593,13 +589,13 @@
;; read - add|sub|or|and|xor|nand - write - return new value ;; read - add|sub|or|and|xor|nand - write - return new value
(define_expand "atomic_<fetchop_name>_fetch<mode>" (define_expand "atomic_<fetchop_name>_fetch<mode>"
[(set (match_operand:I124 0 "register_operand" "") [(set (match_operand:QIHISI 0 "register_operand" "")
(FETCHOP:I124 (FETCHOP:QIHISI
(match_operand:I124 1 "memory_operand" "") (match_operand:QIHISI 1 "memory_operand" "")
(match_operand:I124 2 "<fetchop_predicate>" ""))) (match_operand:QIHISI 2 "<fetchop_predicate>" "")))
(set (match_dup 1) (set (match_dup 1)
(unspec:I124 (unspec:QIHISI
[(FETCHOP:I124 (match_dup 1) (match_dup 2))] [(FETCHOP:QIHISI (match_dup 1) (match_dup 2))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(match_operand:SI 3 "const_int_operand" "")] (match_operand:SI 3 "const_int_operand" "")]
"TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA"
...@@ -643,13 +639,13 @@ ...@@ -643,13 +639,13 @@
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "atomic_<fetchop_name>_fetch<mode>_hard" (define_insn "atomic_<fetchop_name>_fetch<mode>_hard"
[(set (match_operand:I12 0 "register_operand" "=&r") [(set (match_operand:QIHI 0 "register_operand" "=&r")
(FETCHOP:I12 (FETCHOP:QIHI
(mem:I12 (match_operand:SI 1 "register_operand" "r")) (mem:QIHI (match_operand:SI 1 "register_operand" "r"))
(match_operand:I12 2 "<fetchop_predicate>" "<fetchop_constraint>"))) (match_operand:QIHI 2 "<fetchop_predicate>" "<fetchop_constraint>")))
(set (mem:I12 (match_dup 1)) (set (mem:QIHI (match_dup 1))
(unspec:I12 (unspec:QIHI
[(FETCHOP:I12 (mem:I12 (match_dup 1)) (match_dup 2))] [(FETCHOP:QIHI (mem:QIHI (match_dup 1)) (match_dup 2))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
...@@ -664,9 +660,9 @@ ...@@ -664,9 +660,9 @@
" add #-4,%1" "\n" " add #-4,%1" "\n"
"0: movli.l @%3,r0" "\n" "0: movli.l @%3,r0" "\n"
" mov.l r0,@-r15" "\n" " mov.l r0,@-r15" "\n"
" mov.<i124suffix> @%1,r0" "\n" " mov.<bw> @%1,r0" "\n"
" <fetchop_name> %2,r0" "\n" " <fetchop_name> %2,r0" "\n"
" mov.<i124suffix> r0,@%1" "\n" " mov.<bw> r0,@%1" "\n"
" mov r0,%0" "\n" " mov r0,%0" "\n"
" mov.l @r15+,r0" "\n" " mov.l @r15+,r0" "\n"
" movco.l r0,@%3" "\n" " movco.l r0,@%3" "\n"
...@@ -675,13 +671,13 @@ ...@@ -675,13 +671,13 @@
[(set_attr "length" "28")]) [(set_attr "length" "28")])
(define_insn "atomic_<fetchop_name>_fetch<mode>_soft" (define_insn "atomic_<fetchop_name>_fetch<mode>_soft"
[(set (match_operand:I124 0 "register_operand" "=&u") [(set (match_operand:QIHISI 0 "register_operand" "=&u")
(FETCHOP:I124 (FETCHOP:QIHISI
(mem:I124 (match_operand:SI 1 "register_operand" "u")) (mem:QIHISI (match_operand:SI 1 "register_operand" "u"))
(match_operand:I124 2 "register_operand" "u"))) (match_operand:QIHISI 2 "register_operand" "u")))
(set (mem:I124 (match_dup 1)) (set (mem:QIHISI (match_dup 1))
(unspec:I124 (unspec:QIHISI
[(FETCHOP:I124 (mem:I124 (match_dup 1)) (match_dup 2))] [(FETCHOP:QIHISI (mem:QIHISI (match_dup 1)) (match_dup 2))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
(clobber (reg:SI R1_REG))] (clobber (reg:SI R1_REG))]
...@@ -691,21 +687,21 @@ ...@@ -691,21 +687,21 @@
" mov r15,r1" "\n" " mov r15,r1" "\n"
" .align 2" "\n" " .align 2" "\n"
" mov #(0f-1f),r15" "\n" " mov #(0f-1f),r15" "\n"
"0: mov.<i124suffix> @%1,%0" "\n" "0: mov.<bwl> @%1,%0" "\n"
" <fetchop_name> %2,%0" "\n" " <fetchop_name> %2,%0" "\n"
" mov.<i124suffix> %0,@%1" "\n" " mov.<bwl> %0,@%1" "\n"
"1: mov r1,r15"; "1: mov r1,r15";
} }
[(set_attr "length" "16")]) [(set_attr "length" "16")])
(define_expand "atomic_nand_fetch<mode>" (define_expand "atomic_nand_fetch<mode>"
[(set (match_operand:I124 0 "register_operand" "") [(set (match_operand:QIHISI 0 "register_operand" "")
(not:I124 (and:I124 (not:QIHISI (and:QIHISI
(match_operand:I124 1 "memory_operand" "") (match_operand:QIHISI 1 "memory_operand" "")
(match_operand:I124 2 "atomic_logical_operand" "")))) (match_operand:QIHISI 2 "atomic_logical_operand" ""))))
(set (match_dup 1) (set (match_dup 1)
(unspec:I124 (unspec:QIHISI
[(not:I124 (and:I124 (match_dup 1) (match_dup 2)))] [(not:QIHISI (and:QIHISI (match_dup 1) (match_dup 2)))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(match_operand:SI 3 "const_int_operand" "")] (match_operand:SI 3 "const_int_operand" "")]
"TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA"
...@@ -749,12 +745,13 @@ ...@@ -749,12 +745,13 @@
[(set_attr "length" "10")]) [(set_attr "length" "10")])
(define_insn "atomic_nand_fetch<mode>_hard" (define_insn "atomic_nand_fetch<mode>_hard"
[(set (match_operand:I12 0 "register_operand" "=&r") [(set (match_operand:QIHI 0 "register_operand" "=&r")
(not:I12 (and:I12 (mem:I12 (match_operand:SI 1 "register_operand" "r")) (not:QIHI
(match_operand:I12 2 "logical_operand" "rK08")))) (and:QIHI (mem:QIHI (match_operand:SI 1 "register_operand" "r"))
(set (mem:I12 (match_dup 1)) (match_operand:QIHI 2 "logical_operand" "rK08"))))
(unspec:I12 (set (mem:QIHI (match_dup 1))
[(not:I12 (and:I12 (mem:I12 (match_dup 1)) (match_dup 2)))] (unspec:QIHI
[(not:QIHI (and:QIHI (mem:QIHI (match_dup 1)) (match_dup 2)))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
(clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 3 "=&r"))
...@@ -768,10 +765,10 @@ ...@@ -768,10 +765,10 @@
" add #-4,%1" "\n" " add #-4,%1" "\n"
"0: movli.l @%3,r0" "\n" "0: movli.l @%3,r0" "\n"
" mov.l r0,@-r15" "\n" " mov.l r0,@-r15" "\n"
" mov.<i124suffix> @%1,r0" "\n" " mov.<bw> @%1,r0" "\n"
" and %2,r0" "\n" " and %2,r0" "\n"
" not r0,%0" "\n" " not r0,%0" "\n"
" mov.<i124suffix> %0,@%1" "\n" " mov.<bw> %0,@%1" "\n"
" mov.l @r15+,r0" "\n" " mov.l @r15+,r0" "\n"
" movco.l r0,@%3" "\n" " movco.l r0,@%3" "\n"
" bf 0b"; " bf 0b";
...@@ -779,13 +776,13 @@ ...@@ -779,13 +776,13 @@
[(set_attr "length" "28")]) [(set_attr "length" "28")])
(define_insn "atomic_nand_fetch<mode>_soft" (define_insn "atomic_nand_fetch<mode>_soft"
[(set (match_operand:I124 0 "register_operand" "=&u") [(set (match_operand:QIHISI 0 "register_operand" "=&u")
(not:I124 (and:I124 (not:QIHISI (and:QIHISI
(mem:I124 (match_operand:SI 1 "register_operand" "u")) (mem:QIHISI (match_operand:SI 1 "register_operand" "u"))
(match_operand:I124 2 "register_operand" "u")))) (match_operand:QIHISI 2 "register_operand" "u"))))
(set (mem:I124 (match_dup 1)) (set (mem:QIHISI (match_dup 1))
(unspec:I124 (unspec:QIHISI
[(not:I124 (and:I124 (mem:I124 (match_dup 1)) (match_dup 2)))] [(not:QIHISI (and:QIHISI (mem:QIHISI (match_dup 1)) (match_dup 2)))]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (reg:SI R0_REG)) (clobber (reg:SI R0_REG))
(clobber (reg:SI R1_REG))] (clobber (reg:SI R1_REG))]
...@@ -795,10 +792,10 @@ ...@@ -795,10 +792,10 @@
" .align 2" "\n" " .align 2" "\n"
" mov r15,r1" "\n" " mov r15,r1" "\n"
" mov #(0f-1f),r15" "\n" " mov #(0f-1f),r15" "\n"
"0: mov.<i124suffix> @%1,%0" "\n" "0: mov.<bwl> @%1,%0" "\n"
" and %2,%0" "\n" " and %2,%0" "\n"
" not %0,%0" "\n" " not %0,%0" "\n"
" mov.<i124suffix> %0,@%1" "\n" " mov.<bwl> %0,@%1" "\n"
"1: mov r1,r15"; "1: mov r1,r15";
} }
[(set_attr "length" "18")]) [(set_attr "length" "18")])
......
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