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riscv-gcc-1
Commit 7efe41a9 by Richard Henderson
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libgcc2.c (near eh_context_specific): Comment #endif string. 

        * libgcc2.c (near eh_context_specific): Comment #endif string.
        * longlong.h: Don't use strings with embedded newlines.

From-SVN: r33687
parent 12a4e8c5
Showing with 238 additions and 268 deletions
gcc/libgcc2.c
...@@ -3193,7 +3193,7 @@ eh_context_specific (void) ...@@ -3193,7 +3193,7 @@ eh_context_specific (void)
return eh; return eh;
} }
#endif __GTHREADS #endif /* __GTHREADS */
/* Support routines for setjmp/longjmp exception handling. */ /* Support routines for setjmp/longjmp exception handling. */
......
gcc/longlong.h
...@@ -108,8 +108,7 @@ ...@@ -108,8 +108,7 @@
#if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32 #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %1,%4,%5 __asm__ ("add %1,%4,%5\n\taddc %0,%2,%3" \
addc %0,%2,%3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%r" ((USItype) (ah)), \ : "%r" ((USItype) (ah)), \
...@@ -117,8 +116,7 @@ ...@@ -117,8 +116,7 @@
"%r" ((USItype) (al)), \ "%r" ((USItype) (al)), \
"rI" ((USItype) (bl))) "rI" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %1,%4,%5 __asm__ ("sub %1,%4,%5\n\tsubc %0,%2,%3" \
subc %0,%2,%3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "r" ((USItype) (ah)), \ : "r" ((USItype) (ah)), \
...@@ -175,8 +173,7 @@ extern UDItype __udiv_qrnnd PARAMS ((UDItype *, UDItype, UDItype, UDItype)); ...@@ -175,8 +173,7 @@ extern UDItype __udiv_qrnnd PARAMS ((UDItype *, UDItype, UDItype, UDItype));
#if defined (__arc__) && W_TYPE_SIZE == 32 #if defined (__arc__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add.f %1, %4, %5 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
adc %0, %2, %3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%r" ((USItype) (ah)), \ : "%r" ((USItype) (ah)), \
...@@ -184,8 +181,7 @@ extern UDItype __udiv_qrnnd PARAMS ((UDItype *, UDItype, UDItype, UDItype)); ...@@ -184,8 +181,7 @@ extern UDItype __udiv_qrnnd PARAMS ((UDItype *, UDItype, UDItype, UDItype));
"%r" ((USItype) (al)), \ "%r" ((USItype) (al)), \
"rIJ" ((USItype) (bl))) "rIJ" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.f %1, %4, %5 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
sbc %0, %2, %3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "r" ((USItype) (ah)), \ : "r" ((USItype) (ah)), \
...@@ -206,8 +202,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -206,8 +202,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__arm__) && W_TYPE_SIZE == 32 #if defined (__arm__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("adds %1, %4, %5 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
adc %0, %2, %3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%r" ((USItype) (ah)), \ : "%r" ((USItype) (ah)), \
...@@ -215,8 +210,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -215,8 +210,7 @@ UDItype __umulsidi3 (USItype, USItype);
"%r" ((USItype) (al)), \ "%r" ((USItype) (al)), \
"rI" ((USItype) (bl))) "rI" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subs %1, %4, %5 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
sbc %0, %2, %3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "r" ((USItype) (ah)), \ : "r" ((USItype) (ah)), \
...@@ -225,19 +219,19 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -225,19 +219,19 @@ UDItype __umulsidi3 (USItype, USItype);
"rI" ((USItype) (bl))) "rI" ((USItype) (bl)))
#define umul_ppmm(xh, xl, a, b) \ #define umul_ppmm(xh, xl, a, b) \
{register USItype __t0, __t1, __t2; \ {register USItype __t0, __t1, __t2; \
__asm__ ("%@ Inlined umul_ppmm __asm__ ("%@ Inlined umul_ppmm\n" \
mov %2, %5, lsr #16 " mov %2, %5, lsr #16\n" \
mov %0, %6, lsr #16 " mov %0, %6, lsr #16\n" \
bic %3, %5, %2, lsl #16 " bic %3, %5, %2, lsl #16\n" \
bic %4, %6, %0, lsl #16 " bic %4, %6, %0, lsl #16\n" \
mul %1, %3, %4 " mul %1, %3, %4\n" \
mul %4, %2, %4 " mul %4, %2, %4\n" \
mul %3, %0, %3 " mul %3, %0, %3\n" \
mul %0, %2, %0 " mul %0, %2, %0\n" \
adds %3, %4, %3 " adds %3, %4, %3\n" \
addcs %0, %0, #65536 " addcs %0, %0, #65536\n" \
adds %1, %1, %3, lsl #16 " adds %1, %1, %3, lsl #16\n" \
adc %0, %0, %3, lsr #16" \ " adc %0, %0, %3, lsr #16" \
: "=&r" ((USItype) (xh)), \ : "=&r" ((USItype) (xh)), \
"=r" ((USItype) (xl)), \ "=r" ((USItype) (xl)), \
"=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
...@@ -277,8 +271,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -277,8 +271,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__gmicro__) && W_TYPE_SIZE == 32 #if defined (__gmicro__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add.w %5,%1 __asm__ ("add.w %5,%1\n\taddx %3,%0" \
addx %3,%0" \
: "=g" ((USItype) (sh)), \ : "=g" ((USItype) (sh)), \
"=&g" ((USItype) (sl)) \ "=&g" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \ : "%0" ((USItype) (ah)), \
...@@ -286,8 +279,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -286,8 +279,7 @@ UDItype __umulsidi3 (USItype, USItype);
"%1" ((USItype) (al)), \ "%1" ((USItype) (al)), \
"g" ((USItype) (bl))) "g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.w %5,%1 __asm__ ("sub.w %5,%1\n\tsubx %3,%0" \
subx %3,%0" \
: "=g" ((USItype) (sh)), \ : "=g" ((USItype) (sh)), \
"=&g" ((USItype) (sl)) \ "=&g" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \ : "0" ((USItype) (ah)), \
...@@ -316,8 +308,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -316,8 +308,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__hppa) && W_TYPE_SIZE == 32 #if defined (__hppa) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %4,%5,%1 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
addc %2,%3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%rM" ((USItype) (ah)), \ : "%rM" ((USItype) (ah)), \
...@@ -325,8 +316,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -325,8 +316,7 @@ UDItype __umulsidi3 (USItype, USItype);
"%rM" ((USItype) (al)), \ "%rM" ((USItype) (al)), \
"rM" ((USItype) (bl))) "rM" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %4,%5,%1 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
subb %2,%3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "rM" ((USItype) (ah)), \ : "rM" ((USItype) (ah)), \
...@@ -357,22 +347,22 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -357,22 +347,22 @@ UDItype __umulsidi3 (USItype, USItype);
do { \ do { \
USItype __tmp; \ USItype __tmp; \
__asm__ ( \ __asm__ ( \
"ldi 1,%0 "ldi 1,%0\n" \
extru,= %1,15,16,%%r0 ; Bits 31..16 zero? " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
extru,tr %1,15,16,%1 ; No. Shift down, skip add. " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
ldo 16(%0),%0 ; Yes. Perform add. " ldo 16(%0),%0 ; Yes. Perform add.\n" \
extru,= %1,23,8,%%r0 ; Bits 15..8 zero? " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
extru,tr %1,23,8,%1 ; No. Shift down, skip add. " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
ldo 8(%0),%0 ; Yes. Perform add. " ldo 8(%0),%0 ; Yes. Perform add.\n" \
extru,= %1,27,4,%%r0 ; Bits 7..4 zero? " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
extru,tr %1,27,4,%1 ; No. Shift down, skip add. " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
ldo 4(%0),%0 ; Yes. Perform add. " ldo 4(%0),%0 ; Yes. Perform add.\n" \
extru,= %1,29,2,%%r0 ; Bits 3..2 zero? " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
extru,tr %1,29,2,%1 ; No. Shift down, skip add. " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
ldo 2(%0),%0 ; Yes. Perform add. " ldo 2(%0),%0 ; Yes. Perform add.\n" \
extru %1,30,1,%1 ; Extract bit 1. " extru %1,30,1,%1 ; Extract bit 1.\n" \
sub %0,%1,%0 ; Subtract it. " sub %0,%1,%0 ; Subtract it.\n" \
" : "=r" (count), "=r" (__tmp) : "1" (x)); \ : "=r" (count), "=r" (__tmp) : "1" (x)); \
} while (0) } while (0)
#endif #endif
...@@ -419,8 +409,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -419,8 +409,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl %5,%1 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
adcl %3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \ : "%0" ((USItype) (ah)), \
...@@ -428,8 +417,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -428,8 +417,7 @@ UDItype __umulsidi3 (USItype, USItype);
"%1" ((USItype) (al)), \ "%1" ((USItype) (al)), \
"g" ((USItype) (bl))) "g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subl %5,%1 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
sbbl %3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \ : "0" ((USItype) (ah)), \
...@@ -525,9 +513,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -525,9 +513,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__M32R__) && W_TYPE_SIZE == 32 #if defined (__M32R__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */ \ /* The cmp clears the condition bit. */ \
__asm__ ("cmp %0,%0 __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0" \
addx %%5,%1
addx %%3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \ : "%0" ((USItype) (ah)), \
...@@ -537,9 +523,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -537,9 +523,7 @@ UDItype __umulsidi3 (USItype, USItype);
: "cbit") : "cbit")
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */ \ /* The cmp clears the condition bit. */ \
__asm__ ("cmp %0,%0 __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0" \
subx %5,%1
subx %3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \ : "0" ((USItype) (ah)), \
...@@ -551,8 +535,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -551,8 +535,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__mc68000__) && W_TYPE_SIZE == 32 #if defined (__mc68000__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add%.l %5,%1 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
addx%.l %3,%0" \
: "=d" ((USItype) (sh)), \ : "=d" ((USItype) (sh)), \
"=&d" ((USItype) (sl)) \ "=&d" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \ : "%0" ((USItype) (ah)), \
...@@ -560,8 +543,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -560,8 +543,7 @@ UDItype __umulsidi3 (USItype, USItype);
"%1" ((USItype) (al)), \ "%1" ((USItype) (al)), \
"g" ((USItype) (bl))) "g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub%.l %5,%1 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
subx%.l %3,%0" \
: "=d" ((USItype) (sh)), \ : "=d" ((USItype) (sh)), \
"=&d" ((USItype) (sl)) \ "=&d" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \ : "0" ((USItype) (ah)), \
...@@ -602,32 +584,32 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -602,32 +584,32 @@ UDItype __umulsidi3 (USItype, USItype);
#if !defined(__mcf5200__) #if !defined(__mcf5200__)
/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */ /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
#define umul_ppmm(xh, xl, a, b) \ #define umul_ppmm(xh, xl, a, b) \
__asm__ ("| Inlined umul_ppmm __asm__ ("| Inlined umul_ppmm\n" \
move%.l %2,%/d0 " move%.l %2,%/d0\n" \
move%.l %3,%/d1 " move%.l %3,%/d1\n" \
move%.l %/d0,%/d2 " move%.l %/d0,%/d2\n" \
swap %/d0 " swap %/d0\n" \
move%.l %/d1,%/d3 " move%.l %/d1,%/d3\n" \
swap %/d1 " swap %/d1\n" \
move%.w %/d2,%/d4 " move%.w %/d2,%/d4\n" \
mulu %/d3,%/d4 " mulu %/d3,%/d4\n" \
mulu %/d1,%/d2 " mulu %/d1,%/d2\n" \
mulu %/d0,%/d3 " mulu %/d0,%/d3\n" \
mulu %/d0,%/d1 " mulu %/d0,%/d1\n" \
move%.l %/d4,%/d0 " move%.l %/d4,%/d0\n" \
eor%.w %/d0,%/d0 " eor%.w %/d0,%/d0\n" \
swap %/d0 " swap %/d0\n" \
add%.l %/d0,%/d2 " add%.l %/d0,%/d2\n" \
add%.l %/d3,%/d2 " add%.l %/d3,%/d2\n" \
jcc 1f " jcc 1f\n" \
add%.l %#65536,%/d1 " add%.l %#65536,%/d1\n" \
1: swap %/d2 "1: swap %/d2\n" \
moveq %#0,%/d0 " moveq %#0,%/d0\n" \
move%.w %/d2,%/d0 " move%.w %/d2,%/d0\n" \
move%.w %/d4,%/d2 " move%.w %/d4,%/d2\n" \
move%.l %/d2,%1 " move%.l %/d2,%1\n" \
add%.l %/d1,%/d0 " add%.l %/d1,%/d0\n" \
move%.l %/d0,%0" \ " move%.l %/d0,%0" \
: "=g" ((USItype) (xh)), \ : "=g" ((USItype) (xh)), \
"=g" ((USItype) (xl)) \ "=g" ((USItype) (xl)) \
: "g" ((USItype) (a)), \ : "g" ((USItype) (a)), \
...@@ -653,8 +635,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -653,8 +635,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__m88000__) && W_TYPE_SIZE == 32 #if defined (__m88000__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addu.co %1,%r4,%r5 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
addu.ci %0,%r2,%r3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%rJ" ((USItype) (ah)), \ : "%rJ" ((USItype) (ah)), \
...@@ -662,8 +643,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -662,8 +643,7 @@ UDItype __umulsidi3 (USItype, USItype);
"%rJ" ((USItype) (al)), \ "%rJ" ((USItype) (al)), \
"rJ" ((USItype) (bl))) "rJ" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subu.co %1,%r4,%r5 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
subu.ci %0,%r2,%r3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "rJ" ((USItype) (ah)), \ : "rJ" ((USItype) (ah)), \
...@@ -882,8 +862,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -882,8 +862,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__pyr__) && W_TYPE_SIZE == 32 #if defined (__pyr__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addw %5,%1 __asm__ ("addw %5,%1\n\taddwc %3,%0" \
addwc %3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \ : "%0" ((USItype) (ah)), \
...@@ -891,8 +870,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -891,8 +870,7 @@ UDItype __umulsidi3 (USItype, USItype);
"%1" ((USItype) (al)), \ "%1" ((USItype) (al)), \
"g" ((USItype) (bl))) "g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subw %5,%1 __asm__ ("subw %5,%1\n\tsubwb %3,%0" \
subwb %3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \ : "0" ((USItype) (ah)), \
...@@ -914,8 +892,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -914,8 +892,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("a %1,%5 __asm__ ("a %1,%5\n\tae %0,%3" \
ae %0,%3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \ : "%0" ((USItype) (ah)), \
...@@ -923,8 +900,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -923,8 +900,7 @@ UDItype __umulsidi3 (USItype, USItype);
"%1" ((USItype) (al)), \ "%1" ((USItype) (al)), \
"r" ((USItype) (bl))) "r" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("s %1,%5 __asm__ ("s %1,%5\n\tse %0,%3" \
se %0,%3" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \ : "0" ((USItype) (ah)), \
...@@ -935,26 +911,26 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -935,26 +911,26 @@ UDItype __umulsidi3 (USItype, USItype);
do { \ do { \
USItype __m0 = (m0), __m1 = (m1); \ USItype __m0 = (m0), __m1 = (m1); \
__asm__ ( \ __asm__ ( \
"s r2,r2 "s r2,r2\n" \
mts r10,%2 " mts r10,%2\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
m r2,%3 " m r2,%3\n" \
cas %0,r2,r0 " cas %0,r2,r0\n" \
mfs r10,%1" \ " mfs r10,%1" \
: "=r" ((USItype) (ph)), \ : "=r" ((USItype) (ph)), \
"=r" ((USItype) (pl)) \ "=r" ((USItype) (pl)) \
: "%r" (__m0), \ : "%r" (__m0), \
...@@ -984,9 +960,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -984,9 +960,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__sh2__) && W_TYPE_SIZE == 32 #if defined (__sh2__) && W_TYPE_SIZE == 32
#define umul_ppmm(w1, w0, u, v) \ #define umul_ppmm(w1, w0, u, v) \
__asm__ ( \ __asm__ ( \
"dmulu.l %2,%3 "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
sts macl,%1
sts mach,%0" \
: "=r" ((USItype)(w1)), \ : "=r" ((USItype)(w1)), \
"=r" ((USItype)(w0)) \ "=r" ((USItype)(w0)) \
: "r" ((USItype)(u)), \ : "r" ((USItype)(u)), \
...@@ -998,8 +972,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -998,8 +972,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \ #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
&& W_TYPE_SIZE == 32 && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %r4,%5,%1 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
addx %r2,%3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "%rJ" ((USItype) (ah)), \ : "%rJ" ((USItype) (ah)), \
...@@ -1008,8 +981,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1008,8 +981,7 @@ UDItype __umulsidi3 (USItype, USItype);
"rI" ((USItype) (bl)) \ "rI" ((USItype) (bl)) \
__CLOBBER_CC) __CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %r4,%5,%1 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
subx %r2,%3,%0" \
: "=r" ((USItype) (sh)), \ : "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \ "=&r" ((USItype) (sl)) \
: "rJ" ((USItype) (ah)), \ : "rJ" ((USItype) (ah)), \
...@@ -1042,45 +1014,45 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1042,45 +1014,45 @@ UDItype __umulsidi3 (USItype, USItype);
: "r" ((USItype) (u)), \ : "r" ((USItype) (u)), \
"r" ((USItype) (v))) "r" ((USItype) (v)))
#define udiv_qrnnd(q, r, n1, n0, d) \ #define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("! Inlined udiv_qrnnd __asm__ ("! Inlined udiv_qrnnd\n" \
wr %%g0,%2,%%y ! Not a delayed write for sparclite " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
tst %%g0 " tst %%g0\n" \
divscc %3,%4,%%g1 " divscc %3,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%%g1 " divscc %%g1,%4,%%g1\n" \
divscc %%g1,%4,%0 " divscc %%g1,%4,%0\n" \
rd %%y,%1 " rd %%y,%1\n" \
bl,a 1f " bl,a 1f\n" \
add %1,%4,%1 " add %1,%4,%1\n" \
1: ! End of inline udiv_qrnnd" \ "1: ! End of inline udiv_qrnnd" \
: "=r" ((USItype) (q)), \ : "=r" ((USItype) (q)), \
"=r" ((USItype) (r)) \ "=r" ((USItype) (r)) \
: "r" ((USItype) (n1)), \ : "r" ((USItype) (n1)), \
...@@ -1101,46 +1073,46 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1101,46 +1073,46 @@ UDItype __umulsidi3 (USItype, USItype);
/* SPARC without integer multiplication and divide instructions. /* SPARC without integer multiplication and divide instructions.
(i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */ (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
#define umul_ppmm(w1, w0, u, v) \ #define umul_ppmm(w1, w0, u, v) \
__asm__ ("! Inlined umul_ppmm __asm__ ("! Inlined umul_ppmm\n" \
wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
sra %3,31,%%o5 ! Don't move this insn " sra %3,31,%%o5 ! Don't move this insn\n" \
and %2,%%o5,%%o5 ! Don't move this insn " and %2,%%o5,%%o5 ! Don't move this insn\n" \
andcc %%g0,0,%%g1 ! Don't move this insn " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,%3,%%g1 " mulscc %%g1,%3,%%g1\n" \
mulscc %%g1,0,%%g1 " mulscc %%g1,0,%%g1\n" \
add %%g1,%%o5,%0 " add %%g1,%%o5,%0\n" \
rd %%y,%1" \ " rd %%y,%1" \
: "=r" ((USItype) (w1)), \ : "=r" ((USItype) (w1)), \
"=r" ((USItype) (w0)) \ "=r" ((USItype) (w0)) \
: "%rI" ((USItype) (u)), \ : "%rI" ((USItype) (u)), \
...@@ -1150,30 +1122,30 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1150,30 +1122,30 @@ UDItype __umulsidi3 (USItype, USItype);
/* It's quite necessary to add this much assembler for the sparc. /* It's quite necessary to add this much assembler for the sparc.
The default udiv_qrnnd (in C) is more than 10 times slower! */ The default udiv_qrnnd (in C) is more than 10 times slower! */
#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
__asm__ ("! Inlined udiv_qrnnd __asm__ ("! Inlined udiv_qrnnd\n" \
mov 32,%%g1 " mov 32,%%g1\n" \
subcc %1,%2,%%g0 " subcc %1,%2,%%g0\n" \
1: bcs 5f "1: bcs 5f\n" \
addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
sub %1,%2,%1 ! this kills msb of n " sub %1,%2,%1 ! this kills msb of n\n" \
addx %1,%1,%1 ! so this can't give carry " addx %1,%1,%1 ! so this can't give carry\n" \
subcc %%g1,1,%%g1 " subcc %%g1,1,%%g1\n" \
2: bne 1b "2: bne 1b\n" \
subcc %1,%2,%%g0 " subcc %1,%2,%%g0\n" \
bcs 3f " bcs 3f\n" \
addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
b 3f " b 3f\n" \
sub %1,%2,%1 ! this kills msb of n " sub %1,%2,%1 ! this kills msb of n\n" \
4: sub %1,%2,%1 "4: sub %1,%2,%1\n" \
5: addxcc %1,%1,%1 "5: addxcc %1,%1,%1\n" \
bcc 2b " bcc 2b\n" \
subcc %%g1,1,%%g1 " subcc %%g1,1,%%g1\n" \
! Got carry from n. Subtract next step to cancel this carry. "! Got carry from n. Subtract next step to cancel this carry.\n" \
bne 4b " bne 4b\n" \
addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
sub %1,%2,%1 " sub %1,%2,%1\n" \
3: xnor %0,0,%0 "3: xnor %0,0,%0\n" \
! End of inline udiv_qrnnd" \ " ! End of inline udiv_qrnnd" \
: "=&r" ((USItype) (__q)), \ : "=&r" ((USItype) (__q)), \
"=&r" ((USItype) (__r)) \ "=&r" ((USItype) (__r)) \
: "r" ((USItype) (__d)), \ : "r" ((USItype) (__d)), \
...@@ -1187,11 +1159,11 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1187,11 +1159,11 @@ UDItype __umulsidi3 (USItype, USItype);
#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \ #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
&& W_TYPE_SIZE == 64 && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %r4,%5,%1 __asm__ ("addcc %r4,%5,%1\n\t" \
add %r2,%3,%0 "add %r2,%3,%0\n\t" \
bcs,a,pn %%xcc, 1f "bcs,a,pn %%xcc, 1f\n\t" \
add %0, 1, %0 "add %0, 1, %0\n" \
1:" \ "1:" \
: "=r" ((UDItype)(sh)), \ : "=r" ((UDItype)(sh)), \
"=&r" ((UDItype)(sl)) \ "=&r" ((UDItype)(sl)) \
: "%rJ" ((UDItype)(ah)), \ : "%rJ" ((UDItype)(ah)), \
...@@ -1201,11 +1173,11 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1201,11 +1173,11 @@ UDItype __umulsidi3 (USItype, USItype);
__CLOBBER_CC) __CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %r4,%5,%1 __asm__ ("subcc %r4,%5,%1\n\t" \
sub %r2,%3,%0 "sub %r2,%3,%0\n\t" \
bcs,a,pn %%xcc, 1f "bcs,a,pn %%xcc, 1f\n\t" \
sub %0, 1, %0 "sub %0, 1, %0\n\t" \
1:" \ "1:" \
: "=r" ((UDItype)(sh)), \ : "=r" ((UDItype)(sh)), \
"=&r" ((UDItype)(sl)) \ "=&r" ((UDItype)(sl)) \
: "rJ" ((UDItype)(ah)), \ : "rJ" ((UDItype)(ah)), \
...@@ -1218,27 +1190,27 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1218,27 +1190,27 @@ UDItype __umulsidi3 (USItype, USItype);
do { \ do { \
UDItype tmp1, tmp2, tmp3, tmp4; \ UDItype tmp1, tmp2, tmp3, tmp4; \
__asm__ __volatile__ ( \ __asm__ __volatile__ ( \
"srl %7,0,%3 "srl %7,0,%3\n\t" \
mulx %3,%6,%1 "mulx %3,%6,%1\n\t" \
srlx %6,32,%2 "srlx %6,32,%2\n\t" \
mulx %2,%3,%4 "mulx %2,%3,%4\n\t" \
sllx %4,32,%5 "sllx %4,32,%5\n\t" \
srl %6,0,%3 "srl %6,0,%3\n\t" \
sub %1,%5,%5 "sub %1,%5,%5\n\t" \
srlx %5,32,%5 "srlx %5,32,%5\n\t" \
addcc %4,%5,%4 "addcc %4,%5,%4\n\t" \
srlx %7,32,%5 "srlx %7,32,%5\n\t" \
mulx %3,%5,%3 "mulx %3,%5,%3\n\t" \
mulx %2,%5,%5 "mulx %2,%5,%5\n\t" \
sethi %%hi(0x80000000),%2 "sethi %%hi(0x80000000),%2\n\t" \
addcc %4,%3,%4 "addcc %4,%3,%4\n\t" \
srlx %4,32,%4 "srlx %4,32,%4\n\t" \
add %2,%2,%2 "add %2,%2,%2\n\t" \
movcc %%xcc,%%g0,%2 "movcc %%xcc,%%g0,%2\n\t" \
addcc %5,%4,%5 "addcc %5,%4,%5\n\t" \
sllx %3,32,%3 "sllx %3,32,%3\n\t" \
add %1,%3,%1 "add %1,%3,%1\n\t" \
add %5,%2,%0" \ "add %5,%2,%0" \
: "=r" ((UDItype)(wh)), \ : "=r" ((UDItype)(wh)), \
"=&r" ((UDItype)(wl)), \ "=&r" ((UDItype)(wl)), \
"=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \ "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
...@@ -1252,8 +1224,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1252,8 +1224,7 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__vax__) && W_TYPE_SIZE == 32 #if defined (__vax__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl2 %5,%1 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
adwc %3,%0" \
: "=g" ((USItype) (sh)), \ : "=g" ((USItype) (sh)), \
"=&g" ((USItype) (sl)) \ "=&g" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \ : "%0" ((USItype) (ah)), \
...@@ -1261,8 +1232,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1261,8 +1232,7 @@ UDItype __umulsidi3 (USItype, USItype);
"%1" ((USItype) (al)), \ "%1" ((USItype) (al)), \
"g" ((USItype) (bl))) "g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subl2 %5,%1 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
sbwc %3,%0" \
: "=g" ((USItype) (sh)), \ : "=g" ((USItype) (sh)), \
"=&g" ((USItype) (sl)) \ "=&g" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \ : "0" ((USItype) (ah)), \
...@@ -1444,7 +1414,7 @@ UDItype __umulsidi3 (USItype, USItype); ...@@ -1444,7 +1414,7 @@ UDItype __umulsidi3 (USItype, USItype);
#endif #endif
#if !defined (count_leading_zeros) #if !defined (count_leading_zeros)
static const UQItype __clz_tab[]; extern const UQItype __clz_tab[];
#define count_leading_zeros(count, x) \ #define count_leading_zeros(count, x) \
do { \ do { \
UWtype __xr = (x); \ UWtype __xr = (x); \
......
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