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lvzhengyang
riscv-gcc-1
Commits
7d34a1b0
Commit
7d34a1b0
authored
Apr 04, 2011
by
Richard Sandiford
Committed by
Richard Sandiford
Apr 04, 2011
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pdp11.h (IRA_COVER_CLASSES): Delete.
gcc/ * config/pdp11/pdp11.h (IRA_COVER_CLASSES): Delete. From-SVN: r171929
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c30e7434
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gcc/ChangeLog
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7d34a1b0
2011-04-04 Richard Sandiford <richard.sandiford@linaro.org>
2011-04-04 Richard Sandiford <richard.sandiford@linaro.org>
* config/pdp11/pdp11.h (IRA_COVER_CLASSES): Delete.
2011-04-04 Richard Sandiford <richard.sandiford@linaro.org>
* config/vax/vax.c: Include reload.h.
* config/vax/vax.c: Include reload.h.
2011-04-04 Anatoly Sokolov <aesok@post.ru>
2011-04-04 Anatoly Sokolov <aesok@post.ru>
...
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gcc/config/pdp11/pdp11.h
View file @
7d34a1b0
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@@ -271,16 +271,6 @@ enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REG
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@@ -271,16 +271,6 @@ enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REG
#define INDEX_REG_CLASS GENERAL_REGS
#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS GENERAL_REGS
/* The following macro defines cover classes for Integrated Register
Allocator. Cover classes is a set of non-intersected register
classes covering all hard registers used for register allocation
purpose. Any move between two registers of a cover class should be
cheaper than load or store of the registers. The macro value is
array of register classes with LIM_REG_CLASSES used as the end
marker. */
#define IRA_COVER_CLASSES { GENERAL_REGS, FPU_REGS, LIM_REG_CLASSES }
/* Hook for testing if memory is needed for moving between registers. */
/* Hook for testing if memory is needed for moving between registers. */
#define SECONDARY_MEMORY_NEEDED(class1, class2, m) \
#define SECONDARY_MEMORY_NEEDED(class1, class2, m) \
pdp11_secondary_memory_needed (class1, class2, m)
pdp11_secondary_memory_needed (class1, class2, m)
...
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