Commit 7cc6af0c by Richard Henderson

re PR target/19005 (Error: bad register name `%sil')

        PR target/19005
        * config/i386/i386.md (swaphi_1): Swap with swaphi_2, allow with
        optimize_size.
        (swapqi_1): Rename from swapqi.  Enable only for no partial reg
        stall and optimize_size.
        (swapqi_2): New.
        (swaphi_1, swaphi_2, swapqi_1): Add athlon_decode.
        (swapsi, swaphi_1, swaphi_2, swapqi_1, swapdi): Remove modrm override.

From-SVN: r92250
parent 692308bb
2004-12-15 Richard Henderson <rth@redhat.com>
PR target/19005
* config/i386/i386.md (swaphi_1): Swap with swaphi_2, allow with
optimize_size.
(swapqi_1): Rename from swapqi. Enable only for no partial reg
stall and optimize_size.
(swapqi_2): New.
(swaphi_1, swaphi_2, swapqi_1): Add athlon_decode.
(swapsi, swaphi_1, swaphi_2, swapqi_1, swapdi): Remove modrm override.
2004-12-16 Uros Bizjak <uros@kss-loka.si> 2004-12-16 Uros Bizjak <uros@kss-loka.si>
* config/i386/i386.md (*floathisf2_i387, *floathidf2_i387): * config/i386/i386.md (*floathisf2_i387, *floathidf2_i387):
......
...@@ -1238,10 +1238,9 @@ ...@@ -1238,10 +1238,9 @@
"" ""
"xchg{l}\t%1, %0" "xchg{l}\t%1, %0"
[(set_attr "type" "imov") [(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
(set_attr "mode" "SI") (set_attr "mode" "SI")
(set_attr "modrm" "0")]) (set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")])
(define_expand "movhi" (define_expand "movhi"
[(set (match_operand:HI 0 "nonimmediate_operand" "") [(set (match_operand:HI 0 "nonimmediate_operand" "")
...@@ -1355,24 +1354,24 @@ ...@@ -1355,24 +1354,24 @@
(match_operand:HI 1 "register_operand" "+r")) (match_operand:HI 1 "register_operand" "+r"))
(set (match_dup 1) (set (match_dup 1)
(match_dup 0))] (match_dup 0))]
"TARGET_PARTIAL_REG_STALL" "!TARGET_PARTIAL_REG_STALL || optimize_size"
"xchg{w}\t%1, %0" "xchg{l}\t%k1, %k0"
[(set_attr "type" "imov") [(set_attr "type" "imov")
(set_attr "mode" "SI")
(set_attr "pent_pair" "np") (set_attr "pent_pair" "np")
(set_attr "mode" "HI") (set_attr "athlon_decode" "vector")])
(set_attr "modrm" "0")])
(define_insn "*swaphi_2" (define_insn "*swaphi_2"
[(set (match_operand:HI 0 "register_operand" "+r") [(set (match_operand:HI 0 "register_operand" "+r")
(match_operand:HI 1 "register_operand" "+r")) (match_operand:HI 1 "register_operand" "+r"))
(set (match_dup 1) (set (match_dup 1)
(match_dup 0))] (match_dup 0))]
"! TARGET_PARTIAL_REG_STALL" "TARGET_PARTIAL_REG_STALL"
"xchg{l}\t%k1, %k0" "xchg{w}\t%1, %0"
[(set_attr "type" "imov") [(set_attr "type" "imov")
(set_attr "mode" "HI")
(set_attr "pent_pair" "np") (set_attr "pent_pair" "np")
(set_attr "mode" "SI") (set_attr "athlon_decode" "vector")])
(set_attr "modrm" "0")])
(define_expand "movstricthi" (define_expand "movstricthi"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "")) [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
...@@ -1521,17 +1520,29 @@ ...@@ -1521,17 +1520,29 @@
DONE; DONE;
}) })
(define_insn "*swapqi" (define_insn "*swapqi_1"
[(set (match_operand:QI 0 "register_operand" "+r") [(set (match_operand:QI 0 "register_operand" "+r")
(match_operand:QI 1 "register_operand" "+r")) (match_operand:QI 1 "register_operand" "+r"))
(set (match_dup 1) (set (match_dup 1)
(match_dup 0))] (match_dup 0))]
"" "!TARGET_PARTIAL_REG_STALL || optimize_size"
"xchg{b}\t%1, %0" "xchg{l}\t%k1, %k0"
[(set_attr "type" "imov") [(set_attr "type" "imov")
(set_attr "mode" "SI")
(set_attr "pent_pair" "np") (set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")])
(define_insn "*swapqi_2"
[(set (match_operand:QI 0 "register_operand" "+q")
(match_operand:QI 1 "register_operand" "+q"))
(set (match_dup 1)
(match_dup 0))]
"TARGET_PARTIAL_REG_STALL"
"xchg{b}\t%1, %0"
[(set_attr "type" "imov")
(set_attr "mode" "QI") (set_attr "mode" "QI")
(set_attr "modrm" "0")]) (set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")])
(define_expand "movstrictqi" (define_expand "movstrictqi"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
...@@ -2094,11 +2105,9 @@ ...@@ -2094,11 +2105,9 @@
"TARGET_64BIT" "TARGET_64BIT"
"xchg{q}\t%1, %0" "xchg{q}\t%1, %0"
[(set_attr "type" "imov") [(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
(set_attr "mode" "DI") (set_attr "mode" "DI")
(set_attr "modrm" "0")]) (set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")])
(define_expand "movsf" (define_expand "movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "") [(set (match_operand:SF 0 "nonimmediate_operand" "")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment