Commit 7b1ac803 by Bernd Schmidt Committed by Bernd Schmidt

haifa-sched.c (schedule-block): Reorder the inner scheduling loop to reduce duplication...

	* haifa-sched.c (schedule-block): Reorder the inner scheduling loop
	to reduce duplication, and to achieve a slightly more logical order
	of operations.

From-SVN: r174271
parent 1aa9438f
2011-05-26 Bernd Schmidt <bernds@codesourcery.com>
* haifa-sched.c (schedule-block): Reorder the inner scheduling loop
to reduce duplication, and to achieve a slightly more logical order
of operations.
2011-05-26 Jakub Jelinek <jakub@redhat.com> 2011-05-26 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/49161 PR tree-optimization/49161
......
...@@ -3066,63 +3066,77 @@ schedule_block (basic_block *target_bb) ...@@ -3066,63 +3066,77 @@ schedule_block (basic_block *target_bb)
} }
while (advance > 0); while (advance > 0);
prune_ready_list (temp_state, true); if (ready.n_ready > 0)
prune_ready_list (temp_state, true);
if (ready.n_ready == 0) if (ready.n_ready == 0)
continue; continue;
if (sort_p) first_cycle_insn_p = true;
cycle_issued_insns = 0;
can_issue_more = issue_rate;
for (;;)
{ {
/* Sort the ready list based on priority. */ rtx insn;
ready_sort (&ready); int cost;
bool asm_p = false;
if (sched_verbose >= 2) if (sort_p && ready.n_ready > 0)
{ {
fprintf (sched_dump, ";;\t\tReady list after ready_sort: "); /* Sort the ready list based on priority. This must be
debug_ready_list (&ready); done every iteration through the loop, as schedule_insn
may have readied additional insns that will not be
sorted correctly. */
ready_sort (&ready);
if (sched_verbose >= 2)
{
fprintf (sched_dump, ";;\t\tReady list after ready_sort: ");
debug_ready_list (&ready);
}
} }
}
/* We don't want md sched reorder to even see debug isns, so put /* We don't want md sched reorder to even see debug isns, so put
them out right away. */ them out right away. */
if (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0))) if (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0))
{ && (*current_sched_info->schedule_more_p) ())
while (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
{ {
rtx insn = ready_remove_first (&ready); while (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
gcc_assert (DEBUG_INSN_P (insn)); {
(*current_sched_info->begin_schedule_ready) (insn); rtx insn = ready_remove_first (&ready);
VEC_safe_push (rtx, heap, scheduled_insns, insn); gcc_assert (DEBUG_INSN_P (insn));
last_scheduled_insn = insn; (*current_sched_info->begin_schedule_ready) (insn);
advance = schedule_insn (insn); VEC_safe_push (rtx, heap, scheduled_insns, insn);
gcc_assert (advance == 0); last_scheduled_insn = insn;
if (ready.n_ready > 0) advance = schedule_insn (insn);
ready_sort (&ready); gcc_assert (advance == 0);
if (ready.n_ready > 0)
ready_sort (&ready);
}
} }
if (!ready.n_ready) if (first_cycle_insn_p && !ready.n_ready)
continue; break;
}
/* Allow the target to reorder the list, typically for
better instruction bundling. */
if (sort_p && targetm.sched.reorder
&& (ready.n_ready == 0
|| !SCHED_GROUP_P (ready_element (&ready, 0))))
can_issue_more =
targetm.sched.reorder (sched_dump, sched_verbose,
ready_lastpos (&ready),
&ready.n_ready, clock_var);
else
can_issue_more = issue_rate;
first_cycle_insn_p = true; /* Allow the target to reorder the list, typically for
cycle_issued_insns = 0; better instruction bundling. */
for (;;) if (sort_p
{ && (ready.n_ready == 0
rtx insn; || !SCHED_GROUP_P (ready_element (&ready, 0))))
int cost; {
bool asm_p = false; if (first_cycle_insn_p && targetm.sched.reorder)
can_issue_more
= targetm.sched.reorder (sched_dump, sched_verbose,
ready_lastpos (&ready),
&ready.n_ready, clock_var);
else if (!first_cycle_insn_p && targetm.sched.reorder2)
can_issue_more
= targetm.sched.reorder2 (sched_dump, sched_verbose,
ready.n_ready
? ready_lastpos (&ready) : NULL,
&ready.n_ready, clock_var);
}
restart_choose_ready:
if (sched_verbose >= 2) if (sched_verbose >= 2)
{ {
fprintf (sched_dump, ";;\tReady list (t = %3d): ", fprintf (sched_dump, ";;\tReady list (t = %3d): ",
...@@ -3164,8 +3178,7 @@ schedule_block (basic_block *target_bb) ...@@ -3164,8 +3178,7 @@ schedule_block (basic_block *target_bb)
/* Finish cycle. */ /* Finish cycle. */
break; break;
if (res > 0) if (res > 0)
/* Restart choose_ready (). */ goto restart_choose_ready;
continue;
gcc_assert (insn != NULL_RTX); gcc_assert (insn != NULL_RTX);
} }
...@@ -3207,7 +3220,7 @@ schedule_block (basic_block *target_bb) ...@@ -3207,7 +3220,7 @@ schedule_block (basic_block *target_bb)
insn from the split block. */ insn from the split block. */
{ {
TODO_SPEC (insn) = (TODO_SPEC (insn) & ~SPECULATIVE) | HARD_DEP; TODO_SPEC (insn) = (TODO_SPEC (insn) & ~SPECULATIVE) | HARD_DEP;
continue; goto restart_choose_ready;
} }
/* DECISION is made. */ /* DECISION is made. */
...@@ -3256,45 +3269,8 @@ schedule_block (basic_block *target_bb) ...@@ -3256,45 +3269,8 @@ schedule_block (basic_block *target_bb)
break; break;
first_cycle_insn_p = false; first_cycle_insn_p = false;
if (ready.n_ready > 0)
prune_ready_list (temp_state, false);
/* Sort the ready list based on priority. This must be
redone here, as schedule_insn may have readied additional
insns that will not be sorted correctly. */
if (ready.n_ready > 0) if (ready.n_ready > 0)
ready_sort (&ready); prune_ready_list (temp_state, false);
/* Quickly go through debug insns such that md sched
reorder2 doesn't have to deal with debug insns. */
if (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0))
&& (*current_sched_info->schedule_more_p) ())
{
while (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
{
insn = ready_remove_first (&ready);
gcc_assert (DEBUG_INSN_P (insn));
(*current_sched_info->begin_schedule_ready) (insn);
VEC_safe_push (rtx, heap, scheduled_insns, insn);
advance = schedule_insn (insn);
last_scheduled_insn = insn;
gcc_assert (advance == 0);
if (ready.n_ready > 0)
ready_sort (&ready);
}
}
if (targetm.sched.reorder2
&& (ready.n_ready == 0
|| !SCHED_GROUP_P (ready_element (&ready, 0))))
{
can_issue_more =
targetm.sched.reorder2 (sched_dump, sched_verbose,
ready.n_ready
? ready_lastpos (&ready) : NULL,
&ready.n_ready, clock_var);
}
} }
} }
......
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