Commit 79f421e1 by Segher Boessenkool Committed by Segher Boessenkool

rs6000: Remove TARGET_ISEL64

TARGET_ISEL64 just means TARGET_ISEL && TARGET_POWERPC64.  Since
everywhere it is used uses :GPR already, we can just as well use
TARGET_ISEL always.


	* config/rs6000/rs6000.h (TARGET_ISEL64): Delete.
	* config/rs6000/rs6000.md (sel): Delete mode attribute.
	(mov<mode>cc, isel_signed_<mode>, isel_unsigned_<mode>,
	*isel_reversed_signed_<mode>, *isel_reversed_unsigned_<mode>): Use
	TARGET_ISEL instead of TARGET_ISEL<sel>.

From-SVN: r253671
parent 7c754ceb
2017-10-11 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.h (TARGET_ISEL64): Delete.
* config/rs6000/rs6000.md (sel): Delete mode attribute.
(mov<mode>cc, isel_signed_<mode>, isel_unsigned_<mode>,
*isel_reversed_signed_<mode>, *isel_reversed_unsigned_<mode>): Use
TARGET_ISEL instead of TARGET_ISEL<sel>.
2017-10-11 David Edelsohn <dje.gcc@gmail.com> 2017-10-11 David Edelsohn <dje.gcc@gmail.com>
* config/rs6000/rs6000.c * config/rs6000/rs6000.c
...@@ -565,8 +565,6 @@ extern int rs6000_vector_align[]; ...@@ -565,8 +565,6 @@ extern int rs6000_vector_align[];
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or Enable 32-bit fcfid's on any of the switches for newer ISA machines or
XILINX. */ XILINX. */
......
...@@ -578,9 +578,6 @@ ...@@ -578,9 +578,6 @@
; DImode bits ; DImode bits
(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
;; ISEL/ISEL64 target selection
(define_mode_attr sel [(SI "") (DI "64")])
;; Bitmask for shift instructions ;; Bitmask for shift instructions
(define_mode_attr hH [(SI "h") (DI "H")]) (define_mode_attr hH [(SI "h") (DI "H")])
...@@ -4915,7 +4912,7 @@ ...@@ -4915,7 +4912,7 @@
(if_then_else:GPR (match_operand 1 "comparison_operator" "") (if_then_else:GPR (match_operand 1 "comparison_operator" "")
(match_operand:GPR 2 "gpc_reg_operand" "") (match_operand:GPR 2 "gpc_reg_operand" "")
(match_operand:GPR 3 "gpc_reg_operand" "")))] (match_operand:GPR 3 "gpc_reg_operand" "")))]
"TARGET_ISEL<sel>" "TARGET_ISEL"
" "
{ {
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
...@@ -4940,7 +4937,7 @@ ...@@ -4940,7 +4937,7 @@
(const_int 0)]) (const_int 0)])
(match_operand:GPR 2 "reg_or_zero_operand" "O,b") (match_operand:GPR 2 "reg_or_zero_operand" "O,b")
(match_operand:GPR 3 "gpc_reg_operand" "r,r")))] (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
"TARGET_ISEL<sel>" "TARGET_ISEL"
"isel %0,%2,%3,%j1" "isel %0,%2,%3,%j1"
[(set_attr "type" "isel")]) [(set_attr "type" "isel")])
...@@ -4952,7 +4949,7 @@ ...@@ -4952,7 +4949,7 @@
(const_int 0)]) (const_int 0)])
(match_operand:GPR 2 "reg_or_zero_operand" "O,b") (match_operand:GPR 2 "reg_or_zero_operand" "O,b")
(match_operand:GPR 3 "gpc_reg_operand" "r,r")))] (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
"TARGET_ISEL<sel>" "TARGET_ISEL"
"isel %0,%2,%3,%j1" "isel %0,%2,%3,%j1"
[(set_attr "type" "isel")]) [(set_attr "type" "isel")])
...@@ -4968,7 +4965,7 @@ ...@@ -4968,7 +4965,7 @@
(const_int 0)]) (const_int 0)])
(match_operand:GPR 2 "gpc_reg_operand" "r,r") (match_operand:GPR 2 "gpc_reg_operand" "r,r")
(match_operand:GPR 3 "reg_or_zero_operand" "O,b")))] (match_operand:GPR 3 "reg_or_zero_operand" "O,b")))]
"TARGET_ISEL<sel>" "TARGET_ISEL"
{ {
PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1]))); PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
return "isel %0,%3,%2,%j1"; return "isel %0,%3,%2,%j1";
...@@ -4983,7 +4980,7 @@ ...@@ -4983,7 +4980,7 @@
(const_int 0)]) (const_int 0)])
(match_operand:GPR 2 "gpc_reg_operand" "r,r") (match_operand:GPR 2 "gpc_reg_operand" "r,r")
(match_operand:GPR 3 "reg_or_zero_operand" "O,b")))] (match_operand:GPR 3 "reg_or_zero_operand" "O,b")))]
"TARGET_ISEL<sel>" "TARGET_ISEL"
{ {
PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1]))); PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
return "isel %0,%3,%2,%j1"; return "isel %0,%3,%2,%j1";
......
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