Commit 76794c52 by Andreas Krebbel Committed by Andreas Krebbel

S/390: arch12: New builtins.

This patch implements a set of low-level builtins for instruction
which would otherwise not be emitted by the compiler plus a set of
high-level builtins as defined by the IBM XL compiler.  The high-level
builtins will be described in a future revision of the z/OS XL C/C++
Programming Guide.

I'll try to come up with a documentation appropriate for the GCC
manual as well (sometimes in the future).

gcc/ChangeLog:

2017-03-24  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390-builtins.def: Add VXE builtins.  Add a flags
	argument to the overloaded builtin variants.  Use the new flag to
	deprecate certain builtin variants.
	* config/s390/s390-builtin-types.def: Add new builtin types.
	* config/s390/s390-builtins.h: Support new flags field for
	overloaded builtins.
	* config/s390/s390-c.c (OB_DEF_VAR): New flags field.
	(s390_macro_to_expand): Enable vector float data type.
	(s390_cpu_cpp_builtins_internal): Indicate support of the new
	builtins by incrementing the __VEC__ version number.
	(s390_expand_overloaded_builtin): Support expansion of vec_xl and
	vec_xst.
	(s390_resolve_overloaded_builtin): Emit error messages depending
	on the builtin flags.
	* config/s390/s390.c (s390_expand_builtin): Support additional
	flags argument.  Change error message to match the messages
	emitted in s390-c.c.
	* config/s390/s390.md: New UNSPEC_* constants.
	(op_type): Add new instruction types.
	* config/s390/vecintrin.h: Add new builtins and test data class
	constants.
	* config/s390/vx-builtins.md (V_HW_32_64): Add V4SF.
	(V_HW_4, VEC_HW, VECF_HW): New mode iterators.
	(VEC_INEXACT, VEC_NOINEXACT): New constants.
	("vec_splats<mode>", "vec_insert<mode>", "vec_promote<mode>")
	("vec_insert_and_zero<mode>", "vec_mergeh<mode>")
	("vec_mergel<mode>"): V_HW -> VEC_HW.

	("vlrlrv16qi", "vstrlrv16qi", "vbpermv16qi", "vec_msumv2di")
	("vmslg", "*vftci<mode>_cconly", "vftci<mode>_intcconly")
	("*vftci<mode>", "vftci<mode>_intcc", "vec_double_s64")
	("vec_double_u64", "vfmin<mode>", "vfmax<mode>"): New definition.

	("and_av2df3", "and_cv2df3", "vec_andc_av2df3")
	("vec_andc_cv2df3", "xor_av2df3", "xor_cv2df3", "vec_nor_av2df3")
	("vec_nor_cv2df3", "ior_av2df3", "ior_cv2df3", "vec_nabs")
	("*vftcidb", "*vftcidb_cconly", "vftcidb"): Remove definition.

	("vec_all_<fpcmpcc:code>v2df", "vec_any_<fpcmpcc:code>v2df")
	("vec_scatter_elementv4si_DI", "vec_cmp<fpcmp:code>v2df")
	("vec_di_to_df_s64", "vec_di_to_df_u64", "vec_df_to_di_u64")
	("vfidb", "*vldeb", "*vledb", "*vec_cmp<insn_cmp>v2df_cconly")
	("vec_cmpeqv2df_cc", "vec_cmpeqv2df_cc", "vec_cmphv2df_cc")
	("vec_cmphev2df_cc", "*vec_cmpeqv2df_cc")
	("*vec_cmphv2df_cc", "*vec_cmphev2df_cc"): Enable new modes as ...

	("vec_all_<fpcmpcc:code><mode>", "vec_any_<fpcmpcc:code><mode>")
	("vec_scatter_element<V_HW_4:mode>_DI")
	("vec_cmp<fpcmp:code><mode>", "vcdgb", "vcdlgb", "vclgdb")
	("vec_fpint<mode>", "vflls")
	("vflrd", "*vec_cmp<insn_cmp><mode>_cconly", "vec_cmpeq<mode>_cc")
	("vec_cmpeq<mode>_cc", "vec_cmph<mode>_cc", "vec_cmphe<mode>_cc")
	("*vec_cmpeq<mode>_cc", "*vec_cmph<mode>_cc")
	("*vec_cmphe<mode>_cc"): ... these.

	("vec_ctd_s64", "vec_ctsl", "vec_ctul", "vec_st2f"): Use rounding
	mode constant instead of magic value.

gcc/testsuite/ChangeLog:

2017-03-24  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gcc.target/s390/target-attribute/tattr-3.c: Adjust error message
	and remove the high-level builtin.  The error message for the
	would prevent compilation from reaching the second.
	* gcc.target/s390/target-attribute/tattr-4.c: Likewise.

From-SVN: r246459
parent 2de2b3f9
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390-builtins.def: Add VXE builtins. Add a flags
argument to the overloaded builtin variants. Use the new flag to
deprecate certain builtin variants.
* config/s390/s390-builtin-types.def: Add new builtin types.
* config/s390/s390-builtins.h: Support new flags field for
overloaded builtins.
* config/s390/s390-c.c (OB_DEF_VAR): New flags field.
(s390_macro_to_expand): Enable vector float data type.
(s390_cpu_cpp_builtins_internal): Indicate support of the new
builtins by incrementing the __VEC__ version number.
(s390_expand_overloaded_builtin): Support expansion of vec_xl and
vec_xst.
(s390_resolve_overloaded_builtin): Emit error messages depending
on the builtin flags.
* config/s390/s390.c (s390_expand_builtin): Support additional
flags argument. Change error message to match the messages
emitted in s390-c.c.
* config/s390/s390.md: New UNSPEC_* constants.
(op_type): Add new instruction types.
* config/s390/vecintrin.h: Add new builtins and test data class
constants.
* config/s390/vx-builtins.md (V_HW_32_64): Add V4SF.
(V_HW_4, VEC_HW, VECF_HW): New mode iterators.
(VEC_INEXACT, VEC_NOINEXACT): New constants.
("vec_splats<mode>", "vec_insert<mode>", "vec_promote<mode>")
("vec_insert_and_zero<mode>", "vec_mergeh<mode>")
("vec_mergel<mode>"): V_HW -> VEC_HW.
("vlrlrv16qi", "vstrlrv16qi", "vbpermv16qi", "vec_msumv2di")
("vmslg", "*vftci<mode>_cconly", "vftci<mode>_intcconly")
("*vftci<mode>", "vftci<mode>_intcc", "vec_double_s64")
("vec_double_u64", "vfmin<mode>", "vfmax<mode>"): New definition.
("and_av2df3", "and_cv2df3", "vec_andc_av2df3")
("vec_andc_cv2df3", "xor_av2df3", "xor_cv2df3", "vec_nor_av2df3")
("vec_nor_cv2df3", "ior_av2df3", "ior_cv2df3", "vec_nabs")
("*vftcidb", "*vftcidb_cconly", "vftcidb"): Remove definition.
("vec_all_<fpcmpcc:code>v2df", "vec_any_<fpcmpcc:code>v2df")
("vec_scatter_elementv4si_DI", "vec_cmp<fpcmp:code>v2df")
("vec_di_to_df_s64", "vec_di_to_df_u64", "vec_df_to_di_u64")
("vfidb", "*vldeb", "*vledb", "*vec_cmp<insn_cmp>v2df_cconly")
("vec_cmpeqv2df_cc", "vec_cmpeqv2df_cc", "vec_cmphv2df_cc")
("vec_cmphev2df_cc", "*vec_cmpeqv2df_cc")
("*vec_cmphv2df_cc", "*vec_cmphev2df_cc"): Enable new modes as ...
("vec_all_<fpcmpcc:code><mode>", "vec_any_<fpcmpcc:code><mode>")
("vec_scatter_element<V_HW_4:mode>_DI")
("vec_cmp<fpcmp:code><mode>", "vcdgb", "vcdlgb", "vclgdb")
("vec_fpint<mode>", "vflls")
("vflrd", "*vec_cmp<insn_cmp><mode>_cconly", "vec_cmpeq<mode>_cc")
("vec_cmpeq<mode>_cc", "vec_cmph<mode>_cc", "vec_cmphe<mode>_cc")
("*vec_cmpeq<mode>_cc", "*vec_cmph<mode>_cc")
("*vec_cmphe<mode>_cc"): ... these.
("vec_ctd_s64", "vec_ctsl", "vec_ctul", "vec_st2f"): Use rounding
mode constant instead of magic value.
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.c (s390_expand_vec_compare): Support other
vector floating point modes than just V2DF.
(s390_expand_vcond): Likewise.
......
......@@ -54,73 +54,74 @@
s390_builtin_types[T6])
DEF_TYPE (BT_INT, integer_type_node, 0)
DEF_TYPE (BT_VOID, void_type_node, 0)
DEF_TYPE (BT_FLTCONST, float_type_node, 1)
DEF_TYPE (BT_ULONG, long_unsigned_type_node, 0)
DEF_TYPE (BT_UINT64, c_uint64_type_node, 0)
DEF_TYPE (BT_FLT, float_type_node, 0)
DEF_TYPE (BT_INT128, intTI_type_node, 0)
DEF_TYPE (BT_UINT, unsigned_type_node, 0)
DEF_TYPE (BT_VOIDCONST, void_type_node, 1)
DEF_TYPE (BT_ULONG, long_unsigned_type_node, 0)
DEF_TYPE (BT_INT128, intTI_type_node, 0)
DEF_TYPE (BT_USHORTCONST, short_unsigned_type_node, 1)
DEF_TYPE (BT_SHORTCONST, short_integer_type_node, 1)
DEF_TYPE (BT_INTCONST, integer_type_node, 1)
DEF_TYPE (BT_UCHARCONST, unsigned_char_type_node, 1)
DEF_TYPE (BT_UCHAR, unsigned_char_type_node, 0)
DEF_TYPE (BT_INTCONST, integer_type_node, 1)
DEF_TYPE (BT_SCHARCONST, signed_char_type_node, 1)
DEF_TYPE (BT_UCHAR, unsigned_char_type_node, 0)
DEF_TYPE (BT_SHORT, short_integer_type_node, 0)
DEF_TYPE (BT_LONG, long_integer_type_node, 0)
DEF_TYPE (BT_SCHAR, signed_char_type_node, 0)
DEF_TYPE (BT_ULONGLONGCONST, long_long_unsigned_type_node, 1)
DEF_TYPE (BT_USHORT, short_unsigned_type_node, 0)
DEF_TYPE (BT_LONGLONG, long_long_integer_type_node, 0)
DEF_TYPE (BT_DBLCONST, double_type_node, 1)
DEF_TYPE (BT_ULONGLONG, long_long_unsigned_type_node, 0)
DEF_TYPE (BT_DBLCONST, double_type_node, 1)
DEF_TYPE (BT_FLT, float_type_node, 0)
DEF_TYPE (BT_DBL, double_type_node, 0)
DEF_TYPE (BT_FLTCONST, float_type_node, 1)
DEF_TYPE (BT_ULONGLONGCONST, long_long_unsigned_type_node, 1)
DEF_TYPE (BT_LONGLONG, long_long_integer_type_node, 0)
DEF_TYPE (BT_LONGLONGCONST, long_long_integer_type_node, 1)
DEF_TYPE (BT_UINTCONST, unsigned_type_node, 1)
DEF_VECTOR_TYPE (BT_UV2DI, BT_ULONGLONG, 2)
DEF_VECTOR_TYPE (BT_V4SI, BT_INT, 4)
DEF_VECTOR_TYPE (BT_V2DI, BT_LONGLONG, 2)
DEF_VECTOR_TYPE (BT_V8HI, BT_SHORT, 8)
DEF_VECTOR_TYPE (BT_V4SI, BT_INT, 4)
DEF_VECTOR_TYPE (BT_UV4SI, BT_UINT, 4)
DEF_VECTOR_TYPE (BT_V16QI, BT_SCHAR, 16)
DEF_VECTOR_TYPE (BT_V2DF, BT_DBL, 2)
DEF_VECTOR_TYPE (BT_V2DI, BT_LONGLONG, 2)
DEF_VECTOR_TYPE (BT_UV8HI, BT_USHORT, 8)
DEF_VECTOR_TYPE (BT_V4SF, BT_FLT, 4)
DEF_VECTOR_TYPE (BT_V2DF, BT_DBL, 2)
DEF_VECTOR_TYPE (BT_UV16QI, BT_UCHAR, 16)
DEF_POINTER_TYPE (BT_UCHARPTR, BT_UCHAR)
DEF_POINTER_TYPE (BT_DBLCONSTPTR, BT_DBLCONST)
DEF_POINTER_TYPE (BT_USHORTPTR, BT_USHORT)
DEF_POINTER_TYPE (BT_UINTCONSTPTR, BT_UINTCONST)
DEF_POINTER_TYPE (BT_VOIDPTR, BT_VOID)
DEF_POINTER_TYPE (BT_FLTPTR, BT_FLT)
DEF_POINTER_TYPE (BT_ULONGLONGCONSTPTR, BT_ULONGLONGCONST)
DEF_POINTER_TYPE (BT_UINT64PTR, BT_UINT64)
DEF_POINTER_TYPE (BT_FLTCONSTPTR, BT_FLTCONST)
DEF_POINTER_TYPE (BT_USHORTCONSTPTR, BT_USHORTCONST)
DEF_POINTER_TYPE (BT_SCHARPTR, BT_SCHAR)
DEF_POINTER_TYPE (BT_UINTCONSTPTR, BT_UINTCONST)
DEF_POINTER_TYPE (BT_ULONGLONGCONSTPTR, BT_ULONGLONGCONST)
DEF_POINTER_TYPE (BT_UCHARPTR, BT_UCHAR)
DEF_POINTER_TYPE (BT_VOIDCONSTPTR, BT_VOIDCONST)
DEF_POINTER_TYPE (BT_LONGLONGCONSTPTR, BT_LONGLONGCONST)
DEF_POINTER_TYPE (BT_SHORTPTR, BT_SHORT)
DEF_POINTER_TYPE (BT_USHORTPTR, BT_USHORT)
DEF_POINTER_TYPE (BT_DBLCONSTPTR, BT_DBLCONST)
DEF_POINTER_TYPE (BT_INTPTR, BT_INT)
DEF_POINTER_TYPE (BT_INTCONSTPTR, BT_INTCONST)
DEF_POINTER_TYPE (BT_UINTPTR, BT_UINT)
DEF_POINTER_TYPE (BT_LONGLONGPTR, BT_LONGLONG)
DEF_POINTER_TYPE (BT_ULONGLONGPTR, BT_ULONGLONG)
DEF_POINTER_TYPE (BT_INTCONSTPTR, BT_INTCONST)
DEF_POINTER_TYPE (BT_DBLPTR, BT_DBL)
DEF_POINTER_TYPE (BT_VOIDCONSTPTR, BT_VOIDCONST)
DEF_POINTER_TYPE (BT_USHORTCONSTPTR, BT_USHORTCONST)
DEF_POINTER_TYPE (BT_SHORTCONSTPTR, BT_SHORTCONST)
DEF_POINTER_TYPE (BT_UCHARCONSTPTR, BT_UCHARCONST)
DEF_POINTER_TYPE (BT_FLTCONSTPTR, BT_FLTCONST)
DEF_POINTER_TYPE (BT_SCHARCONSTPTR, BT_SCHARCONST)
DEF_POINTER_TYPE (BT_UINTPTR, BT_UINT)
DEF_DISTINCT_TYPE (BT_BLONGLONG, BT_ULONGLONG)
DEF_DISTINCT_TYPE (BT_BINT, BT_UINT)
DEF_DISTINCT_TYPE (BT_BSHORT, BT_USHORT)
DEF_POINTER_TYPE (BT_FLTPTR, BT_FLT)
DEF_DISTINCT_TYPE (BT_BCHAR, BT_UCHAR)
DEF_OPAQUE_VECTOR_TYPE (BT_OV2DI, BT_LONGLONG, 2)
DEF_OPAQUE_VECTOR_TYPE (BT_BV16QI, BT_BCHAR, 16)
DEF_DISTINCT_TYPE (BT_BSHORT, BT_USHORT)
DEF_DISTINCT_TYPE (BT_BINT, BT_UINT)
DEF_DISTINCT_TYPE (BT_BLONGLONG, BT_ULONGLONG)
DEF_OPAQUE_VECTOR_TYPE (BT_BV8HI, BT_BSHORT, 8)
DEF_OPAQUE_VECTOR_TYPE (BT_OV4SI, BT_INT, 4)
DEF_OPAQUE_VECTOR_TYPE (BT_BV16QI, BT_BCHAR, 16)
DEF_OPAQUE_VECTOR_TYPE (BT_BV2DI, BT_BLONGLONG, 2)
DEF_OPAQUE_VECTOR_TYPE (BT_OV2DI, BT_LONGLONG, 2)
DEF_OPAQUE_VECTOR_TYPE (BT_OUV4SI, BT_UINT, 4)
DEF_OPAQUE_VECTOR_TYPE (BT_BV4SI, BT_BINT, 4)
DEF_OPAQUE_VECTOR_TYPE (BT_BV2DI, BT_BLONGLONG, 2)
DEF_OPAQUE_VECTOR_TYPE (BT_BV8HI, BT_BSHORT, 8)
DEF_FN_TYPE_0 (BT_FN_INT, BT_INT)
DEF_FN_TYPE_0 (BT_FN_UINT, BT_UINT)
DEF_FN_TYPE_1 (BT_FN_INT_INT, BT_INT, BT_INT)
......@@ -150,13 +151,20 @@ DEF_FN_TYPE_1 (BT_FN_V16QI_SCHAR, BT_V16QI, BT_SCHAR)
DEF_FN_TYPE_1 (BT_FN_V16QI_UCHAR, BT_V16QI, BT_UCHAR)
DEF_FN_TYPE_1 (BT_FN_V16QI_V16QI, BT_V16QI, BT_V16QI)
DEF_FN_TYPE_1 (BT_FN_V2DF_DBL, BT_V2DF, BT_DBL)
DEF_FN_TYPE_1 (BT_FN_V2DF_DBLCONSTPTR, BT_V2DF, BT_DBLCONSTPTR)
DEF_FN_TYPE_1 (BT_FN_V2DF_FLTCONSTPTR, BT_V2DF, BT_FLTCONSTPTR)
DEF_FN_TYPE_1 (BT_FN_V2DF_UV2DI, BT_V2DF, BT_UV2DI)
DEF_FN_TYPE_1 (BT_FN_V2DF_V2DF, BT_V2DF, BT_V2DF)
DEF_FN_TYPE_1 (BT_FN_V2DF_V2DI, BT_V2DF, BT_V2DI)
DEF_FN_TYPE_1 (BT_FN_V2DF_V4SF, BT_V2DF, BT_V4SF)
DEF_FN_TYPE_1 (BT_FN_V2DI_SHORT, BT_V2DI, BT_SHORT)
DEF_FN_TYPE_1 (BT_FN_V2DI_V16QI, BT_V2DI, BT_V16QI)
DEF_FN_TYPE_1 (BT_FN_V2DI_V2DI, BT_V2DI, BT_V2DI)
DEF_FN_TYPE_1 (BT_FN_V2DI_V4SI, BT_V2DI, BT_V4SI)
DEF_FN_TYPE_1 (BT_FN_V2DI_V8HI, BT_V2DI, BT_V8HI)
DEF_FN_TYPE_1 (BT_FN_V4SF_FLT, BT_V4SF, BT_FLT)
DEF_FN_TYPE_1 (BT_FN_V4SF_FLTCONSTPTR, BT_V4SF, BT_FLTCONSTPTR)
DEF_FN_TYPE_1 (BT_FN_V4SF_V4SF, BT_V4SF, BT_V4SF)
DEF_FN_TYPE_1 (BT_FN_V4SI_SHORT, BT_V4SI, BT_SHORT)
DEF_FN_TYPE_1 (BT_FN_V4SI_V4SI, BT_V4SI, BT_V4SI)
DEF_FN_TYPE_1 (BT_FN_V4SI_V8HI, BT_V4SI, BT_V8HI)
......@@ -166,6 +174,7 @@ DEF_FN_TYPE_1 (BT_FN_V8HI_V8HI, BT_V8HI, BT_V8HI)
DEF_FN_TYPE_1 (BT_FN_VOID_INT, BT_VOID, BT_INT)
DEF_FN_TYPE_1 (BT_FN_VOID_UINT, BT_VOID, BT_UINT)
DEF_FN_TYPE_2 (BT_FN_DBL_V2DF_INT, BT_DBL, BT_V2DF, BT_INT)
DEF_FN_TYPE_2 (BT_FN_FLT_V4SF_INT, BT_FLT, BT_V4SF, BT_INT)
DEF_FN_TYPE_2 (BT_FN_INT128_INT128_INT128, BT_INT128, BT_INT128, BT_INT128)
DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_INT, BT_INT, BT_OV4SI, BT_INT)
DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_OV4SI, BT_INT, BT_OV4SI, BT_OV4SI)
......@@ -176,6 +185,7 @@ DEF_FN_TYPE_2 (BT_FN_INT_UV8HI_UV8HI, BT_INT, BT_UV8HI, BT_UV8HI)
DEF_FN_TYPE_2 (BT_FN_INT_V16QI_V16QI, BT_INT, BT_V16QI, BT_V16QI)
DEF_FN_TYPE_2 (BT_FN_INT_V2DF_V2DF, BT_INT, BT_V2DF, BT_V2DF)
DEF_FN_TYPE_2 (BT_FN_INT_V2DI_V2DI, BT_INT, BT_V2DI, BT_V2DI)
DEF_FN_TYPE_2 (BT_FN_INT_V4SF_V4SF, BT_INT, BT_V4SF, BT_V4SF)
DEF_FN_TYPE_2 (BT_FN_INT_V4SI_V4SI, BT_INT, BT_V4SI, BT_V4SI)
DEF_FN_TYPE_2 (BT_FN_INT_V8HI_V8HI, BT_INT, BT_V8HI, BT_V8HI)
DEF_FN_TYPE_2 (BT_FN_INT_VOIDPTR_INT, BT_INT, BT_VOIDPTR, BT_INT)
......@@ -204,6 +214,7 @@ DEF_FN_TYPE_2 (BT_FN_UV16QI_UV4SI_UV4SI, BT_UV16QI, BT_UV4SI, BT_UV4SI)
DEF_FN_TYPE_2 (BT_FN_UV16QI_UV8HI_UV8HI, BT_UV16QI, BT_UV8HI, BT_UV8HI)
DEF_FN_TYPE_2 (BT_FN_UV2DI_UCHAR_UCHAR, BT_UV2DI, BT_UCHAR, BT_UCHAR)
DEF_FN_TYPE_2 (BT_FN_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_ULONGLONG, BT_INT)
DEF_FN_TYPE_2 (BT_FN_UV2DI_UV16QI_UV16QI, BT_UV2DI, BT_UV16QI, BT_UV16QI)
DEF_FN_TYPE_2 (BT_FN_UV2DI_UV2DI_UCHAR, BT_UV2DI, BT_UV2DI, BT_UCHAR)
DEF_FN_TYPE_2 (BT_FN_UV2DI_UV2DI_UINT, BT_UV2DI, BT_UV2DI, BT_UINT)
DEF_FN_TYPE_2 (BT_FN_UV2DI_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI)
......@@ -235,6 +246,7 @@ DEF_FN_TYPE_2 (BT_FN_V16QI_V8HI_V8HI, BT_V16QI, BT_V8HI, BT_V8HI)
DEF_FN_TYPE_2 (BT_FN_V2DF_DBL_INT, BT_V2DF, BT_DBL, BT_INT)
DEF_FN_TYPE_2 (BT_FN_V2DF_UV2DI_INT, BT_V2DF, BT_UV2DI, BT_INT)
DEF_FN_TYPE_2 (BT_FN_V2DF_UV4SI_INT, BT_V2DF, BT_UV4SI, BT_INT)
DEF_FN_TYPE_2 (BT_FN_V2DF_V2DF_UCHAR, BT_V2DF, BT_V2DF, BT_UCHAR)
DEF_FN_TYPE_2 (BT_FN_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF)
DEF_FN_TYPE_2 (BT_FN_V2DF_V2DI_INT, BT_V2DF, BT_V2DI, BT_INT)
DEF_FN_TYPE_2 (BT_FN_V2DI_BV2DI_V2DI, BT_V2DI, BT_BV2DI, BT_V2DI)
......@@ -243,10 +255,14 @@ DEF_FN_TYPE_2 (BT_FN_V2DI_V2DF_INT, BT_V2DI, BT_V2DF, BT_INT)
DEF_FN_TYPE_2 (BT_FN_V2DI_V2DF_V2DF, BT_V2DI, BT_V2DF, BT_V2DF)
DEF_FN_TYPE_2 (BT_FN_V2DI_V2DI_V2DI, BT_V2DI, BT_V2DI, BT_V2DI)
DEF_FN_TYPE_2 (BT_FN_V2DI_V4SI_V4SI, BT_V2DI, BT_V4SI, BT_V4SI)
DEF_FN_TYPE_2 (BT_FN_V4SF_FLT_INT, BT_V4SF, BT_FLT, BT_INT)
DEF_FN_TYPE_2 (BT_FN_V4SF_V4SF_UCHAR, BT_V4SF, BT_V4SF, BT_UCHAR)
DEF_FN_TYPE_2 (BT_FN_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF)
DEF_FN_TYPE_2 (BT_FN_V4SI_BV4SI_V4SI, BT_V4SI, BT_BV4SI, BT_V4SI)
DEF_FN_TYPE_2 (BT_FN_V4SI_INT_VOIDPTR, BT_V4SI, BT_INT, BT_VOIDPTR)
DEF_FN_TYPE_2 (BT_FN_V4SI_UV4SI_UV4SI, BT_V4SI, BT_UV4SI, BT_UV4SI)
DEF_FN_TYPE_2 (BT_FN_V4SI_V2DI_V2DI, BT_V4SI, BT_V2DI, BT_V2DI)
DEF_FN_TYPE_2 (BT_FN_V4SI_V4SF_V4SF, BT_V4SI, BT_V4SF, BT_V4SF)
DEF_FN_TYPE_2 (BT_FN_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI)
DEF_FN_TYPE_2 (BT_FN_V4SI_V8HI_V8HI, BT_V4SI, BT_V8HI, BT_V8HI)
DEF_FN_TYPE_2 (BT_FN_V8HI_BV8HI_V8HI, BT_V8HI, BT_BV8HI, BT_V8HI)
......@@ -256,9 +272,12 @@ DEF_FN_TYPE_2 (BT_FN_V8HI_V4SI_V4SI, BT_V8HI, BT_V4SI, BT_V4SI)
DEF_FN_TYPE_2 (BT_FN_V8HI_V8HI_V8HI, BT_V8HI, BT_V8HI, BT_V8HI)
DEF_FN_TYPE_2 (BT_FN_VOID_UINT64PTR_UINT64, BT_VOID, BT_UINT64PTR, BT_UINT64)
DEF_FN_TYPE_2 (BT_FN_VOID_V2DF_FLTPTR, BT_VOID, BT_V2DF, BT_FLTPTR)
DEF_FN_TYPE_3 (BT_FN_BV2DI_V2DF_USHORT_INTPTR, BT_BV2DI, BT_V2DF, BT_USHORT, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_BV4SI_V4SF_USHORT_INTPTR, BT_BV4SI, BT_V4SF, BT_USHORT, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_INT128_INT128_INT128_INT128, BT_INT128, BT_INT128, BT_INT128, BT_INT128)
DEF_FN_TYPE_3 (BT_FN_INT_OV4SI_OV4SI_INTPTR, BT_INT, BT_OV4SI, BT_OV4SI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_OV4SI_INT_OV4SI_INT, BT_OV4SI, BT_INT, BT_OV4SI, BT_INT)
DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_INT_INTPTR, BT_OV4SI, BT_OV4SI, BT_INT, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_INT, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INT)
DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_INTPTR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI)
......@@ -273,6 +292,7 @@ DEF_FN_TYPE_3 (BT_FN_UV16QI_UV8HI_UV8HI_INTPTR, BT_UV16QI, BT_UV8HI, BT_UV8HI, B
DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_UV2DI, BT_ULONGLONG, BT_INT)
DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_INT)
DEF_FN_TYPE_3 (BT_FN_UV2DI_UV4SI_UV4SI_UV2DI, BT_UV2DI, BT_UV4SI, BT_UV4SI, BT_UV2DI)
DEF_FN_TYPE_3 (BT_FN_UV2DI_V2DF_INT_INT, BT_UV2DI, BT_V2DF, BT_INT, BT_INT)
DEF_FN_TYPE_3 (BT_FN_UV4SI_UV2DI_UV2DI_INTPTR, BT_UV4SI, BT_UV2DI, BT_UV2DI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UINT_INT, BT_UV4SI, BT_UV4SI, BT_UINT, BT_INT)
DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UV4SI_INT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT)
......@@ -289,16 +309,27 @@ DEF_FN_TYPE_3 (BT_FN_V16QI_UV16QI_UV16QI_INTPTR, BT_V16QI, BT_UV16QI, BT_UV16QI,
DEF_FN_TYPE_3 (BT_FN_V16QI_V16QI_V16QI_INTPTR, BT_V16QI, BT_V16QI, BT_V16QI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V16QI_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_V16QI)
DEF_FN_TYPE_3 (BT_FN_V16QI_V8HI_V8HI_INTPTR, BT_V16QI, BT_V8HI, BT_V8HI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V2DF_UV2DI_INT_INT, BT_V2DF, BT_UV2DI, BT_INT, BT_INT)
DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_DBL_INT, BT_V2DF, BT_V2DF, BT_DBL, BT_INT)
DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_UCHAR_UCHAR, BT_V2DF, BT_V2DF, BT_UCHAR, BT_UCHAR)
DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_V2DF_INT, BT_V2DF, BT_V2DF, BT_V2DF, BT_INT)
DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF, BT_V2DF)
DEF_FN_TYPE_3 (BT_FN_V2DF_V2DI_INT_INT, BT_V2DF, BT_V2DI, BT_INT, BT_INT)
DEF_FN_TYPE_3 (BT_FN_V2DI_UV2DI_UV2DI_INTPTR, BT_V2DI, BT_UV2DI, BT_UV2DI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V2DI_V2DF_INT_INT, BT_V2DI, BT_V2DF, BT_INT, BT_INT)
DEF_FN_TYPE_3 (BT_FN_V2DI_V2DF_INT_INTPTR, BT_V2DI, BT_V2DF, BT_INT, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V2DI_V2DF_V2DF_INTPTR, BT_V2DI, BT_V2DF, BT_V2DF, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V2DI_V2DI_V2DI_INTPTR, BT_V2DI, BT_V2DI, BT_V2DI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V2DI_V4SI_V4SI_V2DI, BT_V2DI, BT_V4SI, BT_V4SI, BT_V2DI)
DEF_FN_TYPE_3 (BT_FN_V4SF_V2DF_INT_INT, BT_V4SF, BT_V2DF, BT_INT, BT_INT)
DEF_FN_TYPE_3 (BT_FN_V4SF_V4SF_FLT_INT, BT_V4SF, BT_V4SF, BT_FLT, BT_INT)
DEF_FN_TYPE_3 (BT_FN_V4SF_V4SF_UCHAR_UCHAR, BT_V4SF, BT_V4SF, BT_UCHAR, BT_UCHAR)
DEF_FN_TYPE_3 (BT_FN_V4SF_V4SF_V4SF_INT, BT_V4SF, BT_V4SF, BT_V4SF, BT_INT)
DEF_FN_TYPE_3 (BT_FN_V4SF_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF, BT_V4SF)
DEF_FN_TYPE_3 (BT_FN_V4SI_UV4SI_UV4SI_INTPTR, BT_V4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V4SI_V2DI_V2DI_INTPTR, BT_V4SI, BT_V2DI, BT_V2DI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V4SI_V4SF_INT_INTPTR, BT_V4SI, BT_V4SF, BT_INT, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V4SI_V4SF_V4SF_INTPTR, BT_V4SI, BT_V4SF, BT_V4SF, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V4SI_V4SI_V4SI_INTPTR, BT_V4SI, BT_V4SI, BT_V4SI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_V4SI_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_V4SI)
DEF_FN_TYPE_3 (BT_FN_V4SI_V8HI_V8HI_V4SI, BT_V4SI, BT_V8HI, BT_V8HI, BT_V4SI)
......@@ -310,10 +341,12 @@ DEF_FN_TYPE_3 (BT_FN_V8HI_V8HI_V8HI_V8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_V8HI)
DEF_FN_TYPE_3 (BT_FN_VOID_OV4SI_INT_VOIDPTR, BT_VOID, BT_OV4SI, BT_INT, BT_VOIDPTR)
DEF_FN_TYPE_3 (BT_FN_VOID_OV4SI_VOIDPTR_UINT, BT_VOID, BT_OV4SI, BT_VOIDPTR, BT_UINT)
DEF_FN_TYPE_3 (BT_FN_VOID_V16QI_UINT_VOIDPTR, BT_VOID, BT_V16QI, BT_UINT, BT_VOIDPTR)
DEF_FN_TYPE_4 (BT_FN_INT128_UV2DI_UV2DI_INT128_INT, BT_INT128, BT_UV2DI, BT_UV2DI, BT_INT128, BT_INT)
DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OUV4SI_INTCONSTPTR_UCHAR, BT_OV4SI, BT_OV4SI, BT_OUV4SI, BT_INTCONSTPTR, BT_UCHAR)
DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INTPTR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INTPTR)
DEF_FN_TYPE_4 (BT_FN_UV16QI_UV16QI_UV16QI_INT_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT, BT_INTPTR)
DEF_FN_TYPE_4 (BT_FN_UV16QI_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT)
DEF_FN_TYPE_4 (BT_FN_UV16QI_UV2DI_UV2DI_UV16QI_INT, BT_UV16QI, BT_UV2DI, BT_UV2DI, BT_UV16QI, BT_INT)
DEF_FN_TYPE_4 (BT_FN_UV2DI_UV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONGCONSTPTR, BT_UCHAR)
DEF_FN_TYPE_4 (BT_FN_UV2DI_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_INT)
DEF_FN_TYPE_4 (BT_FN_UV4SI_UV4SI_UV4SI_INT_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT, BT_INTPTR)
......@@ -331,6 +364,7 @@ DEF_OV_TYPE (BT_OV_BV16QI_BV16QI, BT_BV16QI, BT_BV16QI)
DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI, BT_BV16QI, BT_BV16QI, BT_BV16QI)
DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_BV16QI, BT_BV16QI, BT_BV16QI, BT_BV16QI, BT_BV16QI)
DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_INTPTR, BT_BV16QI, BT_BV16QI, BT_BV16QI, BT_INTPTR)
DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_ULONGLONG, BT_BV16QI, BT_BV16QI, BT_BV16QI, BT_ULONGLONG)
DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_UV16QI, BT_BV16QI, BT_BV16QI, BT_BV16QI, BT_UV16QI)
DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_INTPTR, BT_BV16QI, BT_BV16QI, BT_INTPTR)
DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_UCHAR, BT_BV16QI, BT_BV16QI, BT_UCHAR)
......@@ -347,6 +381,7 @@ DEF_OV_TYPE (BT_OV_BV16QI_V16QI_V16QI_INTPTR, BT_BV16QI, BT_V16QI, BT_V16QI, BT_
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI)
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI)
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_INT, BT_BV2DI, BT_BV2DI, BT_BV2DI, BT_INT)
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_ULONGLONG, BT_BV2DI, BT_BV2DI, BT_BV2DI, BT_ULONGLONG)
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_UV16QI, BT_BV2DI, BT_BV2DI, BT_BV2DI, BT_UV16QI)
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_UV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI, BT_UV2DI)
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_UCHAR, BT_BV2DI, BT_BV2DI, BT_UCHAR)
......@@ -356,6 +391,7 @@ DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_UV4SI, BT_BV2DI, BT_BV2DI, BT_UV4SI)
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_UV8HI, BT_BV2DI, BT_BV2DI, BT_UV8HI)
DEF_OV_TYPE (BT_OV_BV2DI_BV4SI, BT_BV2DI, BT_BV4SI)
DEF_OV_TYPE (BT_OV_BV2DI_UV2DI_UV2DI, BT_BV2DI, BT_UV2DI, BT_UV2DI)
DEF_OV_TYPE (BT_OV_BV2DI_V2DF_USHORT_INTPTR, BT_BV2DI, BT_V2DF, BT_USHORT, BT_INTPTR)
DEF_OV_TYPE (BT_OV_BV2DI_V2DF_V2DF, BT_BV2DI, BT_V2DF, BT_V2DF)
DEF_OV_TYPE (BT_OV_BV2DI_V2DI_V2DI, BT_BV2DI, BT_V2DI, BT_V2DI)
DEF_OV_TYPE (BT_OV_BV4SI_BV2DI_BV2DI, BT_BV4SI, BT_BV2DI, BT_BV2DI)
......@@ -363,6 +399,7 @@ DEF_OV_TYPE (BT_OV_BV4SI_BV4SI, BT_BV4SI, BT_BV4SI)
DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI, BT_BV4SI, BT_BV4SI, BT_BV4SI)
DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI_BV4SI, BT_BV4SI, BT_BV4SI, BT_BV4SI, BT_BV4SI)
DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI_INTPTR, BT_BV4SI, BT_BV4SI, BT_BV4SI, BT_INTPTR)
DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI_ULONGLONG, BT_BV4SI, BT_BV4SI, BT_BV4SI, BT_ULONGLONG)
DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI_UV16QI, BT_BV4SI, BT_BV4SI, BT_BV4SI, BT_UV16QI)
DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_BV4SI_UV4SI, BT_BV4SI, BT_BV4SI, BT_BV4SI, BT_UV4SI)
DEF_OV_TYPE (BT_OV_BV4SI_BV4SI_INTPTR, BT_BV4SI, BT_BV4SI, BT_INTPTR)
......@@ -376,6 +413,8 @@ DEF_OV_TYPE (BT_OV_BV4SI_UV4SI_UV4SI, BT_BV4SI, BT_UV4SI, BT_UV4SI)
DEF_OV_TYPE (BT_OV_BV4SI_UV4SI_UV4SI_INTPTR, BT_BV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR)
DEF_OV_TYPE (BT_OV_BV4SI_UV4SI_UV4SI_UV4SI, BT_BV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI)
DEF_OV_TYPE (BT_OV_BV4SI_UV4SI_UV4SI_UV4SI_INTPTR, BT_BV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR)
DEF_OV_TYPE (BT_OV_BV4SI_V4SF_USHORT_INTPTR, BT_BV4SI, BT_V4SF, BT_USHORT, BT_INTPTR)
DEF_OV_TYPE (BT_OV_BV4SI_V4SF_V4SF, BT_BV4SI, BT_V4SF, BT_V4SF)
DEF_OV_TYPE (BT_OV_BV4SI_V4SI_V4SI, BT_BV4SI, BT_V4SI, BT_V4SI)
DEF_OV_TYPE (BT_OV_BV4SI_V4SI_V4SI_INTPTR, BT_BV4SI, BT_V4SI, BT_V4SI, BT_INTPTR)
DEF_OV_TYPE (BT_OV_BV8HI_BV16QI, BT_BV8HI, BT_BV16QI)
......@@ -384,6 +423,7 @@ DEF_OV_TYPE (BT_OV_BV8HI_BV8HI, BT_BV8HI, BT_BV8HI)
DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI, BT_BV8HI, BT_BV8HI, BT_BV8HI)
DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI_BV8HI, BT_BV8HI, BT_BV8HI, BT_BV8HI, BT_BV8HI)
DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI_INTPTR, BT_BV8HI, BT_BV8HI, BT_BV8HI, BT_INTPTR)
DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI_ULONGLONG, BT_BV8HI, BT_BV8HI, BT_BV8HI, BT_ULONGLONG)
DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI_UV16QI, BT_BV8HI, BT_BV8HI, BT_BV8HI, BT_UV16QI)
DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_BV8HI_UV8HI, BT_BV8HI, BT_BV8HI, BT_BV8HI, BT_UV8HI)
DEF_OV_TYPE (BT_OV_BV8HI_BV8HI_INTPTR, BT_BV8HI, BT_BV8HI, BT_INTPTR)
......@@ -398,6 +438,7 @@ DEF_OV_TYPE (BT_OV_BV8HI_UV8HI_UV8HI_UV8HI_INTPTR, BT_BV8HI, BT_UV8HI, BT_UV8HI,
DEF_OV_TYPE (BT_OV_BV8HI_V8HI_V8HI, BT_BV8HI, BT_V8HI, BT_V8HI)
DEF_OV_TYPE (BT_OV_BV8HI_V8HI_V8HI_INTPTR, BT_BV8HI, BT_V8HI, BT_V8HI, BT_INTPTR)
DEF_OV_TYPE (BT_OV_DBL_V2DF_INT, BT_DBL, BT_V2DF, BT_INT)
DEF_OV_TYPE (BT_OV_FLT_V4SF_INT, BT_FLT, BT_V4SF, BT_INT)
DEF_OV_TYPE (BT_OV_INT_BV16QI_BV16QI, BT_INT, BT_BV16QI, BT_BV16QI)
DEF_OV_TYPE (BT_OV_INT_BV16QI_UV16QI, BT_INT, BT_BV16QI, BT_UV16QI)
DEF_OV_TYPE (BT_OV_INT_BV16QI_V16QI, BT_INT, BT_BV16QI, BT_V16QI)
......@@ -426,6 +467,8 @@ DEF_OV_TYPE (BT_OV_INT_V2DF_V2DF, BT_INT, BT_V2DF, BT_V2DF)
DEF_OV_TYPE (BT_OV_INT_V2DI_BV2DI, BT_INT, BT_V2DI, BT_BV2DI)
DEF_OV_TYPE (BT_OV_INT_V2DI_UV2DI, BT_INT, BT_V2DI, BT_UV2DI)
DEF_OV_TYPE (BT_OV_INT_V2DI_V2DI, BT_INT, BT_V2DI, BT_V2DI)
DEF_OV_TYPE (BT_OV_INT_V4SF_UV4SI, BT_INT, BT_V4SF, BT_UV4SI)
DEF_OV_TYPE (BT_OV_INT_V4SF_V4SF, BT_INT, BT_V4SF, BT_V4SF)
DEF_OV_TYPE (BT_OV_INT_V4SI_BV4SI, BT_INT, BT_V4SI, BT_BV4SI)
DEF_OV_TYPE (BT_OV_INT_V4SI_INT, BT_INT, BT_V4SI, BT_INT)
DEF_OV_TYPE (BT_OV_INT_V4SI_UV4SI, BT_INT, BT_V4SI, BT_UV4SI)
......@@ -616,6 +659,7 @@ DEF_OV_TYPE (BT_OV_V2DF_DBLCONSTPTR_USHORT, BT_V2DF, BT_DBLCONSTPTR, BT_USHORT)
DEF_OV_TYPE (BT_OV_V2DF_DBL_INT, BT_V2DF, BT_DBL, BT_INT)
DEF_OV_TYPE (BT_OV_V2DF_DBL_V2DF_INT, BT_V2DF, BT_DBL, BT_V2DF, BT_INT)
DEF_OV_TYPE (BT_OV_V2DF_LONG_DBLPTR, BT_V2DF, BT_LONG, BT_DBLPTR)
DEF_OV_TYPE (BT_OV_V2DF_UV2DI, BT_V2DF, BT_UV2DI)
DEF_OV_TYPE (BT_OV_V2DF_UV2DI_INT, BT_V2DF, BT_UV2DI, BT_INT)
DEF_OV_TYPE (BT_OV_V2DF_V2DF, BT_V2DF, BT_V2DF)
DEF_OV_TYPE (BT_OV_V2DF_V2DF_BV2DI, BT_V2DF, BT_V2DF, BT_BV2DI)
......@@ -628,7 +672,9 @@ DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_INT, BT_V2DF, BT_V2DF, BT_V2DF, BT_INT)
DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_ULONGLONG, BT_V2DF, BT_V2DF, BT_V2DF, BT_ULONGLONG)
DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV16QI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV16QI)
DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV2DI)
DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF, BT_V2DF)
DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DI, BT_V2DF, BT_V2DF, BT_V2DI)
DEF_OV_TYPE (BT_OV_V2DF_V2DI, BT_V2DF, BT_V2DI)
DEF_OV_TYPE (BT_OV_V2DF_V2DI_INT, BT_V2DF, BT_V2DI, BT_INT)
DEF_OV_TYPE (BT_OV_V2DI_BV2DI_V2DI, BT_V2DI, BT_BV2DI, BT_V2DI)
DEF_OV_TYPE (BT_OV_V2DI_LONGLONG, BT_V2DI, BT_LONGLONG)
......@@ -660,6 +706,26 @@ DEF_OV_TYPE (BT_OV_V2DI_V4SI, BT_V2DI, BT_V4SI)
DEF_OV_TYPE (BT_OV_V2DI_V4SI_V4SI, BT_V2DI, BT_V4SI, BT_V4SI)
DEF_OV_TYPE (BT_OV_V2DI_V4SI_V4SI_V2DI, BT_V2DI, BT_V4SI, BT_V4SI, BT_V2DI)
DEF_OV_TYPE (BT_OV_V2DI_V8HI, BT_V2DI, BT_V8HI)
DEF_OV_TYPE (BT_OV_V4SF_BV4SI_V4SF, BT_V4SF, BT_BV4SI, BT_V4SF)
DEF_OV_TYPE (BT_OV_V4SF_FLT, BT_V4SF, BT_FLT)
DEF_OV_TYPE (BT_OV_V4SF_FLTCONSTPTR, BT_V4SF, BT_FLTCONSTPTR)
DEF_OV_TYPE (BT_OV_V4SF_FLTCONSTPTR_UINT, BT_V4SF, BT_FLTCONSTPTR, BT_UINT)
DEF_OV_TYPE (BT_OV_V4SF_FLTCONSTPTR_USHORT, BT_V4SF, BT_FLTCONSTPTR, BT_USHORT)
DEF_OV_TYPE (BT_OV_V4SF_FLT_INT, BT_V4SF, BT_FLT, BT_INT)
DEF_OV_TYPE (BT_OV_V4SF_FLT_V4SF_INT, BT_V4SF, BT_FLT, BT_V4SF, BT_INT)
DEF_OV_TYPE (BT_OV_V4SF_LONG_FLTPTR, BT_V4SF, BT_LONG, BT_FLTPTR)
DEF_OV_TYPE (BT_OV_V4SF_V4SF, BT_V4SF, BT_V4SF)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_BV4SI, BT_V4SF, BT_V4SF, BT_BV4SI)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_UCHAR, BT_V4SF, BT_V4SF, BT_UCHAR)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_UV4SI)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI_FLTCONSTPTR_UCHAR, BT_V4SF, BT_V4SF, BT_UV4SI, BT_FLTCONSTPTR, BT_UCHAR)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_BV4SI, BT_V4SF, BT_V4SF, BT_V4SF, BT_BV4SI)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_ULONGLONG, BT_V4SF, BT_V4SF, BT_V4SF, BT_ULONGLONG)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UV16QI, BT_V4SF, BT_V4SF, BT_V4SF, BT_UV16QI)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_V4SF, BT_UV4SI)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF, BT_V4SF)
DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SI, BT_V4SF, BT_V4SF, BT_V4SI)
DEF_OV_TYPE (BT_OV_V4SI_BV4SI_V4SI, BT_V4SI, BT_BV4SI, BT_V4SI)
DEF_OV_TYPE (BT_OV_V4SI_INT, BT_V4SI, BT_INT)
DEF_OV_TYPE (BT_OV_V4SI_INTCONSTPTR, BT_V4SI, BT_INTCONSTPTR)
......@@ -745,6 +811,9 @@ DEF_OV_TYPE (BT_OV_VOID_V2DF_UV2DI_DBLPTR_ULONGLONG, BT_VOID, BT_V2DF, BT_UV2DI,
DEF_OV_TYPE (BT_OV_VOID_V2DI_LONGLONGPTR_UINT, BT_VOID, BT_V2DI, BT_LONGLONGPTR, BT_UINT)
DEF_OV_TYPE (BT_OV_VOID_V2DI_LONG_LONGLONGPTR, BT_VOID, BT_V2DI, BT_LONG, BT_LONGLONGPTR)
DEF_OV_TYPE (BT_OV_VOID_V2DI_UV2DI_LONGLONGPTR_ULONGLONG, BT_VOID, BT_V2DI, BT_UV2DI, BT_LONGLONGPTR, BT_ULONGLONG)
DEF_OV_TYPE (BT_OV_VOID_V4SF_FLTPTR_UINT, BT_VOID, BT_V4SF, BT_FLTPTR, BT_UINT)
DEF_OV_TYPE (BT_OV_VOID_V4SF_LONG_FLTPTR, BT_VOID, BT_V4SF, BT_LONG, BT_FLTPTR)
DEF_OV_TYPE (BT_OV_VOID_V4SF_V4SF_FLTPTR_ULONGLONG, BT_VOID, BT_V4SF, BT_V4SF, BT_FLTPTR, BT_ULONGLONG)
DEF_OV_TYPE (BT_OV_VOID_V4SI_INTPTR_UINT, BT_VOID, BT_V4SI, BT_INTPTR, BT_UINT)
DEF_OV_TYPE (BT_OV_VOID_V4SI_LONG_INTPTR, BT_VOID, BT_V4SI, BT_LONG, BT_INTPTR)
DEF_OV_TYPE (BT_OV_VOID_V4SI_UV4SI_INTPTR_ULONGLONG, BT_VOID, BT_V4SI, BT_UV4SI, BT_INTPTR, BT_ULONGLONG)
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -145,6 +145,8 @@ extern const unsigned int opflags_builtin[S390_BUILTIN_MAX + 1];
extern const unsigned int
bflags_overloaded_builtin[S390_OVERLOADED_BUILTIN_MAX + 1];
extern const unsigned int
bflags_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1];
extern const unsigned int
opflags_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1];
static inline unsigned int
......
......@@ -61,7 +61,7 @@ type_for_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1] =
#undef OB_DEF_VAR
#define B_DEF(...)
#define OB_DEF(...)
#define OB_DEF_VAR(NAME, PATTERN, FLAGS, FNTYPE) FNTYPE,
#define OB_DEF_VAR(NAME, PATTERN, FLAGS, OPFLAGS, FNTYPE) FNTYPE,
#include "s390-builtins.def"
BT_OV_MAX
};
......@@ -259,6 +259,7 @@ s390_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
|| rid_code == RID_SHORT || rid_code == RID_SIGNED
|| rid_code == RID_INT || rid_code == RID_CHAR
|| (rid_code == RID_FLOAT && TARGET_VXE)
|| rid_code == RID_DOUBLE)
{
expand_this = C_CPP_HASHNODE (__vector_keyword);
......@@ -323,7 +324,7 @@ s390_cpu_cpp_builtins_internal (cpp_reader *pfile,
s390_def_or_undef_macro (pfile, MASK_OPT_VX, old_opts, opts,
"__VX__", "__VX__");
s390_def_or_undef_macro (pfile, MASK_ZVECTOR, old_opts, opts,
"__VEC__=10301", "__VEC__");
"__VEC__=10302", "__VEC__");
s390_def_or_undef_macro (pfile, MASK_ZVECTOR, old_opts, opts,
"__vector=__attribute__((vector_size(16)))",
"__vector__");
......@@ -471,11 +472,13 @@ s390_expand_overloaded_builtin (location_t loc,
}
return build_int_cst (NULL_TREE,
TYPE_VECTOR_SUBPARTS (TREE_TYPE ((*arglist)[0])));
case S390_OVERLOADED_BUILTIN_s390_vec_xl:
case S390_OVERLOADED_BUILTIN_s390_vec_xld2:
case S390_OVERLOADED_BUILTIN_s390_vec_xlw4:
return build2 (MEM_REF, return_type,
fold_build_pointer_plus ((*arglist)[1], (*arglist)[0]),
build_int_cst (TREE_TYPE ((*arglist)[1]), 0));
case S390_OVERLOADED_BUILTIN_s390_vec_xst:
case S390_OVERLOADED_BUILTIN_s390_vec_xstd2:
case S390_OVERLOADED_BUILTIN_s390_vec_xstw4:
return build2 (MODIFY_EXPR, TREE_TYPE((*arglist)[0]),
......@@ -848,6 +851,7 @@ s390_resolve_overloaded_builtin (location_t loc,
int last_match_type = INT_MAX;
int last_match_index = -1;
unsigned int all_op_flags;
const unsigned int ob_flags = bflags_for_builtin(ob_fcode);
int num_matches = 0;
tree target_builtin_decl, b_arg_chain, return_type;
enum s390_builtin_ov_type_index last_match_fntype_index;
......@@ -861,7 +865,7 @@ s390_resolve_overloaded_builtin (location_t loc,
/* 0...S390_BUILTIN_MAX-1 is for non-overloaded builtins. */
if (ob_fcode < S390_BUILTIN_MAX)
{
if (bflags_for_builtin(ob_fcode) & B_INT)
if (ob_flags & B_INT)
{
error_at (loc,
"builtin %qF is for GCC internal use only.",
......@@ -871,6 +875,21 @@ s390_resolve_overloaded_builtin (location_t loc,
return NULL_TREE;
}
if (ob_flags & B_DEP)
warning_at (loc, 0, "builtin %qF is deprecated.", ob_fndecl);
if (!TARGET_VX && (ob_flags & B_VX))
{
error_at (loc, "%qF requires -mvx", ob_fndecl);
return error_mark_node;
}
if (!TARGET_VXE && (ob_flags & B_VXE))
{
error_at (loc, "%qF requires -march=arch12 or higher", ob_fndecl);
return error_mark_node;
}
ob_fcode -= S390_BUILTIN_MAX;
for (b_arg_chain = TYPE_ARG_TYPES (TREE_TYPE (ob_fndecl));
......@@ -941,6 +960,20 @@ s390_resolve_overloaded_builtin (location_t loc,
return error_mark_node;
}
if (!TARGET_VXE
&& bflags_overloaded_builtin_var[last_match_index] & B_VXE)
{
error_at (loc, "%qs matching variant requires -march=arch12 or higher",
IDENTIFIER_POINTER (DECL_NAME (ob_fndecl)));
return error_mark_node;
}
if (bflags_overloaded_builtin_var[last_match_index] & B_DEP)
warning_at (loc, 0, "%qs matching variant is deprecated.",
IDENTIFIER_POINTER (DECL_NAME (ob_fndecl)));
/* Overloaded variants which have MAX set as low level builtin are
supposed to be replaced during expansion with something else. */
if (bt_for_overloaded_builtin_var[last_match_index] == S390_BUILTIN_MAX)
target_builtin_decl = ob_fndecl;
else
......
......@@ -625,6 +625,19 @@ const unsigned int bflags_overloaded_builtin[S390_OVERLOADED_BUILTIN_MAX + 1] =
};
const unsigned int
bflags_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1] =
{
#undef B_DEF
#undef OB_DEF
#undef OB_DEF_VAR
#define B_DEF(...)
#define OB_DEF(...)
#define OB_DEF_VAR(NAME, PATTERN, FLAGS, OPFLAGS, FNTYPE) FLAGS,
#include "s390-builtins.def"
0
};
const unsigned int
opflags_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1] =
{
#undef B_DEF
......@@ -632,7 +645,7 @@ opflags_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1] =
#undef OB_DEF_VAR
#define B_DEF(...)
#define OB_DEF(...)
#define OB_DEF_VAR(NAME, PATTERN, FLAGS, FNTYPE) FLAGS,
#define OB_DEF_VAR(NAME, PATTERN, FLAGS, OPFLAGS, FNTYPE) OPFLAGS,
#include "s390-builtins.def"
0
};
......@@ -827,7 +840,7 @@ s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
}
if (((bflags & B_VX) || (bflags & B_VXE)) && !TARGET_VX)
{
error ("builtin %qF is not supported without -mvx "
error ("builtin %qF requires -mvx "
"(default with -march=z13 and higher).", fndecl);
return const0_rtx;
}
......
......@@ -156,6 +156,7 @@
UNSPEC_VEC_INSERT_AND_ZERO
UNSPEC_VEC_LOAD_BNDRY
UNSPEC_VEC_LOAD_LEN
UNSPEC_VEC_LOAD_LEN_R
UNSPEC_VEC_MERGEH
UNSPEC_VEC_MERGEL
UNSPEC_VEC_PACK
......@@ -169,6 +170,8 @@
UNSPEC_VEC_PERMI
UNSPEC_VEC_EXTEND
UNSPEC_VEC_STORE_LEN
UNSPEC_VEC_STORE_LEN_R
UNSPEC_VEC_VBPERM
UNSPEC_VEC_UNPACKH
UNSPEC_VEC_UNPACKH_L
UNSPEC_VEC_UNPACKL
......@@ -223,13 +226,18 @@
UNSPEC_VEC_VCGDB
UNSPEC_VEC_VCLGDB
UNSPEC_VEC_VFIDB
UNSPEC_VEC_VFI
UNSPEC_VEC_VLDEB
UNSPEC_VEC_VLEDB
UNSPEC_VEC_VFLL ; vector fp load lengthened
UNSPEC_VEC_VFLR ; vector fp load rounded
UNSPEC_VEC_VFTCIDB
UNSPEC_VEC_VFTCIDBCC
UNSPEC_VEC_VFTCI
UNSPEC_VEC_VFTCICC
UNSPEC_VEC_MSUM
UNSPEC_VEC_VFMIN
UNSPEC_VEC_VFMAX
])
;;
......@@ -400,7 +408,7 @@
;; Used to determine defaults for length and other attribute values.
(define_attr "op_type"
"NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
"NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI"
(const_string "NN"))
;; Instruction type attribute used for scheduling.
......
......@@ -21,18 +21,42 @@ along with GCC; see the file COPYING3. If not see
#ifndef _VECINTRIN_H
#define _VECINTRIN_H
#define __VFTCI_ZERO 1<<11
#define __VFTCI_ZERO_N 1<<10
#define __VFTCI_NORMAL 1<<9
#define __VFTCI_NORMAL_N 1<<8
#define __VFTCI_SUBNORMAL 1<<7
#define __VFTCI_SUBNORMAL_N 1<<6
#define __VFTCI_INF 1<<5
#define __VFTCI_INF_N 1<<4
#define __VFTCI_QNAN 1<<3
#define __VFTCI_QNAN_N 1<<2
#define __VFTCI_SNAN 1<<1
#define __VFTCI_SNAN_N 1<<0
#define __VEC_CLASS_FP_ZERO_P (1<<11)
#define __VEC_CLASS_FP_ZERO_N (1<<10)
#define __VEC_CLASS_FP_ZERO (__VEC_CLASS_FP_ZERO_P \
| __VEC_CLASS_FP_ZERO_N)
#define __VEC_CLASS_FP_NORMAL_P (1<<9)
#define __VEC_CLASS_FP_NORMAL_N (1<<8)
#define __VEC_CLASS_FP_NORMAL (__VEC_CLASS_FP_NORMAL_P \
| __VEC_CLASS_FP_NORMAL_N)
#define __VEC_CLASS_FP_SUBNORMAL_P (1<<7)
#define __VEC_CLASS_FP_SUBNORMAL_N (1<<6)
#define __VEC_CLASS_FP_SUBNORMAL (__VEC_CLASS_FP_SUBNORMAL_P \
| __VEC_CLASS_FP_SUBNORMAL_N)
#define __VEC_CLASS_FP_INFINITY_P (1<<5)
#define __VEC_CLASS_FP_INFINITY_N (1<<4)
#define __VEC_CLASS_FP_INFINITY (__VEC_CLASS_FP_INFINITY_P \
| __VEC_CLASS_FP_INFINITY_N)
#define __VEC_CLASS_FP_QNAN_P (1<<3)
#define __VEC_CLASS_FP_QNAN_N (1<<2)
#define __VEC_CLASS_FP_QNAN (__VEC_CLASS_FP_QNAN_P \
| __VEC_CLASS_FP_QNAN_N)
#define __VEC_CLASS_FP_SNAN_P (1<<1)
#define __VEC_CLASS_FP_SNAN_N (1<<0)
#define __VEC_CLASS_FP_SNAN (__VEC_CLASS_FP_SNAN_P \
| __VEC_CLASS_FP_SNAN_N)
#define __VEC_CLASS_FP_NAN (__VEC_CLASS_FP_QNAN \
| __VEC_CLASS_FP_SNAN)
#define __VEC_CLASS_FP_NOT_NORMAL (__VEC_CLASS_FP_NAN \
| __VEC_CLASS_FP_SUBNORMAL \
|__VEC_CLASS_FP_ZERO \
| __VEC_CLASS_FP_INFINITY)
/* This also accepts a type for its parameter, so it is not enough
to #define vec_step to __builtin_vec_step. */
......@@ -76,62 +100,69 @@ __lcbb(const void *ptr, int bndry)
#define vec_checksum __builtin_s390_vcksm
#define vec_gfmsum_128 __builtin_s390_vgfmg
#define vec_gfmsum_accum_128 __builtin_s390_vgfmag
#define vec_ceil(X) __builtin_s390_vfidb((X), 4, 6)
#define vec_roundp(X) __builtin_s390_vfidb((X), 4, 6)
#define vec_floor(X) __builtin_s390_vfidb((X), 4, 7)
#define vec_roundm(X) __builtin_s390_vfidb((X), 4, 7)
#define vec_trunc(X) __builtin_s390_vfidb((X), 4, 5)
#define vec_roundz(X) __builtin_s390_vfidb((X), 4, 5)
#define vec_roundc(X) __builtin_s390_vfidb((X), 4, 0)
#define vec_round(X) __builtin_s390_vfidb((X), 4, 4)
#define vec_ceil(X) __builtin_s390_vfi((X), 4, 6)
#define vec_roundp(X) __builtin_s390_vfi((X), 4, 6)
#define vec_floor(X) __builtin_s390_vfi((X), 4, 7)
#define vec_roundm(X) __builtin_s390_vfi((X), 4, 7)
#define vec_trunc(X) __builtin_s390_vfi((X), 4, 5)
#define vec_roundz(X) __builtin_s390_vfi((X), 4, 5)
#define vec_rint(X) __builtin_s390_vfi((X), 0, 0)
#define vec_roundc(X) __builtin_s390_vfi((X), 4, 0)
#define vec_round(X) __builtin_s390_vfi((X), 4, 4)
#define vec_signed(X) __builtin_s390_vcgdb((X), 0, 0)
#define vec_unsigned(X) __builtin_s390_vclgdb((X), 0, 0)
#define vec_doublee(X) __builtin_s390_vfll((X))
#define vec_floate(X) __builtin_s390_vflr((X), 0, 0)
#define vec_madd __builtin_s390_vfmadb
#define vec_msub __builtin_s390_vfmsdb
#define vec_load_len_r(X,Y) __builtin_s390_vlrl((Y),(X))
#define vec_store_len_r(X,Y) __builtin_s390_vstrl((Y),(X))
#define vec_all_nan(a) \
__extension__ ({ \
int __cc; \
__builtin_s390_vftcidb (a, \
__VFTCI_QNAN \
| __VFTCI_QNAN_N \
| __VFTCI_SNAN \
| __VFTCI_SNAN_N, &__cc); \
__builtin_s390_vec_fp_test_data_class (a, \
__VEC_CLASS_FP_QNAN \
| __VEC_CLASS_FP_QNAN_N \
| __VEC_CLASS_FP_SNAN \
| __VEC_CLASS_FP_SNAN_N, &__cc); \
__cc == 0 ? 1 : 0; \
})
#define vec_all_numeric(a) \
__extension__ ({ \
int __cc; \
__builtin_s390_vftcidb (a, \
__VFTCI_NORMAL \
| __VFTCI_NORMAL_N \
| __VFTCI_SUBNORMAL \
| __VFTCI_SUBNORMAL_N, &__cc); \
__builtin_s390_vec_fp_test_data_class (a, \
__VEC_CLASS_FP_NORMAL \
| __VEC_CLASS_FP_NORMAL_N \
| __VEC_CLASS_FP_SUBNORMAL \
| __VEC_CLASS_FP_SUBNORMAL_N, &__cc); \
__cc == 0 ? 1 : 0; \
})
#define vec_any_nan(a) \
__extension__ ({ \
int __cc; \
__builtin_s390_vftcidb (a, \
__VFTCI_QNAN \
| __VFTCI_QNAN_N \
| __VFTCI_SNAN \
| __VFTCI_SNAN_N, &cc); \
__builtin_s390_vec_fp_test_data_class (a, \
__VEC_CLASS_FP_QNAN \
| __VEC_CLASS_FP_QNAN_N \
| __VEC_CLASS_FP_SNAN \
| __VEC_CLASS_FP_SNAN_N, &cc); \
cc != 3 ? 1 : 0; \
})
#define vec_any_numeric(a) \
__extension__ ({ \
int __cc; \
__builtin_s390_vftcidb (a, \
__VFTCI_NORMAL \
| __VFTCI_NORMAL_N \
| __VFTCI_SUBNORMAL \
| __VFTCI_SUBNORMAL_N, &cc); \
__builtin_s390_vec_fp_test_data_class (a, \
__VEC_CLASS_FP_NORMAL \
| __VEC_CLASS_FP_NORMAL_N \
| __VEC_CLASS_FP_SUBNORMAL \
| __VEC_CLASS_FP_SUBNORMAL_N, &cc); \
cc != 3 ? 1 : 0; \
})
#define vec_gather_element __builtin_s390_vec_gather_element
#define vec_xl __builtin_s390_vec_xl
#define vec_xld2 __builtin_s390_vec_xld2
#define vec_xlw4 __builtin_s390_vec_xlw4
#define vec_splats __builtin_s390_vec_splats
......@@ -155,9 +186,11 @@ __lcbb(const void *ptr, int bndry)
#define vec_scatter_element __builtin_s390_vec_scatter_element
#define vec_sel __builtin_s390_vec_sel
#define vec_extend_s64 __builtin_s390_vec_extend_s64
#define vec_xst __builtin_s390_vec_xst
#define vec_xstd2 __builtin_s390_vec_xstd2
#define vec_xstw4 __builtin_s390_vec_xstw4
#define vec_store_len __builtin_s390_vec_store_len
#define vec_bperm_u128 __builtin_s390_vec_bperm_u128
#define vec_unpackh __builtin_s390_vec_unpackh
#define vec_unpackl __builtin_s390_vec_unpackl
#define vec_addc __builtin_s390_vec_addc
......@@ -223,6 +256,10 @@ __lcbb(const void *ptr, int bndry)
#define vec_sum_u128 __builtin_s390_vec_sum_u128
#define vec_sum4 __builtin_s390_vec_sum4
#define vec_test_mask __builtin_s390_vec_test_mask
#define vec_msum_u128 __builtin_s390_vec_msum_u128
#define vec_eqv __builtin_s390_vec_eqv
#define vec_nand __builtin_s390_vec_nand
#define vec_orc __builtin_s390_vec_orc
#define vec_find_any_eq_idx __builtin_s390_vec_find_any_eq_idx
#define vec_find_any_ne_idx __builtin_s390_vec_find_any_ne_idx
#define vec_find_any_eq_or_0_idx __builtin_s390_vec_find_any_eq_or_0_idx
......@@ -268,4 +305,10 @@ __lcbb(const void *ptr, int bndry)
#define vec_ctul __builtin_s390_vec_ctul
#define vec_ld2f __builtin_s390_vec_ld2f
#define vec_st2f __builtin_s390_vec_st2f
#define vec_double __builtin_s390_vec_double
#define vec_nmadd __builtin_s390_vec_nmadd
#define vec_nmsub __builtin_s390_vec_nmsub
#define vec_nabs __builtin_s390_vec_nabs
#define vec_sqrt __builtin_s390_vec_sqrt
#define vec_fp_test_data_class __builtin_s390_vec_fp_test_data_class
#endif /* _VECINTRIN_H */
......@@ -20,9 +20,13 @@
; The patterns in this file are enabled with -mzvector
(define_mode_iterator V_HW_32_64 [V4SI V2DI V2DF])
(define_mode_iterator V_HW_32_64 [V4SI V2DI V2DF (V4SF "TARGET_VXE")])
(define_mode_iterator VI_HW_SD [V4SI V2DI])
(define_mode_iterator V_HW_HSD [V8HI V4SI V2DI V2DF])
(define_mode_iterator V_HW_4 [V4SI V4SF])
; Full size vector modes with more than one element which are directly supported in vector registers by the hardware.
(define_mode_iterator VEC_HW [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")])
(define_mode_iterator VECF_HW [(V4SF "TARGET_VXE") V2DF])
; The element type of the vector with floating point modes translated
; to int modes of the same size.
......@@ -61,6 +65,11 @@
(VEC_RND_TO_INF 6)
(VEC_RND_TO_MINF 7)])
; Inexact suppression facility flag as being used for e.g. VFI
(define_constants
[(VEC_INEXACT 0)
(VEC_NOINEXACT 4)])
; Vector gather element
......@@ -142,23 +151,23 @@
})
(define_expand "vec_splats<mode>"
[(set (match_operand:V_HW 0 "register_operand" "")
(vec_duplicate:V_HW (match_operand:<non_vec> 1 "general_operand" "")))]
[(set (match_operand:VEC_HW 0 "register_operand" "")
(vec_duplicate:VEC_HW (match_operand:<non_vec> 1 "general_operand" "")))]
"TARGET_VX")
(define_expand "vec_insert<mode>"
[(set (match_operand:V_HW 0 "register_operand" "")
(unspec:V_HW [(match_operand:<non_vec> 2 "register_operand" "")
[(set (match_operand:VEC_HW 0 "register_operand" "")
(unspec:VEC_HW [(match_operand:<non_vec> 2 "register_operand" "")
(match_operand:SI 3 "nonmemory_operand" "")
(match_operand:V_HW 1 "register_operand" "")]
(match_operand:VEC_HW 1 "register_operand" "")]
UNSPEC_VEC_SET))]
"TARGET_VX"
"")
; This is vec_set + modulo arithmetic on the element selector (op 2)
(define_expand "vec_promote<mode>"
[(set (match_operand:V_HW 0 "register_operand" "")
(unspec:V_HW [(match_operand:<non_vec> 1 "register_operand" "")
[(set (match_operand:VEC_HW 0 "register_operand" "")
(unspec:VEC_HW [(match_operand:<non_vec> 1 "register_operand" "")
(match_operand:SI 2 "nonmemory_operand" "")
(match_dup 0)]
UNSPEC_VEC_SET))]
......@@ -169,8 +178,8 @@
; vllezb, vllezh, vllezf, vllezg
(define_insn "vec_insert_and_zero<mode>"
[(set (match_operand:V_HW 0 "register_operand" "=v")
(unspec:V_HW [(match_operand:<non_vec> 1 "memory_operand" "R")]
[(set (match_operand:VEC_HW 0 "register_operand" "=v")
(unspec:VEC_HW [(match_operand:<non_vec> 1 "memory_operand" "R")]
UNSPEC_VEC_INSERT_AND_ZERO))]
"TARGET_VX"
"vllez<bhfgq>\t%v0,%1"
......@@ -185,14 +194,26 @@
"vlbb\t%v0,%1,%2"
[(set_attr "op_type" "VRX")])
(define_insn "vlrlrv16qi"
[(set (match_operand:V16QI 0 "register_operand" "=v,v")
(unspec:V16QI [(match_operand:BLK 2 "memory_operand" "Q,Q")
(match_operand:SI 1 "nonmemory_operand" "d,C")]
UNSPEC_VEC_LOAD_LEN_R))]
"TARGET_VXE"
"@
vlrlr\t%v0,%1,%2
vlrl\t%v0,%2,%1"
[(set_attr "op_type" "VRS,VSI")])
; FIXME: The following two patterns might using vec_merge. But what is
; the canonical form: (vec_select (vec_merge op0 op1)) or (vec_merge
; (vec_select op0) (vec_select op1)
; vmrhb, vmrhh, vmrhf, vmrhg
(define_insn "vec_mergeh<mode>"
[(set (match_operand:V_HW 0 "register_operand" "=v")
(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
(match_operand:V_HW 2 "register_operand" "v")]
[(set (match_operand:VEC_HW 0 "register_operand" "=v")
(unspec:VEC_HW [(match_operand:VEC_HW 1 "register_operand" "v")
(match_operand:VEC_HW 2 "register_operand" "v")]
UNSPEC_VEC_MERGEH))]
"TARGET_VX"
"vmrh<bhfgq>\t%v0,%1,%2"
......@@ -200,9 +221,9 @@
; vmrlb, vmrlh, vmrlf, vmrlg
(define_insn "vec_mergel<mode>"
[(set (match_operand:V_HW 0 "register_operand" "=v")
(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
(match_operand:V_HW 2 "register_operand" "v")]
[(set (match_operand:VEC_HW 0 "register_operand" "=v")
(unspec:VEC_HW [(match_operand:VEC_HW 1 "register_operand" "v")
(match_operand:VEC_HW 2 "register_operand" "v")]
UNSPEC_VEC_MERGEL))]
"TARGET_VX"
"vmrl<bhfgq>\t%v0,%1,%2"
......@@ -397,14 +418,14 @@
; vscef, vsceg
; A 64 bit target address generated from 32 bit elements
(define_insn "vec_scatter_elementv4si_DI"
[(set (mem:SI
(define_insn "vec_scatter_element<V_HW_4:mode>_DI"
[(set (mem:<non_vec>
(plus:DI (zero_extend:DI
(unspec:SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_EXTRACT))
(match_operand:SI 2 "address_operand" "ZQ")))
(unspec:SI [(match_operand:V4SI 0 "register_operand" "v")
(unspec:<non_vec> [(match_operand:V_HW_4 0 "register_operand" "v")
(match_dup 3)] UNSPEC_VEC_EXTRACT))]
"TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4"
"vscef\t%v0,%O2(%v1,%R2),%3"
......@@ -515,6 +536,31 @@
"vstl\t%v0,%1,%2"
[(set_attr "op_type" "VRS")])
; Vector store rightmost with length
(define_insn "vstrlrv16qi"
[(set (match_operand:BLK 2 "memory_operand" "=Q,Q")
(unspec:BLK [(match_operand:V16QI 0 "register_operand" "v,v")
(match_operand:SI 1 "nonmemory_operand" "d,C")]
UNSPEC_VEC_STORE_LEN_R))]
"TARGET_VXE"
"@
vstrlr\t%v0,%2,%1
vstrl\t%v0,%1,%2"
[(set_attr "op_type" "VRS,VSI")])
; vector bit permute
(define_insn "vbpermv16qi"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(unspec:V2DI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VEC_VBPERM))]
"TARGET_VXE"
"vbperm\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
; Vector unpack high
......@@ -600,24 +646,6 @@
; Vector and
; The following two patterns allow mixed mode and's as required for the intrinsics.
(define_insn "and_av2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(and:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX"
"vn\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
(define_insn "and_cv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(and:V2DF (match_operand:V2DF 1 "register_operand" "v")
(subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)))]
"TARGET_VX"
"vn\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
; Vector and with complement
; vnc
......@@ -629,24 +657,6 @@
"vnc\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
; The following two patterns allow mixed mode and's as required for the intrinsics.
(define_insn "vec_andc_av2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(and:V2DF (not:V2DF (match_operand:V2DF 2 "register_operand" "v"))
(subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)))]
"TARGET_VX"
"vnc\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
(define_insn "vec_andc_cv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(and:V2DF (not:V2DF (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0))
(match_operand:V2DF 1 "register_operand" "v")))]
"TARGET_VX"
"vnc\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
; Vector average
......@@ -720,10 +730,10 @@
; vec_all/any fp compares
(define_expand "vec_all_<fpcmpcc:code>v2df"
(define_expand "vec_all_<fpcmpcc:code><mode>"
[(match_operand:SI 0 "register_operand" "")
(fpcmpcc (match_operand:V2DF 1 "register_operand" "")
(match_operand:V2DF 2 "register_operand" ""))]
(fpcmpcc (match_operand:VECF_HW 1 "register_operand" "")
(match_operand:VECF_HW 2 "register_operand" ""))]
"TARGET_VX"
{
s390_expand_vec_compare_cc (operands[0],
......@@ -734,10 +744,10 @@
DONE;
})
(define_expand "vec_any_<fpcmpcc:code>v2df"
(define_expand "vec_any_<fpcmpcc:code><mode>"
[(match_operand:SI 0 "register_operand" "")
(fpcmpcc (match_operand:V2DF 1 "register_operand" "")
(match_operand:V2DF 2 "register_operand" ""))]
(fpcmpcc (match_operand:VECF_HW 1 "register_operand" "")
(match_operand:VECF_HW 2 "register_operand" ""))]
"TARGET_VX"
{
s390_expand_vec_compare_cc (operands[0],
......@@ -761,10 +771,10 @@
DONE;
})
(define_expand "vec_cmp<fpcmp:code>v2df"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(fpcmp:V2DI (match_operand:V2DF 1 "register_operand" "v")
(match_operand:V2DF 2 "register_operand" "v")))]
(define_expand "vec_cmp<fpcmp:code><mode>"
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
(fpcmp:<tointvec> (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")))]
"TARGET_VX"
{
s390_expand_vec_compare (operands[0], <fpcmp:CODE>, operands[1], operands[2]);
......@@ -781,24 +791,6 @@
; vec_xor -> xor
; The following two patterns allow mixed mode xor's as required for the intrinsics.
(define_insn "xor_av2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(xor:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX"
"vx\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
(define_insn "xor_cv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(xor:V2DF (match_operand:V2DF 1 "register_operand" "v")
(subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)))]
"TARGET_VX"
"vx\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
; Vector Galois field multiply sum
; vgfmb, vgfmh, vgfmf
......@@ -971,50 +963,16 @@
(define_insn "vec_nor<mode>3"
[(set (match_operand:VT_HW 0 "register_operand" "=v")
(not:VT_HW (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "%v")
(not:VT_HW
(ior:VT_HW (match_operand:VT_HW 1 "register_operand" "%v")
(match_operand:VT_HW 2 "register_operand" "v"))))]
"TARGET_VX"
"vno\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
; The following two patterns allow mixed mode and's as required for the intrinsics.
(define_insn "vec_nor_av2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(not:V2DF (ior:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)
(match_operand:V2DF 2 "register_operand" "v"))))]
"TARGET_VX"
"vno\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
(define_insn "vec_nor_cv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(not:V2DF (ior:V2DF (match_operand:V2DF 1 "register_operand" "v")
(subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0))))]
"TARGET_VX"
"vno\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
; Vector or
; The following two patterns allow mixed mode or's as required for the intrinsics.
(define_insn "ior_av2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(ior:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX"
"vo\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
(define_insn "ior_cv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(ior:V2DF (match_operand:V2DF 1 "register_operand" "v")
(subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)))]
"TARGET_VX"
"vo\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
; Vector population count vec_popcnt -> popcount
; Vector element rotate left logical vec_rl -> vrotl, vec_rli -> rot
......@@ -1219,6 +1177,31 @@
[(set_attr "op_type" "VRR")])
; Vector multiply sum logical
(define_insn "vec_msumv2di"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")
(match_operand:V2DI 2 "register_operand" "v")
(match_operand:V16QI 3 "register_operand" "v")
(match_operand:QI 4 "const_mask_operand" "C")]
UNSPEC_VEC_MSUM))]
"TARGET_VXE"
"vmslg\t%v0,%v1,%v2,%v3"
[(set_attr "op_type" "VRR")])
(define_insn "vmslg"
[(set (match_operand:TI 0 "register_operand" "=v")
(unspec:TI [(match_operand:V2DI 1 "register_operand" "v")
(match_operand:V2DI 2 "register_operand" "v")
(match_operand:TI 3 "register_operand" "v")
(match_operand:QI 4 "const_mask_operand" "C")]
UNSPEC_VEC_MSUM))]
"TARGET_VXE"
"vmslg\t%v0,%v1,%v2,%v3"
[(set_attr "op_type" "VRR")])
; Vector find any element equal
; vfaeb, vfaeh, vfaef
......@@ -1609,22 +1592,23 @@
operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_CS | VSTRING_FLAG_ZS);
})
; Signed V2DI -> V2DF conversion - inexact exception disabled
(define_insn "vec_di_to_df_s64"
(define_insn "vcdgb"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v")
(match_operand:QI 2 "const_mask_operand" "C")]
(match_operand:QI 2 "const_mask_operand" "C") ; inexact suppression
(match_operand:QI 3 "const_mask_operand" "C")] ; rounding mode
UNSPEC_VEC_VCDGB))]
"TARGET_VX && UINTVAL (operands[2]) != 2 && UINTVAL (operands[2]) <= 7"
"vcdgb\t%v0,%v1,4,%b2"
"TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
"vcdgb\t%v0,%v1,%b2,%b3"
[(set_attr "op_type" "VRR")])
; The result needs to be multiplied with 2**-op2
(define_expand "vec_ctd_s64"
[(set (match_operand:V2DF 0 "register_operand" "")
(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
(const_int 0)] ; According to current BFP rounding mode
(const_int 4) ; inexact suppressed
(const_int VEC_RND_CURRENT)]
UNSPEC_VEC_VCDGB))
(use (match_operand:QI 2 "const_int_operand" ""))
(set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
......@@ -1640,21 +1624,22 @@
operands[3] = force_reg (V2DFmode, operands[3]);
})
; Unsigned V2DI -> V2DF conversion - inexact exception disabled
(define_insn "vec_di_to_df_u64"
(define_insn "vcdlgb"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v")
(match_operand:QI 2 "const_int_operand" "C")]
(match_operand:QI 2 "const_mask_operand" "C") ; inexact suppression
(match_operand:QI 3 "const_mask_operand" "C")] ; rounding mode
UNSPEC_VEC_VCDLGB))]
"TARGET_VX"
"vcdlgb\t%v0,%v1,4,%b2"
"TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
"vcdlgb\t%v0,%v1,%b2,%b3"
[(set_attr "op_type" "VRR")])
; The result needs to be multiplied with 2**-op2
(define_expand "vec_ctd_u64"
[(set (match_operand:V2DF 0 "register_operand" "")
(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
(const_int 0)] ; According to current BFP rounding mode
(const_int 4) ; inexact suppressed
(const_int VEC_RND_CURRENT)]
UNSPEC_VEC_VCDLGB))
(use (match_operand:QI 2 "const_int_operand" ""))
(set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
......@@ -1670,15 +1655,14 @@
operands[3] = force_reg (V2DFmode, operands[3]);
})
; Signed V2DF -> V2DI conversion - inexact exception disabled
(define_insn "vec_df_to_di_s64"
(define_insn "vcgdb"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
(match_operand:QI 2 "const_int_operand" "C")]
(match_operand:QI 2 "const_mask_operand" "C")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_VCGDB))]
"TARGET_VX"
"vcgdb\t%v0,%v1,4,%b2"
"TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
"vcgdb\t%v0,%v1,%b2,%b3"
[(set_attr "op_type" "VRR")])
; The input needs to be multiplied with 2**op2
......@@ -1687,7 +1671,9 @@
(set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
(match_dup 3)))
(set (match_operand:V2DI 0 "register_operand" "")
(unspec:V2DI [(match_dup 4) (const_int 0)] ; According to current BFP rounding mode
(unspec:V2DI [(match_dup 4)
(const_int 4) ; inexact suppressed
(const_int VEC_RND_CURRENT)]
UNSPEC_VEC_VCGDB))]
"TARGET_VX"
{
......@@ -1702,14 +1688,14 @@
operands[4] = gen_reg_rtx (V2DFmode);
})
; Unsigned V2DF -> V2DI conversion - inexact exception disabled
(define_insn "vec_df_to_di_u64"
(define_insn "vclgdb"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
(match_operand:QI 2 "const_mask_operand" "C")]
(match_operand:QI 2 "const_mask_operand" "C")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_VCLGDB))]
"TARGET_VX && UINTVAL (operands[2]) <= 7"
"vclgdb\t%v0,%v1,4,%b2"
"TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
"vclgdb\t%v0,%v1,%b2,%b3"
[(set_attr "op_type" "VRR")])
; The input needs to be multiplied with 2**op2
......@@ -1718,7 +1704,9 @@
(set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
(match_dup 3)))
(set (match_operand:V2DI 0 "register_operand" "")
(unspec:V2DI [(match_dup 4) (const_int 0)] ; According to current BFP rounding mode
(unspec:V2DI [(match_dup 4)
(const_int 4) ; inexact suppressed
(const_int VEC_RND_CURRENT)]
UNSPEC_VEC_VCLGDB))]
"TARGET_VX"
{
......@@ -1734,23 +1722,24 @@
})
; Vector load fp integer - IEEE inexact exception is suppressed
(define_insn "vfidb"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
(match_operand:QI 2 "const_mask_operand" "C")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_VFIDB))]
"TARGET_VX && !(UINTVAL (operands[2]) & 3) && UINTVAL (operands[3]) <= 7"
"vfidb\t%v0,%v1,%b2,%b3"
; vfisb, vfidb, wfisb, wfidb, wfixb
(define_insn "vec_fpint<mode>"
[(set (match_operand:VFT 0 "register_operand" "=v")
(unspec:VFT [(match_operand:VFT 1 "register_operand" "v")
(match_operand:QI 2 "const_mask_operand" "C") ; inexact suppression control
(match_operand:QI 3 "const_mask_operand" "C")] ; rounding mode
UNSPEC_VEC_VFI))]
"TARGET_VX"
"<vw>fi<sdx>b\t%v0,%v1,%b2,%b3"
[(set_attr "op_type" "VRR")])
; Vector load lengthened - V4SF -> V2DF
(define_insn "*vldeb"
(define_insn "vflls"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(unspec:V2DF [(match_operand:V4SF 1 "register_operand" "v")]
UNSPEC_VEC_VLDEB))]
UNSPEC_VEC_VFLL))]
"TARGET_VX"
"vldeb\t%v0,%v1"
[(set_attr "op_type" "VRR")])
......@@ -1769,7 +1758,7 @@
(match_dup 2)]
UNSPEC_VEC_SET))
(set (match_operand:V2DF 0 "register_operand" "")
(unspec:V2DF [(match_dup 2)] UNSPEC_VEC_VLDEB))]
(unspec:V2DF [(match_dup 2)] UNSPEC_VEC_VFLL))]
"TARGET_VX"
{
operands[2] = gen_reg_rtx (V4SFmode);
......@@ -1780,18 +1769,22 @@
; Vector load rounded - V2DF -> V4SF
(define_insn "*vledb"
(define_insn "vflrd"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V2DF 1 "register_operand" "v")]
UNSPEC_VEC_VLEDB))]
(unspec:V4SF [(match_operand:V2DF 1 "register_operand" "v")
(match_operand:QI 2 "const_mask_operand" "C")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_VFLR))]
"TARGET_VX"
"vledb\t%v0,%v1,0,0"
"vledb\t%v0,%v1,%b2,%b3"
[(set_attr "op_type" "VRR")])
(define_expand "vec_st2f"
[(set (match_dup 2)
(unspec:V4SF [(match_operand:V2DF 0 "register_operand" "")]
UNSPEC_VEC_VLEDB))
(unspec:V4SF [(match_operand:V2DF 0 "register_operand" "")
(const_int VEC_INEXACT)
(const_int VEC_RND_CURRENT)]
UNSPEC_VEC_VFLR))
(set (match_operand:SF 1 "memory_operand" "")
(unspec:SF [(match_dup 2) (const_int 0)] UNSPEC_VEC_EXTRACT))
(set (match_dup 3)
......@@ -1803,46 +1796,59 @@
})
; Vector load negated fp
(define_expand "vec_nabs"
[(set (match_operand:V2DF 0 "register_operand" "")
(neg:V2DF (abs:V2DF (match_operand:V2DF 1 "register_operand" ""))))]
"TARGET_VX")
; Vector square root fp vec_sqrt -> sqrt rtx standard name
; Vector FP test data class immediate
;; Vector FP test data class immediate
(define_insn "*vftcidb"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "v")
(match_operand:HI 2 "const_int_operand" "J")]
UNSPEC_VEC_VFTCIDB))
(set (reg:CCRAW CC_REGNUM)
(unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))]
; vec_all_nan, vec_all_numeric, vec_any_nan, vec_any_numeric
; These ignore the vector result and only want CC stored to an int
; pointer.
; vftcisb, vftcidb
(define_insn "*vftci<mode>_cconly"
[(set (reg:CCRAW CC_REGNUM)
(unspec:CCRAW [(match_operand:VECF_HW 1 "register_operand")
(match_operand:HI 2 "const_int_operand")]
UNSPEC_VEC_VFTCICC))
(clobber (match_scratch:<tointvec> 0))]
"TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
"vftcidb\t%v0,%v1,%x2"
"vftci<sdx>b\t%v0,%v1,%x2"
[(set_attr "op_type" "VRR")])
(define_insn "*vftcidb_cconly"
(define_expand "vftci<mode>_intcconly"
[(parallel
[(set (reg:CCRAW CC_REGNUM)
(unspec:CCRAW [(match_operand:V2DF 1 "register_operand" "v")
(unspec:CCRAW [(match_operand:VECF_HW 0 "register_operand")
(match_operand:HI 1 "const_int_operand")]
UNSPEC_VEC_VFTCICC))
(clobber (scratch:<tointvec>))])
(set (match_operand:SI 2 "register_operand" "")
(unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
"TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")")
; vec_fp_test_data_class wants the result vector and the CC stored to
; an int pointer.
; vftcisb, vftcidb
(define_insn "*vftci<mode>"
[(set (match_operand:VECF_HW 0 "register_operand" "=v")
(unspec:VECF_HW [(match_operand:VECF_HW 1 "register_operand" "v")
(match_operand:HI 2 "const_int_operand" "J")]
UNSPEC_VEC_VFTCIDBCC))
(clobber (match_scratch:V2DI 0 "=v"))]
UNSPEC_VEC_VFTCI))
(set (reg:CCRAW CC_REGNUM)
(unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCICC))]
"TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
"vftcidb\t%v0,%v1,%x2"
"vftci<sdx>b\t%v0,%v1,%x2"
[(set_attr "op_type" "VRR")])
(define_expand "vftcidb"
(define_expand "vftci<mode>_intcc"
[(parallel
[(set (match_operand:V2DF 0 "register_operand" "")
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "")
(match_operand:HI 2 "const_int_operand" "")]
UNSPEC_VEC_VFTCIDB))
[(set (match_operand:VECF_HW 0 "register_operand")
(unspec:VECF_HW [(match_operand:VECF_HW 1 "register_operand")
(match_operand:HI 2 "const_int_operand")]
UNSPEC_VEC_VFTCI))
(set (reg:CCRAW CC_REGNUM)
(unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))])
(unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCICC))])
(set (match_operand:SI 3 "memory_operand" "")
(unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
"TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")")
......@@ -1933,79 +1939,123 @@
[(set_attr "op_type" "VRR")])
;;
;; Floating point comparesg
;; Floating point compares
;;
(define_insn "*vec_cmp<insn_cmp>v2df_cconly"
; vfcesbs, vfcedbs, wfcexbs, vfchsbs, vfchdbs, wfchxbs, vfchesbs, vfchedbs, wfchexbs
(define_insn "*vec_cmp<insn_cmp><mode>_cconly"
[(set (reg:VFCMP CC_REGNUM)
(compare:VFCMP (match_operand:V2DF 0 "register_operand" "v")
(match_operand:V2DF 1 "register_operand" "v")))
(clobber (match_scratch:V2DI 2 "=v"))]
(compare:VFCMP (match_operand:VF_HW 0 "register_operand" "v")
(match_operand:VF_HW 1 "register_operand" "v")))
(clobber (match_scratch:<tointvec> 2 "=v"))]
"TARGET_VX"
"vfc<asm_fcmp>dbs\t%v2,%v0,%v1"
"<vw>fc<asm_fcmp><sdx>bs\t%v2,%v0,%v1"
[(set_attr "op_type" "VRR")])
; FIXME: Merge the following 2x3 patterns with VFCMP
(define_expand "vec_cmpeqv2df_cc"
(define_expand "vec_cmpeq<mode>_cc"
[(parallel
[(set (reg:CCVEQ CC_REGNUM)
(compare:CCVEQ (match_operand:V2DF 1 "register_operand" "v")
(match_operand:V2DF 2 "register_operand" "v")))
(set (match_operand:V2DI 0 "register_operand" "=v")
(eq:V2DI (match_dup 1) (match_dup 2)))])
(compare:CCVEQ (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")))
(set (match_operand:<tointvec> 0 "register_operand" "=v")
(eq:<tointvec> (match_dup 1) (match_dup 2)))])
(set (match_operand:SI 3 "memory_operand" "")
(unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))]
"TARGET_VX")
(define_expand "vec_cmphv2df_cc"
(define_expand "vec_cmph<mode>_cc"
[(parallel
[(set (reg:CCVIH CC_REGNUM)
(compare:CCVIH (match_operand:V2DF 1 "register_operand" "v")
(match_operand:V2DF 2 "register_operand" "v")))
(set (match_operand:V2DI 0 "register_operand" "=v")
(gt:V2DI (match_dup 1) (match_dup 2)))])
[(set (reg:CCVFH CC_REGNUM)
(compare:CCVFH (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")))
(set (match_operand:<tointvec> 0 "register_operand" "=v")
(gt:<tointvec> (match_dup 1) (match_dup 2)))])
(set (match_operand:SI 3 "memory_operand" "")
(unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))]
"TARGET_VX")
(define_expand "vec_cmphev2df_cc"
(define_expand "vec_cmphe<mode>_cc"
[(parallel
[(set (reg:CCVFHE CC_REGNUM)
(compare:CCVFHE (match_operand:V2DF 1 "register_operand" "v")
(match_operand:V2DF 2 "register_operand" "v")))
(set (match_operand:V2DI 0 "register_operand" "=v")
(ge:V2DI (match_dup 1) (match_dup 2)))])
(compare:CCVFHE (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")))
(set (match_operand:<tointvec> 0 "register_operand" "=v")
(ge:<tointvec> (match_dup 1) (match_dup 2)))])
(set (match_operand:SI 3 "memory_operand" "")
(unspec:SI [(reg:CCVFHE CC_REGNUM)] UNSPEC_CC_TO_INT))]
"TARGET_VX")
; These 3 cannot be merged as the insn defintion above since it also
; requires to rewrite the RTL equality operator that the same time as
; the CC mode.
(define_insn "*vec_cmpeqv2df_cc"
; vfcesbs, vfcedbs, wfcexbs
(define_insn "*vec_cmpeq<mode>_cc"
[(set (reg:CCVEQ CC_REGNUM)
(compare:CCVEQ (match_operand:V2DF 0 "register_operand" "v")
(match_operand:V2DF 1 "register_operand" "v")))
(set (match_operand:V2DI 2 "register_operand" "=v")
(eq:V2DI (match_dup 0) (match_dup 1)))]
(compare:CCVEQ (match_operand:VF_HW 0 "register_operand" "v")
(match_operand:VF_HW 1 "register_operand" "v")))
(set (match_operand:<tointvec> 2 "register_operand" "=v")
(eq:<tointvec> (match_dup 0) (match_dup 1)))]
"TARGET_VX"
"vfcedbs\t%v2,%v0,%v1"
"<vw>fce<sdx>bs\t%v2,%v0,%v1"
[(set_attr "op_type" "VRR")])
(define_insn "*vec_cmphv2df_cc"
[(set (reg:CCVIH CC_REGNUM)
(compare:CCVIH (match_operand:V2DF 0 "register_operand" "v")
(match_operand:V2DF 1 "register_operand" "v")))
(set (match_operand:V2DI 2 "register_operand" "=v")
(gt:V2DI (match_dup 0) (match_dup 1)))]
; vfchsbs, vfchdbs, wfchxbs
(define_insn "*vec_cmph<mode>_cc"
[(set (reg:CCVFH CC_REGNUM)
(compare:CCVFH (match_operand:VF_HW 0 "register_operand" "v")
(match_operand:VF_HW 1 "register_operand" "v")))
(set (match_operand:<tointvec> 2 "register_operand" "=v")
(gt:<tointvec> (match_dup 0) (match_dup 1)))]
"TARGET_VX"
"vfchdbs\t%v2,%v0,%v1"
"<vw>fch<sdx>bs\t%v2,%v0,%v1"
[(set_attr "op_type" "VRR")])
(define_insn "*vec_cmphev2df_cc"
; vfchesbs, vfchedbs, wfchexbs
(define_insn "*vec_cmphe<mode>_cc"
[(set (reg:CCVFHE CC_REGNUM)
(compare:CCVFHE (match_operand:V2DF 0 "register_operand" "v")
(match_operand:V2DF 1 "register_operand" "v")))
(set (match_operand:V2DI 2 "register_operand" "=v")
(ge:V2DI (match_dup 0) (match_dup 1)))]
(compare:CCVFHE (match_operand:VF_HW 0 "register_operand" "v")
(match_operand:VF_HW 1 "register_operand" "v")))
(set (match_operand:<tointvec> 2 "register_operand" "=v")
(ge:<tointvec> (match_dup 0) (match_dup 1)))]
"TARGET_VX"
"vfchedbs\t%v2,%v0,%v1"
"<vw>fche<sdx>bs\t%v2,%v0,%v1"
[(set_attr "op_type" "VRR")])
(define_expand "vec_double_s64"
[(set (match_operand:V2DF 0 "register_operand")
(unspec:V2DF [(match_operand:V2DI 1 "register_operand")
(const_int 0) ; inexact suppression disabled
(const_int VEC_RND_CURRENT)]
UNSPEC_VEC_VCDGB))]
"TARGET_VX")
(define_expand "vec_double_u64"
[(set (match_operand:V2DF 0 "register_operand")
(unspec:V2DF [(match_operand:V2DI 1 "register_operand")
(const_int 0) ; inexact suppression disabled
(const_int VEC_RND_CURRENT)]
UNSPEC_VEC_VCDLGB))]
"TARGET_VX")
(define_insn "vfmin<mode>"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
(unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v")
(match_operand:VF_HW 2 "register_operand" "v")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_VFMIN))]
"TARGET_VXE"
"<vw>fmin<sdx>b\t%v0,%v1,%v2,%b3"
[(set_attr "op_type" "VRR")])
(define_insn "vfmax<mode>"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
(unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v")
(match_operand:VF_HW 2 "register_operand" "v")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_VFMAX))]
"TARGET_VXE"
"<vw>fmax<sdx>b\t%v0,%v1,%v2,%b3"
[(set_attr "op_type" "VRR")])
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/target-attribute/tattr-3.c: Adjust error message
and remove the high-level builtin. The error message for the
would prevent compilation from reaching the second.
* gcc.target/s390/target-attribute/tattr-4.c: Likewise.
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/vxe/negfma-1.c: New test.
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
......
......@@ -16,8 +16,7 @@ void vx1(void)
__attribute__ ((target("arch=z10")))
void vx0(void)
{
vec_load_bndry ((const signed char *)0, 64); /* { dg-error "is not supported without -mvx" } */
__builtin_s390_vll ((unsigned int)0, (const void *)8); /* { dg-error "is not supported without -mvx" } */
__builtin_s390_vll ((unsigned int)0, (const void *)8); /* { dg-error "requires -mvx" } */
}
void vxd(void)
......
......@@ -24,8 +24,7 @@ void a0(void)
#ifdef __VEC__
#error __VEC__ is defined
#endif
vec_load_bndry ((const signed char *)0, 64); /* { dg-error "is not supported without -mvx" } */
__builtin_s390_vll ((unsigned int)0, (const void *)8); /* { dg-error "is not supported without -mvx" } */
__builtin_s390_vll ((unsigned int)0, (const void *)8); /* { dg-error "requires -mvx" } */
}
void d(void)
......@@ -33,6 +32,5 @@ void d(void)
#ifdef __VEC__
#error __VEC__ is defined
#endif
vec_load_bndry ((const signed char *)0, 64); /* { dg-error "is not supported without -mvx" } */
__builtin_s390_vll ((unsigned int)0, (const void *)8); /* { dg-error "is not supported without -mvx" } */
__builtin_s390_vll ((unsigned int)0, (const void *)8); /* { dg-error "requires -mvx" } */
}
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