sparc.md (movdi_insn_sp32): Add o/J alternative.

        * config/sparc/sparc.md (movdi_insn_sp32): Add o/J alternative.
        (movdi_insn_sp32_v9): Likewise.  Only allow stx with aligned memory.
        (dimode mem/zero splitter): New.

From-SVN: r52168

gcc/ChangeLog

+2002-04-11  Richard Henderson  <rth@redhat.com>
+
+	* config/sparc/sparc.md (movdi_insn_sp32): Add o/J alternative.
+	(movdi_insn_sp32_v9): Likewise.  Only allow stx with aligned memory.
+	(dimode mem/zero splitter): New.
+
 2002-04-11  Hans-Peter Nilsson  <hp@axis.com>
 
 	* config/cris/cris.c (cris_override_options): Tweak error message

gcc/config/sparc/sparc.md

-;- Machine description for SPARC chip for GNU C compiler
+;; Machine description for SPARC chip for GNU C compiler
 ;;  Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
 ;;  1999, 2000, 2001, 2002 Free Software Foundation, Inc.
 ;;  Contributed by Michael Tiemann (tiemann@cygnus.com)
@@ -2531,13 +2531,14 @@
 
 (define_insn "*movdi_insn_sp32_v9"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-					"=m,T,U,o,r,r,r,?T,?f,?f,?o,?f")
+					"=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
         (match_operand:DI 1 "input_operand"
-					" J,U,T,r,o,i,r, f, T, o, f, f"))]
+					" J,J,U,T,r,o,i,r, f, T, o, f, f"))]
   "! TARGET_ARCH64 && TARGET_V9
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "@
    stx\\t%%g0, %0
+   #
    std\\t%1, %0
    ldd\\t%1, %0
    #
@@ -2549,18 +2550,19 @@
    #
    #
    #"
-  [(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
-   (set_attr "length" "*,*,*,2,2,2,2,*,*,2,2,2")])
+  [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
+   (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2")])
 
 (define_insn "*movdi_insn_sp32"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-				"=T,U,o,r,r,r,?T,?f,?f,?o,?f")
+				"=o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
         (match_operand:DI 1 "input_operand"
-				" U,T,r,o,i,r, f, T, o, f, f"))]
+				" J,U,T,r,o,i,r, f, T, o, f, f"))]
   "! TARGET_ARCH64
    && (register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode))"
   "@
+   #
    std\\t%1, %0
    ldd\\t%1, %0
    #
@@ -2572,8 +2574,8 @@
    #
    #
    #"
-  [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
-   (set_attr "length" "*,*,2,2,2,2,*,*,2,2,2")])
+  [(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
+   (set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
 
 ;; The following are generated by sparc_emit_set_const64
 (define_insn "*movdi_sp64_dbl"
@@ -2960,6 +2962,21 @@
   DONE;
 }")
 
+(define_split
+  [(set (match_operand:DI 0 "memory_operand" "")
+        (const_int 0))]
+  "reload_completed
+   && (! TARGET_V9
+       || (! TARGET_ARCH64
+	   && ! mem_min_alignment (operands[0], 8)))
+   && offsettable_memref_p (operands[0])"
+  [(clobber (const_int 0))]
+  "
+{
+  emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx));
+  emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx));
+  DONE;
+}")
 
 ;; Floating point move insns