Skip to content

R
riscv-gcc-1
Commit 735cb76e by J"orn Rennecke Committed by Joern Rennecke
Options

sh.h (REG_CLASS_FROM_LETTER): Change to: (REG_CLASS_FROM_CONSTRAINT). 

	* sh.h (REG_CLASS_FROM_LETTER): Change to:
	(REG_CLASS_FROM_CONSTRAINT).
	(CONST_OK_FOR_I): Rename to:
	(CONST_OK_FOR_I08).  Changed all users.
	(CONST_OK_FOR_J): Rename to:
	(CONST_OK_FOR_I16).  Changed all users.
	(CONST_OK_FOR_K): Rename to:
	(CONST_OK_FOR_P27).  Changed all users.
	(CONST_OK_FOR_L): Rename to:
	(CONST_OK_FOR_K08).  Changed all users.
	(CONST_OK_FOR_O): Rename to:
	(CONST_OK_FOR_I06).  Changed all users.
	(CONST_OK_FOR_P): Rename to:
	(CONST_OK_FOR_I10).  Changed all users.
	(CONSTRAINT_LEN, CONST_OK_FOR_I, CONST_OK_FOR_J16): Define.
	(CONST_OK_FOR_J, CONST_OK_FOR_K, CONST_OK_FOR_P): Likewise.
	(EXTRA_CONSTRAINT_A, EXTRA_CONSTRAINT_Bsc): Likewise.
	(EXTRA_CONSTRAINT_B, PIC_OFFSET_P, PIC_DIRECT_ADDR_P): Likewise.
	(EXTRA_CONSTRAINT_Cpg, EXTRA_CONSTRAINT_C): Likewise.
	(EXTRA_MEMORY_CONSTRAINT,(EXTRA_CONSTRAINT_Sr0): Likewise.
	(CONST_OK_FOR_LETTER_P): Replace with
	(CONST_OK_FOR_CONSTRAINT_P).
	(EXTRA_CONSTRAINT_S): Rename to:
	(EXTRA_CONSTRAINT_C16).  Changed all users.
	(MOVI_SHORI_BASE_OPERAND_P): Don't allow direct addresses.
	(EXTRA_CONSTRAINT_T): Rename to:
	(EXTRA_CONSTRAINT_Csy).  Changed all users.
	(EXTRA_CONSTRAINT_Z): Remove.
	(EXTRA_CONSTRAINT): Replace with:
	(EXTRA_CONSTRAINT_STR).
	(EXTRA_CONSTRAINT_U): Rename to:
	 (EXTRA_CONSTRAINT_Z).  Changed all users.
	* sh.c (and_operand): Use CONST_OK_FOR_J16.
	* sh.md (cmpeqsi_t-1, cmpeqsi_t, adddi3_media): Use new constraints.
	(addsi3_media, addsi3_compact, andsi3_compact, anddi3): Likewise.
	(iorsi3, iordi3, xorsi3, xordi3, ashlsi3_std, ashlhi3_k): Likewise.
	(lshrsi3_k, movsi_i, movsi_ie, movsi_i_lowpart, movsi_media): Likewise.
	(movsi_media_nofpu, movqi_media, movhi_i, movhi_media): Likewise.
	(*movdi_i, movdi_media, movdi_media_nofpu, shori_media): Likewise.
	(movdf_media, movdf_media_nofpu, movv2sf_i, movv4sf_i): Likewise.
	(movsf_media, movsf_media_nofpu, movsi_y, beq_media): Likewise.
	(beq_media_i, bne_media, pt, ptb, movv8qi_i, movv2hi_i): Likewise.
	(movv4hi_i, movv2si_i, negcmpeqv8qi, negcmpeqv2si): Likewise.
	(negcmpeqv4hi, negcmpgtuv8qi, negcmpgtv2si, negcmpgtv4hi): Likewise.
	(mcmv, mcnvs_lw, mcnvs_wb, mcnvs_wub, mextr_rl, mextr_lr): Likewise.
	(mextr1, mextr2, mextr3, mextr4, mextr5, mextr6, mextr7): Likewise.
	(mperm_w, mperm_w_little, mperm_w_big, msad_ubq_i): Likewise.
	(mshards_q, mshfhi_b, mshflo_b, mshf4_b, mshf0_b, mshfhi_l): Likewise.
	(mshflo_l, mshf4_l, mshf0_l, mshfhi_w, mshflo_w, mshf4_w): Likewise.
	(mshf0_w, mshflo_w_x, mshfhi_l_di, mshfhi_l_di_rev): Likewise.
	(mshflo_l_di_rev, mshflo_l_di_x, concat_v2sf): Likewise.
	(mshflo_l_di_x_rev, subv2si3, subv4hi3, sssubv2si3): Likewise.
	(sssubv4hi3): Likewise.
	(movsf_i): Change I[08]/r to G/r.
	(movsf_ie): Change f/{G,H}/c/X to f/{G,H}/c/Bsc.

	* sh.c (sh_output_mi_thunk): Use CONST_OK_FOR_ADD.

From-SVN: r68022
parent 0bad3b7c
Showing with 416 additions and 235 deletions
gcc/ChangeLog
2003-06-16 J"orn Rennecke <joern.rennecke@superh.com>
* sh.h (REG_CLASS_FROM_LETTER): Change to:
(REG_CLASS_FROM_CONSTRAINT).
(CONST_OK_FOR_I): Rename to:
(CONST_OK_FOR_I08). Changed all users.
(CONST_OK_FOR_J): Rename to:
(CONST_OK_FOR_I16). Changed all users.
(CONST_OK_FOR_K): Rename to:
(CONST_OK_FOR_P27). Changed all users.
(CONST_OK_FOR_L): Rename to:
(CONST_OK_FOR_K08). Changed all users.
(CONST_OK_FOR_O): Rename to:
(CONST_OK_FOR_I06). Changed all users.
(CONST_OK_FOR_P): Rename to:
(CONST_OK_FOR_I10). Changed all users.
(CONSTRAINT_LEN, CONST_OK_FOR_I, CONST_OK_FOR_J16): Define.
(CONST_OK_FOR_J, CONST_OK_FOR_K, CONST_OK_FOR_P): Likewise.
(EXTRA_CONSTRAINT_A, EXTRA_CONSTRAINT_Bsc): Likewise.
(EXTRA_CONSTRAINT_B, PIC_OFFSET_P, PIC_DIRECT_ADDR_P): Likewise.
(EXTRA_CONSTRAINT_Cpg, EXTRA_CONSTRAINT_C): Likewise.
(EXTRA_MEMORY_CONSTRAINT,(EXTRA_CONSTRAINT_Sr0): Likewise.
(CONST_OK_FOR_LETTER_P): Replace with
(CONST_OK_FOR_CONSTRAINT_P).
(EXTRA_CONSTRAINT_S): Rename to:
(EXTRA_CONSTRAINT_C16). Changed all users.
(MOVI_SHORI_BASE_OPERAND_P): Don't allow direct addresses.
(EXTRA_CONSTRAINT_T): Rename to:
(EXTRA_CONSTRAINT_Csy). Changed all users.
(EXTRA_CONSTRAINT_Z): Remove.
(EXTRA_CONSTRAINT): Replace with:
(EXTRA_CONSTRAINT_STR).
(EXTRA_CONSTRAINT_U): Rename to:
(EXTRA_CONSTRAINT_Z). Changed all users.
* sh.c (and_operand): Use CONST_OK_FOR_J16.
* sh.md (cmpeqsi_t-1, cmpeqsi_t, adddi3_media): Use new constraints.
(addsi3_media, addsi3_compact, andsi3_compact, anddi3): Likewise.
(iorsi3, iordi3, xorsi3, xordi3, ashlsi3_std, ashlhi3_k): Likewise.
(lshrsi3_k, movsi_i, movsi_ie, movsi_i_lowpart, movsi_media): Likewise.
(movsi_media_nofpu, movqi_media, movhi_i, movhi_media): Likewise.
(*movdi_i, movdi_media, movdi_media_nofpu, shori_media): Likewise.
(movdf_media, movdf_media_nofpu, movv2sf_i, movv4sf_i): Likewise.
(movsf_media, movsf_media_nofpu, movsi_y, beq_media): Likewise.
(beq_media_i, bne_media, pt, ptb, movv8qi_i, movv2hi_i): Likewise.
(movv4hi_i, movv2si_i, negcmpeqv8qi, negcmpeqv2si): Likewise.
(negcmpeqv4hi, negcmpgtuv8qi, negcmpgtv2si, negcmpgtv4hi): Likewise.
(mcmv, mcnvs_lw, mcnvs_wb, mcnvs_wub, mextr_rl, mextr_lr): Likewise.
(mextr1, mextr2, mextr3, mextr4, mextr5, mextr6, mextr7): Likewise.
(mperm_w, mperm_w_little, mperm_w_big, msad_ubq_i): Likewise.
(mshards_q, mshfhi_b, mshflo_b, mshf4_b, mshf0_b, mshfhi_l): Likewise.
(mshflo_l, mshf4_l, mshf0_l, mshfhi_w, mshflo_w, mshf4_w): Likewise.
(mshf0_w, mshflo_w_x, mshfhi_l_di, mshfhi_l_di_rev): Likewise.
(mshflo_l_di_rev, mshflo_l_di_x, concat_v2sf): Likewise.
(mshflo_l_di_x_rev, subv2si3, subv4hi3, sssubv2si3): Likewise.
(sssubv4hi3): Likewise.
(movsf_i): Change I[08]/r to G/r.
(movsf_ie): Change f/{G,H}/c/X to f/{G,H}/c/Bsc.
* sh.c (sh_output_mi_thunk): Use CONST_OK_FOR_ADD.
2003-06-16 Vladimir Makarov <vmakarov@redhat.com> 2003-06-16 Vladimir Makarov <vmakarov@redhat.com>
* config/i386/i386.c (ix86_memory_move_cost): Fix typo. * config/i386/i386.c (ix86_memory_move_cost): Fix typo.
......
gcc/config/sh/sh.c
...@@ -56,7 +56,7 @@ int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch; ...@@ -56,7 +56,7 @@ int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
/* These are some macros to abstract register modes. */ /* These are some macros to abstract register modes. */
#define CONST_OK_FOR_ADD(size) \ #define CONST_OK_FOR_ADD(size) \
(TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size)) (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
#define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi)) #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
#define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3)) #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
#define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3)) #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
...@@ -1489,8 +1489,8 @@ andcosts (x) ...@@ -1489,8 +1489,8 @@ andcosts (x)
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
{ {
if ((GET_CODE (XEXP (x, 1)) == CONST_INT if ((GET_CODE (XEXP (x, 1)) == CONST_INT
&& CONST_OK_FOR_J (INTVAL (XEXP (x, 1)))) && CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
|| EXTRA_CONSTRAINT_S (XEXP (x, 1))) || EXTRA_CONSTRAINT_C16 (XEXP (x, 1)))
return 1; return 1;
else else
return 2; return 2;
...@@ -1499,13 +1499,13 @@ andcosts (x) ...@@ -1499,13 +1499,13 @@ andcosts (x)
/* These constants are single cycle extu.[bw] instructions. */ /* These constants are single cycle extu.[bw] instructions. */
if (i == 0xff || i == 0xffff) if (i == 0xff || i == 0xffff)
return 1; return 1;
/* Constants that can be used in an and immediate instruction is a single /* Constants that can be used in an and immediate instruction in a single
cycle, but this requires r0, so make it a little more expensive. */ cycle, but this requires r0, so make it a little more expensive. */
if (CONST_OK_FOR_L (i)) if (CONST_OK_FOR_K08 (i))
return 2; return 2;
/* Constants that can be loaded with a mov immediate and an and. /* Constants that can be loaded with a mov immediate and an and.
This case is probably unnecessary. */ This case is probably unnecessary. */
if (CONST_OK_FOR_I (i)) if (CONST_OK_FOR_I08 (i))
return 2; return 2;
/* Any other constants requires a 2 cycle pc-relative load plus an and. /* Any other constants requires a 2 cycle pc-relative load plus an and.
This case is probably unnecessary. */ This case is probably unnecessary. */
...@@ -1537,11 +1537,11 @@ addsubcosts (x) ...@@ -1537,11 +1537,11 @@ addsubcosts (x)
return TARGET_SHMEDIA64 ? 5 : 3; return TARGET_SHMEDIA64 ? 5 : 3;
case CONST_INT: case CONST_INT:
if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1)))) if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
return 2; return 2;
else if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1)) >> 16)) else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
return 3; return 3;
else if (CONST_OK_FOR_J ((INTVAL (XEXP (x, 1)) >> 16) >> 16)) else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
return 4; return 4;
/* Fall through. */ /* Fall through. */
...@@ -1601,22 +1601,22 @@ sh_rtx_costs (x, code, outer_code, total) ...@@ -1601,22 +1601,22 @@ sh_rtx_costs (x, code, outer_code, total)
*total = 0; *total = 0;
else if ((outer_code == IOR || outer_code == XOR else if ((outer_code == IOR || outer_code == XOR
|| outer_code == PLUS) || outer_code == PLUS)
&& CONST_OK_FOR_P (INTVAL (x))) && CONST_OK_FOR_I10 (INTVAL (x)))
*total = 0; *total = 0;
else if (CONST_OK_FOR_J (INTVAL (x))) else if (CONST_OK_FOR_I16 (INTVAL (x)))
*total = COSTS_N_INSNS (outer_code != SET); *total = COSTS_N_INSNS (outer_code != SET);
else if (CONST_OK_FOR_J (INTVAL (x) >> 16)) else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
*total = COSTS_N_INSNS (2); *total = COSTS_N_INSNS (2);
else if (CONST_OK_FOR_J ((INTVAL (x) >> 16) >> 16)) else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
*total = COSTS_N_INSNS (3); *total = COSTS_N_INSNS (3);
else else
*total = COSTS_N_INSNS (4); *total = COSTS_N_INSNS (4);
return true; return true;
} }
if (CONST_OK_FOR_I (INTVAL (x))) if (CONST_OK_FOR_I08 (INTVAL (x)))
*total = 0; *total = 0;
else if ((outer_code == AND || outer_code == IOR || outer_code == XOR) else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
&& CONST_OK_FOR_L (INTVAL (x))) && CONST_OK_FOR_K08 (INTVAL (x)))
*total = 1; *total = 1;
else else
*total = 8; *total = 8;
...@@ -2034,7 +2034,7 @@ shl_and_kind (left_rtx, mask_rtx, attrp) ...@@ -2034,7 +2034,7 @@ shl_and_kind (left_rtx, mask_rtx, attrp)
{ {
if (i > right) if (i > right)
break; break;
if (! CONST_OK_FOR_L (mask >> i)) if (! CONST_OK_FOR_K08 (mask >> i))
continue; continue;
cost = (i != 0) + 2 + ext_shift_insns[left + i]; cost = (i != 0) + 2 + ext_shift_insns[left + i];
if (cost < best_cost) if (cost < best_cost)
...@@ -2051,14 +2051,14 @@ shl_and_kind (left_rtx, mask_rtx, attrp) ...@@ -2051,14 +2051,14 @@ shl_and_kind (left_rtx, mask_rtx, attrp)
{ {
if (i > right) if (i > right)
break; break;
cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3) cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
+ (can_ext ? ext_shift_insns : shift_insns)[left + i]; + (can_ext ? ext_shift_insns : shift_insns)[left + i];
if (cost < best_cost) if (cost < best_cost)
{ {
best = 4 - can_ext; best = 4 - can_ext;
best_cost = cost; best_cost = cost;
best_right = i; best_right = i;
best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i); best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
} }
} }
...@@ -2836,8 +2836,8 @@ hi_const (src) ...@@ -2836,8 +2836,8 @@ hi_const (src)
/* Nonzero if the insn is a move instruction which needs to be fixed. */ /* Nonzero if the insn is a move instruction which needs to be fixed. */
/* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
need to fix it if the input value is CONST_OK_FOR_I. */ need to fix it if the input value is CONST_OK_FOR_I08. */
static int static int
broken_move (insn) broken_move (insn)
...@@ -2874,7 +2874,7 @@ broken_move (insn) ...@@ -2874,7 +2874,7 @@ broken_move (insn)
&& GET_CODE (SET_DEST (pat)) == REG && GET_CODE (SET_DEST (pat)) == REG
&& FP_REGISTER_P (REGNO (SET_DEST (pat)))) && FP_REGISTER_P (REGNO (SET_DEST (pat))))
&& (GET_CODE (SET_SRC (pat)) != CONST_INT && (GET_CODE (SET_SRC (pat)) != CONST_INT
|| ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat))))) || ! CONST_OK_FOR_I08 (INTVAL (SET_SRC (pat)))))
return 1; return 1;
} }
...@@ -6383,17 +6383,17 @@ arith_operand (op, mode) ...@@ -6383,17 +6383,17 @@ arith_operand (op, mode)
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
{ {
/* FIXME: We should be checking whether the CONST_INT fits in a /* FIXME: We should be checking whether the CONST_INT fits in a
CONST_OK_FOR_J here, but this causes reload_cse to crash when CONST_OK_FOR_I16 here, but this causes reload_cse to crash when
attempting to transform a sequence of two 64-bit sets of the attempting to transform a sequence of two 64-bit sets of the
same register from literal constants into a set and an add, same register from literal constants into a set and an add,
when the difference is too wide for an add. */ when the difference is too wide for an add. */
if (GET_CODE (op) == CONST_INT if (GET_CODE (op) == CONST_INT
|| EXTRA_CONSTRAINT_S (op)) || EXTRA_CONSTRAINT_C16 (op))
return 1; return 1;
else else
return 0; return 0;
} }
else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op))) else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (op)))
return 1; return 1;
return 0; return 0;
...@@ -6409,7 +6409,7 @@ arith_reg_or_0_operand (op, mode) ...@@ -6409,7 +6409,7 @@ arith_reg_or_0_operand (op, mode)
if (arith_reg_operand (op, mode)) if (arith_reg_operand (op, mode))
return 1; return 1;
if (EXTRA_CONSTRAINT_U (op)) if (EXTRA_CONSTRAINT_Z (op))
return 1; return 1;
return 0; return 0;
...@@ -6424,7 +6424,7 @@ shmedia_6bit_operand (op, mode) ...@@ -6424,7 +6424,7 @@ shmedia_6bit_operand (op, mode)
enum machine_mode mode; enum machine_mode mode;
{ {
return (arith_reg_operand (op, mode) return (arith_reg_operand (op, mode)
|| (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))); || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I06 (INTVAL (op))));
} }
/* Returns 1 if OP is a valid source operand for a logical operation. */ /* Returns 1 if OP is a valid source operand for a logical operation. */
...@@ -6439,12 +6439,12 @@ logical_operand (op, mode) ...@@ -6439,12 +6439,12 @@ logical_operand (op, mode)
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
{ {
if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_P (INTVAL (op))) if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I10 (INTVAL (op)))
return 1; return 1;
else else
return 0; return 0;
} }
else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op))) else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K08 (INTVAL (op)))
return 1; return 1;
return 0; return 0;
...@@ -6462,8 +6462,7 @@ and_operand (op, mode) ...@@ -6462,8 +6462,7 @@ and_operand (op, mode)
if (TARGET_SHMEDIA if (TARGET_SHMEDIA
&& mode == DImode && mode == DImode
&& GET_CODE (op) == CONST_INT && GET_CODE (op) == CONST_INT
&& (INTVAL (op) == (unsigned) 0xffffffff && CONST_OK_FOR_J16 (INTVAL (op)))
|| INTVAL (op) == (HOST_WIDE_INT) -1 << 32))
return 1; return 1;
return 0; return 0;
...@@ -6738,7 +6737,7 @@ target_operand (op, mode) ...@@ -6738,7 +6737,7 @@ target_operand (op, mode)
return 0; return 0;
if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode) if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
&& EXTRA_CONSTRAINT_T (op)) && EXTRA_CONSTRAINT_Csy (op))
return ! reload_completed; return ! reload_completed;
return target_reg_operand (op, mode); return target_reg_operand (op, mode);
...@@ -8327,8 +8326,7 @@ sh_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) ...@@ -8327,8 +8326,7 @@ sh_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
int structure_value_byref = 0; int structure_value_byref = 0;
rtx this, this_value, sibcall, insns, funexp; rtx this, this_value, sibcall, insns, funexp;
tree funtype = TREE_TYPE (function); tree funtype = TREE_TYPE (function);
int simple_add int simple_add = CONST_OK_FOR_ADD (delta);
= (TARGET_SHMEDIA ? CONST_OK_FOR_J (delta) : CONST_OK_FOR_I (delta));
int did_load = 0; int did_load = 0;
rtx scratch0, scratch1, scratch2; rtx scratch0, scratch1, scratch2;
...@@ -8411,9 +8409,7 @@ sh_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) ...@@ -8411,9 +8409,7 @@ sh_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
emit_move_insn (scratch1, GEN_INT (vcall_offset)); emit_move_insn (scratch1, GEN_INT (vcall_offset));
offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1); offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
} }
else if (TARGET_SHMEDIA else if (CONST_OK_FOR_ADD (vcall_offset))
? CONST_OK_FOR_J (vcall_offset)
: CONST_OK_FOR_I (vcall_offset))
{ {
emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset))); emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
offset_addr = scratch0; offset_addr = scratch0;
......
gcc/config/sh/sh.h
...@@ -1293,46 +1293,119 @@ extern int regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1293,46 +1293,119 @@ extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
description. */ description. */
extern enum reg_class reg_class_from_letter[]; extern enum reg_class reg_class_from_letter[];
#define REG_CLASS_FROM_LETTER(C) \ /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
( ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS ) #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
(ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
/* Overview of uppercase letter constraints:
A: Addresses (constraint len == 3)
Ac4: sh4 cache operations
Ac5: sh5 cache operations
Bxx: miscellaneous constraints
Bsc: SCRATCH - for the scratch register in movsi_ie in the
fldi0 / fldi0 cases
C: Constants other than only CONST_INT (constraint len == 3)
C16: 16 bit constant, literal or symbolic
Csy: label or symbol
Cpg: non-explicit constants that can be directly loaded into a general
purpose register in PIC code. like 's' except we don't allow
PIC_DIRECT_ADDR_P
IJKLMNOP: CONT_INT constants
Ixx: signed xx bit
J16: 0xffffffff00000000 | 0x00000000ffffffff
Kxx: unsigned xx bit
M: 1
N: 0
P27: 1 | 2 | 8 | 16
Q: pc relative load operand
Rxx: reserved for exotic register classes.
S: extra memory (storage) constraints (constraint len == 3)
Sua: unaligned memory operations
W: vector
Z: zero in any mode
unused CONST_INT constraint letters: LO
unused EXTRA_CONSTRAINT letters: D T U Y */
#if 1 /* check that the transistion went well. */
#define CONSTRAINT_LEN(C,STR) \
(((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
|| (C) == 'Y' \
|| ((C) == 'I' && (((STR)[1] != '0' && (STR)[1] != '1') || ! isdigit ((STR)[2]))) \
|| ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
|| ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
|| ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
|| ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
? -1 \
: ((C) == 'A' || (C) == 'B' || (C) == 'C' \
|| (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
|| (C) == 'R' || (C) == 'S') \
? 3 \
: DEFAULT_CONSTRAINT_LEN ((C), (STR)))
#else
#define CONSTRAINT_LEN(C,STR) \
(((C) == 'A' || (C) == 'B' || (C) == 'C' \
|| (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
|| (C) == 'R' || (C) == 'S') \
? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
#endif
/* The letters I, J, K, L and M in a register constraint string /* The letters I, J, K, L and M in a register constraint string
can be used to stand for particular ranges of immediate operands. can be used to stand for particular ranges of immediate operands.
This macro defines what the ranges are. This macro defines what the ranges are.
C is the letter, and VALUE is a constant value. C is the letter, and VALUE is a constant value.
Return 1 if VALUE is in the range specified by C. Return 1 if VALUE is in the range specified by C.
I: arithmetic operand -127..128, as used in add, sub, etc I08: arithmetic operand -127..128, as used in add, sub, etc
J: arithmetic operand -32768..32767, as used in SHmedia movi and shori I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
K: shift operand 1,2,8 or 16 P27: shift operand 1,2,8 or 16
L: logical operand 0..255, as used in and, or, etc. K08: logical operand 0..255, as used in and, or, etc.
M: constant 1 M: constant 1
N: constant 0 N: constant 0
O: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
P: arithmetic operand -512..511, as used in SHmedia andi, ori I10: arithmetic operand -512..511, as used in SHmedia andi, ori
*/ */
#define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
&& ((HOST_WIDE_INT)(VALUE)) <= 127) && ((HOST_WIDE_INT)(VALUE)) <= 31)
#define CONST_OK_FOR_J(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \ #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
&& ((HOST_WIDE_INT)(VALUE)) <= 32767) && ((HOST_WIDE_INT)(VALUE)) <= 127)
#define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16) #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
#define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ && ((HOST_WIDE_INT)(VALUE)) <= 511)
&& ((HOST_WIDE_INT)(VALUE)) <= 255) #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
&& ((HOST_WIDE_INT)(VALUE)) <= 32767)
#define CONST_OK_FOR_I(VALUE, STR) \
((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
: (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
: (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
: (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
: 0)
#define CONST_OK_FOR_J16(VALUE) \
((unsigned) (VALUE) == (unsigned) 0xffffffff \
|| (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
#define CONST_OK_FOR_J(VALUE, STR) \
((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
: 0)
#define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
&& ((HOST_WIDE_INT)(VALUE)) <= 255)
#define CONST_OK_FOR_K(VALUE, STR) \
((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
: 0)
#define CONST_OK_FOR_P27(VALUE) \
((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
#define CONST_OK_FOR_P(VALUE, STR) \
((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
: 0)
#define CONST_OK_FOR_M(VALUE) ((VALUE)==1) #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
#define CONST_OK_FOR_N(VALUE) ((VALUE)==0) #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
#define CONST_OK_FOR_O(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \ #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
&& ((HOST_WIDE_INT)(VALUE)) <= 31) ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
#define CONST_OK_FOR_P(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \ : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
&& ((HOST_WIDE_INT)(VALUE)) <= 511) : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
#define CONST_OK_FOR_LETTER_P(VALUE, C) \ : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
: (C) == 'J' ? CONST_OK_FOR_J (VALUE) \ : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
: (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
: (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
: (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
: (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
: (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
: (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
: 0) : 0)
/* Similar, but for floating constants, and defining letters G and H. /* Similar, but for floating constants, and defining letters G and H.
...@@ -1403,7 +1476,7 @@ extern enum reg_class reg_class_from_letter[]; ...@@ -1403,7 +1476,7 @@ extern enum reg_class reg_class_from_letter[];
|| GET_CODE (X) == PLUS)) \ || GET_CODE (X) == PLUS)) \
? GENERAL_REGS \ ? GENERAL_REGS \
: CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \ : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \ ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
? GENERAL_REGS \ ? GENERAL_REGS \
: R0_REGS) \ : R0_REGS) \
: (CLASS == FPSCR_REGS \ : (CLASS == FPSCR_REGS \
...@@ -2300,8 +2373,19 @@ while (0) ...@@ -2300,8 +2373,19 @@ while (0)
&& GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \ && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
&& GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT))) && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
/* The `S' constraint is a 16-bit constant, literal or symbolic. */ /* Extra address constraints. */
#define EXTRA_CONSTRAINT_S(OP) \ #define EXTRA_CONSTRAINT_A(OP, STR) 0
/* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
operand is not SCRATCH (i.e. REG) then R0 is probably being
used, hence mova is being used, hence do not select this pattern */
#define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
#define EXTRA_CONSTRAINT_B(OP, STR) \
((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
: 0)
/* The `C16' constraint is a 16-bit constant, literal or symbolic. */
#define EXTRA_CONSTRAINT_C16(OP) \
(GET_CODE (OP) == CONST \ (GET_CODE (OP) == CONST \
&& GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \ && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
&& GET_MODE (XEXP ((OP), 0)) == DImode \ && GET_MODE (XEXP ((OP), 0)) == DImode \
...@@ -2350,6 +2434,14 @@ while (0) ...@@ -2350,6 +2434,14 @@ while (0)
(GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
&& XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
#define PIC_OFFSET_P(OP) \
(PIC_ADDR_P (OP) \
&& GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
&& reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
#define PIC_DIRECT_ADDR_P(OP) \
(PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
#define NON_PIC_REFERENCE_P(OP) \ #define NON_PIC_REFERENCE_P(OP) \
(GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
|| DATALABEL_REF_P (OP) \ || DATALABEL_REF_P (OP) \
...@@ -2363,14 +2455,17 @@ while (0) ...@@ -2363,14 +2455,17 @@ while (0)
|| GOTOFF_P (OP) || PIC_ADDR_P (OP)) || GOTOFF_P (OP) || PIC_ADDR_P (OP))
#define MOVI_SHORI_BASE_OPERAND_P(OP) \ #define MOVI_SHORI_BASE_OPERAND_P(OP) \
(flag_pic ? PIC_REFERENCE_P (OP) : NON_PIC_REFERENCE_P (OP)) (flag_pic \
? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
|| PIC_OFFSET_P (OP)) \
: NON_PIC_REFERENCE_P (OP))
/* The `T' constraint is a label or a symbol. */ /* The `Csy' constraint is a label or a symbol. */
#define EXTRA_CONSTRAINT_T(OP) \ #define EXTRA_CONSTRAINT_Csy(OP) \
(NON_PIC_REFERENCE_P (OP)) (NON_PIC_REFERENCE_P (OP))
/* A zero in any shape or form. */ /* A zero in any shape or form. */
#define EXTRA_CONSTRAINT_U(OP) \ #define EXTRA_CONSTRAINT_Z(OP) \
((OP) == CONST0_RTX (GET_MODE (OP))) ((OP) == CONST0_RTX (GET_MODE (OP)))
/* Any vector constant we can handle. */ /* Any vector constant we can handle. */
...@@ -2381,18 +2476,38 @@ while (0) ...@@ -2381,18 +2476,38 @@ while (0)
? sh_const_vec ((OP), VOIDmode) \ ? sh_const_vec ((OP), VOIDmode) \
: sh_1el_vec ((OP), VOIDmode)))) : sh_1el_vec ((OP), VOIDmode))))
#define EXTRA_CONSTRAINT_Z(OP) \ /* A non-explicit constant that can be loaded directly into a general purpose
(GET_CODE (OP) == CONST_INT \ register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
&& (INTVAL (OP) == (unsigned) 0xffffffff \ #define EXTRA_CONSTRAINT_Cpg(OP) \
|| INTVAL (OP) == (HOST_WIDE_INT) -1 << 32)) (CONSTANT_P (OP) \
&& GET_CODE (OP) != CONST_INT \
&& GET_CODE (OP) != CONST_DOUBLE \
&& (!flag_pic \
|| (LEGITIMATE_PIC_OPERAND_P (OP) \
&& (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
&& GET_CODE (OP) != LABEL_REF)))
#define EXTRA_CONSTRAINT_C(OP, STR) \
((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
: (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
: (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
: 0)
#define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
#define EXTRA_CONSTRAINT_Sr0(OP) \
(memory_operand((OP), GET_MODE (OP)) \
&& ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
#define EXTRA_CONSTRAINT_S(OP, STR) \
((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
: 0)
#define EXTRA_CONSTRAINT(OP, C) \ #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \ ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
: (C) == 'S' ? EXTRA_CONSTRAINT_S (OP) \ : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
: (C) == 'T' ? EXTRA_CONSTRAINT_T (OP) \ : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
: (C) == 'U' ? EXTRA_CONSTRAINT_U (OP) \ : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
: (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
: (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \ : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
: (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \ : (C) == 'U' ? EXTRA_CONSTRAINT_Z (OP) \
: 0) : 0)
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
......
gcc/config/sh/sh.md
...@@ -628,7 +628,7 @@ ...@@ -628,7 +628,7 @@
(define_insn "" (define_insn ""
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r") (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
(match_operand:SI 1 "arith_operand" "L,r")) (match_operand:SI 1 "arith_operand" "K08,r"))
(const_int 0)))] (const_int 0)))]
"TARGET_SH1" "TARGET_SH1"
"tst %1,%0" "tst %1,%0"
...@@ -643,7 +643,7 @@ ...@@ -643,7 +643,7 @@
(define_insn "cmpeqsi_t" (define_insn "cmpeqsi_t"
[(set (reg:SI T_REG) [(set (reg:SI T_REG)
(eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r") (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
(match_operand:SI 1 "arith_operand" "N,rI,r")))] (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
"TARGET_SH1" "TARGET_SH1"
"@ "@
tst %0,%0 tst %0,%0
...@@ -997,7 +997,7 @@ ...@@ -997,7 +997,7 @@
(define_insn "*adddi3_media" (define_insn "*adddi3_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r") [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r") (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
(match_operand:DI 2 "arith_operand" "r,P")))] (match_operand:DI 2 "arith_operand" "r,I10")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"@ "@
add %1, %2, %0 add %1, %2, %0
...@@ -1079,7 +1079,7 @@ ...@@ -1079,7 +1079,7 @@
(define_insn "addsi3_media" (define_insn "addsi3_media"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r") [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
(plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r") (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
(match_operand:SI 2 "arith_operand" "r,P")))] (match_operand:SI 2 "arith_operand" "r,I10")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"@ "@
add.l %1, %2, %0 add.l %1, %2, %0
...@@ -1089,7 +1089,7 @@ ...@@ -1089,7 +1089,7 @@
(define_insn "*addsi3_compact" (define_insn "*addsi3_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r") [(set (match_operand:SI 0 "arith_reg_operand" "=r")
(plus:SI (match_operand:SI 1 "arith_operand" "%0") (plus:SI (match_operand:SI 1 "arith_operand" "%0")
(match_operand:SI 2 "arith_operand" "rI")))] (match_operand:SI 2 "arith_operand" "rI08")))]
"TARGET_SH1" "TARGET_SH1"
"add %2,%0" "add %2,%0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
...@@ -1950,7 +1950,7 @@ ...@@ -1950,7 +1950,7 @@
(define_insn "*andsi3_compact" (define_insn "*andsi3_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,z") [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
(and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
(match_operand:SI 2 "logical_operand" "r,L")))] (match_operand:SI 2 "logical_operand" "r,K08")))]
"TARGET_SH1" "TARGET_SH1"
"and %2,%0" "and %2,%0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
...@@ -1976,7 +1976,7 @@ ...@@ -1976,7 +1976,7 @@
(define_insn_and_split "anddi3" (define_insn_and_split "anddi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r,r") [(set (match_operand:DI 0 "arith_reg_operand" "=r,r,r")
(and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r") (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
(match_operand:DI 2 "and_operand" "r,P,Z")))] (match_operand:DI 2 "and_operand" "r,I10,J16")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"@ "@
and %1, %2, %0 and %1, %2, %0
...@@ -2006,7 +2006,7 @@ ...@@ -2006,7 +2006,7 @@
(define_insn "iorsi3" (define_insn "iorsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,z") [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
(match_operand:SI 2 "logical_operand" "r,L")))] (match_operand:SI 2 "logical_operand" "r,K08")))]
"TARGET_SH1" "TARGET_SH1"
"or %2,%0" "or %2,%0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
...@@ -2014,7 +2014,7 @@ ...@@ -2014,7 +2014,7 @@
(define_insn "iordi3" (define_insn "iordi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r") [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r") (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
(match_operand:DI 2 "logical_operand" "r,P")))] (match_operand:DI 2 "logical_operand" "r,I10")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"@ "@
or %1, %2, %0 or %1, %2, %0
...@@ -2024,7 +2024,7 @@ ...@@ -2024,7 +2024,7 @@
(define_insn "xorsi3" (define_insn "xorsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "=z,r") [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
(xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
(match_operand:SI 2 "logical_operand" "L,r")))] (match_operand:SI 2 "logical_operand" "K08,r")))]
"TARGET_SH1" "TARGET_SH1"
"xor %2,%0" "xor %2,%0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
...@@ -2032,7 +2032,7 @@ ...@@ -2032,7 +2032,7 @@
(define_insn "xordi3" (define_insn "xordi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r") [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r") (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
(match_operand:DI 2 "shmedia_6bit_operand" "r,O")))] (match_operand:DI 2 "shmedia_6bit_operand" "r,I06")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"@ "@
xor %1, %2, %0 xor %1, %2, %0
...@@ -2224,11 +2224,11 @@ ...@@ -2224,11 +2224,11 @@
(define_insn_and_split "ashlsi3_std" (define_insn_and_split "ashlsi3_std"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r") [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0") (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
(match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri"))) (match_operand:SI 2 "nonmemory_operand" "r,M,P27,?ri")))
(clobber (match_scratch:SI 3 "=X,X,X,&r"))] (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
"TARGET_SH3 "TARGET_SH3
|| (TARGET_SH1 && GET_CODE (operands[2]) == CONST_INT || (TARGET_SH1 && GET_CODE (operands[2]) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (operands[2])))" && CONST_OK_FOR_P27 (INTVAL (operands[2])))"
"@ "@
shld %2,%0 shld %2,%0
add %0,%0 add %0,%0
...@@ -2237,7 +2237,7 @@ ...@@ -2237,7 +2237,7 @@
"TARGET_SH3 "TARGET_SH3
&& reload_completed && reload_completed
&& GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (operands[2]))" && ! CONST_OK_FOR_P27 (INTVAL (operands[2]))"
[(set (match_dup 3) (match_dup 2)) [(set (match_dup 3) (match_dup 2))
(parallel (parallel
[(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3))) [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
...@@ -2249,8 +2249,8 @@ ...@@ -2249,8 +2249,8 @@
(define_insn "ashlhi3_k" (define_insn "ashlhi3_k"
[(set (match_operand:HI 0 "arith_reg_operand" "=r,r") [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0") (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
(match_operand:HI 2 "const_int_operand" "M,K")))] (match_operand:HI 2 "const_int_operand" "M,P27")))]
"TARGET_SH1 && CONST_OK_FOR_K (INTVAL (operands[2]))" "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))"
"@ "@
add %0,%0 add %0,%0
shll%O2 %0" shll%O2 %0"
...@@ -2494,8 +2494,8 @@ ...@@ -2494,8 +2494,8 @@
(define_insn "lshrsi3_k" (define_insn "lshrsi3_k"
[(set (match_operand:SI 0 "arith_reg_operand" "=r") [(set (match_operand:SI 0 "arith_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
(match_operand:SI 2 "const_int_operand" "K")))] (match_operand:SI 2 "const_int_operand" "P27")))]
"TARGET_SH1 && CONST_OK_FOR_K (INTVAL (operands[2])) "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))
&& ! CONST_OK_FOR_M (INTVAL (operands[2]))" && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
"shlr%O2 %0" "shlr%O2 %0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
...@@ -3385,8 +3385,10 @@ ...@@ -3385,8 +3385,10 @@
;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0) ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T. ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
(define_insn "movsi_i" (define_insn "movsi_i"
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r") [(set (match_operand:SI 0 "general_movdst_operand"
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))] "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
(match_operand:SI 1 "general_movsrc_operand"
"Q,rI08,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
"TARGET_SH1 "TARGET_SH1
&& ! TARGET_SH2E && ! TARGET_SH2E
&& (register_operand (operands[0], SImode) && (register_operand (operands[0], SImode)
...@@ -3417,8 +3419,10 @@ ...@@ -3417,8 +3419,10 @@
;; ??? We can't include f/f because we need the proper FPSCR setting when ;; ??? We can't include f/f because we need the proper FPSCR setting when
;; TARGET_FMOVD is in effect, and mode switching is done before reload. ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
(define_insn "movsi_ie" (define_insn "movsi_ie"
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y") [(set (match_operand:SI 0 "general_movdst_operand"
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))] "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
(match_operand:SI 1 "general_movsrc_operand"
"Q,rI08,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
"TARGET_SH2E "TARGET_SH2E
&& (register_operand (operands[0], SImode) && (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))" || register_operand (operands[1], SImode))"
...@@ -3452,7 +3456,7 @@ ...@@ -3452,7 +3456,7 @@
(define_insn "movsi_i_lowpart" (define_insn "movsi_i_lowpart"
[(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r")) [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,x,l,t,r,i"))] (match_operand:SI 1 "general_movsrc_operand" "Q,rI08,mr,x,l,t,r,i"))]
"TARGET_SH1 "TARGET_SH1
&& (register_operand (operands[0], SImode) && (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))" || register_operand (operands[1], SImode))"
...@@ -3468,8 +3472,10 @@ ...@@ -3468,8 +3472,10 @@
[(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")]) [(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
(define_insn "*movsi_media" (define_insn "*movsi_media"
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,f,m,f,r,f,*b,r,b") [(set (match_operand:SI 0 "general_movdst_operand"
(match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,rU,m,f,rU,f,f,r,*b,T"))] "=r,r,r,r,m,f,m,f,r,f,*b,r,b")
(match_operand:SI 1 "general_movsrc_operand"
"r,I16C16,nCpg,m,rZ,m,f,rZ,f,f,r,*b,Csy"))]
"TARGET_SHMEDIA_FPU "TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], SImode) && (register_operand (operands[0], SImode)
|| sh_register_operand (operands[1], SImode))" || sh_register_operand (operands[1], SImode))"
...@@ -3491,8 +3497,10 @@ ...@@ -3491,8 +3497,10 @@
(set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")]) (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")])
(define_insn "*movsi_media_nofpu" (define_insn "*movsi_media_nofpu"
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,*b,r,b") [(set (match_operand:SI 0 "general_movdst_operand"
(match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,rU,r,*b,T"))] "=r,r,r,r,m,*b,r,b")
(match_operand:SI 1 "general_movsrc_operand"
"r,I16C16,nCpg,m,rZ,r,*b,Csy"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (register_operand (operands[0], SImode) && (register_operand (operands[0], SImode)
|| sh_register_operand (operands[1], SImode))" || sh_register_operand (operands[1], SImode))"
...@@ -3525,7 +3533,7 @@ ...@@ -3525,7 +3533,7 @@
(match_operand:SI 1 "immediate_operand" ""))] (match_operand:SI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed "TARGET_SHMEDIA && reload_completed
&& ((GET_CODE (operands[1]) == CONST_INT && ((GET_CODE (operands[1]) == CONST_INT
&& ! CONST_OK_FOR_J (INTVAL (operands[1]))) && ! CONST_OK_FOR_I16 (INTVAL (operands[1])))
|| GET_CODE (operands[1]) == CONST_DOUBLE)" || GET_CODE (operands[1]) == CONST_DOUBLE)"
[(set (subreg:DI (match_dup 0) 0) (match_dup 1))]) [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
...@@ -3641,7 +3649,7 @@ ...@@ -3641,7 +3649,7 @@
(define_insn "*movqi_media" (define_insn "*movqi_media"
[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m") [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
(match_operand:QI 1 "general_movsrc_operand" "r,JS,m,rU"))] (match_operand:QI 1 "general_movsrc_operand" "r,I16C16,m,rZ"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (arith_reg_operand (operands[0], QImode) && (arith_reg_operand (operands[0], QImode)
|| arith_reg_or_0_operand (operands[1], QImode))" || arith_reg_or_0_operand (operands[1], QImode))"
...@@ -3676,8 +3684,8 @@ ...@@ -3676,8 +3684,8 @@
/* When storing r0, we have to avoid reg+reg addressing. */ /* When storing r0, we have to avoid reg+reg addressing. */
(define_insn "movhi_i" (define_insn "movhi_i"
[(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r") [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
(match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))] (match_operand:HI 1 "general_movsrc_operand" "Q,rI08,m,t,r,l,r,i"))]
"TARGET_SH1 "TARGET_SH1
&& (arith_reg_operand (operands[0], HImode) && (arith_reg_operand (operands[0], HImode)
|| arith_reg_operand (operands[1], HImode)) || arith_reg_operand (operands[1], HImode))
...@@ -3697,8 +3705,8 @@ ...@@ -3697,8 +3705,8 @@
[(set_attr "type" "pcload,move,load,move,store,move,move,pcload")]) [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
(define_insn "*movhi_media" (define_insn "*movhi_media"
[(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m") [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
(match_operand:HI 1 "general_movsrc_operand" "r,JS,n,m,rU"))] (match_operand:HI 1 "general_movsrc_operand" "r,I16C16,n,m,rZ"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (arith_reg_operand (operands[0], HImode) && (arith_reg_operand (operands[0], HImode)
|| arith_reg_or_0_operand (operands[1], HImode))" || arith_reg_or_0_operand (operands[1], HImode))"
...@@ -3714,7 +3722,7 @@ ...@@ -3714,7 +3722,7 @@
[(set (match_operand:HI 0 "register_operand" "") [(set (match_operand:HI 0 "register_operand" "")
(match_operand:HI 1 "immediate_operand" ""))] (match_operand:HI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed "TARGET_SHMEDIA && reload_completed
&& ! CONST_OK_FOR_J (INTVAL (operands[1]))" && ! CONST_OK_FOR_I16 (INTVAL (operands[1]))"
[(set (subreg:DI (match_dup 0) 0) (match_dup 1))]) [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
(define_expand "movhi" (define_expand "movhi"
...@@ -3743,7 +3751,7 @@ ...@@ -3743,7 +3751,7 @@
;; compiled with -m2 -ml -O3 -funroll-loops ;; compiled with -m2 -ml -O3 -funroll-loops
(define_insn "*movdi_i" (define_insn "*movdi_i"
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x") [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
(match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))] (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
"TARGET_SH1 "TARGET_SH1
&& (arith_reg_operand (operands[0], DImode) && (arith_reg_operand (operands[0], DImode)
|| arith_reg_operand (operands[1], DImode))" || arith_reg_operand (operands[1], DImode))"
...@@ -3801,8 +3809,10 @@ ...@@ -3801,8 +3809,10 @@
}") }")
(define_insn "*movdi_media" (define_insn "*movdi_media"
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,f,m,f,r,f,*b,r,b") [(set (match_operand:DI 0 "general_movdst_operand"
(match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rlU,m,f,rU,f,f,r,*b,T"))] "=r,r,r,rl,m,f,m,f,r,f,*b,r,b")
(match_operand:DI 1 "general_movsrc_operand"
"r,I16C16,nCpgF,m,rlZ,m,f,rZ,f,f,r,*b,Csy"))]
"TARGET_SHMEDIA_FPU "TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], DImode) && (register_operand (operands[0], DImode)
|| sh_register_operand (operands[1], DImode))" || sh_register_operand (operands[1], DImode))"
...@@ -3825,7 +3835,7 @@ ...@@ -3825,7 +3835,7 @@
(define_insn "*movdi_media_nofpu" (define_insn "*movdi_media_nofpu"
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,b") [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,b")
(match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rlU,r,*b,T"))] (match_operand:DI 1 "general_movsrc_operand" "r,I16C16,nCpgF,m,rlZ,r,*b,Csy"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (register_operand (operands[0], DImode) && (register_operand (operands[0], DImode)
|| sh_register_operand (operands[1], DImode))" || sh_register_operand (operands[1], DImode))"
...@@ -3940,7 +3950,7 @@ ...@@ -3940,7 +3950,7 @@
(match_operand:DI 1 "immediate_operand" ""))] (match_operand:DI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed "TARGET_SHMEDIA && reload_completed
&& GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[1]) == CONST_INT
&& ! CONST_OK_FOR_J (INTVAL (operands[1]))" && ! CONST_OK_FOR_I16 (INTVAL (operands[1]))"
[(set (match_dup 0) (match_dup 2)) [(set (match_dup 0) (match_dup 2))
(match_dup 1)] (match_dup 1)]
" "
...@@ -3966,7 +3976,7 @@ ...@@ -3966,7 +3976,7 @@
{ {
/* If we can't generate the constant with a two-insn movi / shori /* If we can't generate the constant with a two-insn movi / shori
sequence, try some other strategies. */ sequence, try some other strategies. */
if (! CONST_OK_FOR_J (high)) if (! CONST_OK_FOR_I16 (high))
{ {
/* Try constant load / left shift. We know VAL != 0. */ /* Try constant load / left shift. We know VAL != 0. */
val2 = val ^ (val-1); val2 = val ^ (val-1);
...@@ -3974,9 +3984,9 @@ ...@@ -3974,9 +3984,9 @@
{ {
int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15; int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
if (CONST_OK_FOR_J (val >> trailing_zeroes) if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
|| (! CONST_OK_FOR_J (high >> 16) || (! CONST_OK_FOR_I16 (high >> 16)
&& CONST_OK_FOR_J (val >> (trailing_zeroes + 16)))) && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
{ {
val2 = (HOST_WIDE_INT) val >> trailing_zeroes; val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
operands[1] = gen_ashldi3_media (operands[0], operands[0], operands[1] = gen_ashldi3_media (operands[0], operands[0],
...@@ -3991,7 +4001,7 @@ ...@@ -3991,7 +4001,7 @@
int shift = 49 - exact_log2 (val2); int shift = 49 - exact_log2 (val2);
val2 = trunc_int_for_mode (val << shift, DImode); val2 = trunc_int_for_mode (val << shift, DImode);
if (CONST_OK_FOR_J (val2)) if (CONST_OK_FOR_I16 (val2))
{ {
operands[1] = gen_lshrdi3_media (operands[0], operands[0], operands[1] = gen_lshrdi3_media (operands[0], operands[0],
GEN_INT (shift)); GEN_INT (shift));
...@@ -4019,7 +4029,7 @@ ...@@ -4019,7 +4029,7 @@
} }
/* Try movi / mshflo.l w/ r63. */ /* Try movi / mshflo.l w/ r63. */
val2 = val + ((HOST_WIDE_INT) -1 << 32); val2 = val + ((HOST_WIDE_INT) -1 << 32);
if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_J (val2)) if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
{ {
operands[1] = gen_mshflo_l_di (operands[0], operands[0], operands[1] = gen_mshflo_l_di (operands[0], operands[0],
GEN_INT (0)); GEN_INT (0));
...@@ -4079,7 +4089,7 @@ ...@@ -4079,7 +4089,7 @@
(const_int 16)) (const_int 16))
(zero_extend:DI (zero_extend:DI
(truncate:HI (truncate:HI
(match_operand:DI 2 "immediate_operand" "JS,nF")))))] (match_operand:DI 2 "immediate_operand" "I16C16,nF")))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"@ "@
shori %u2, %0 shori %u2, %0
...@@ -4094,7 +4104,7 @@ ...@@ -4094,7 +4104,7 @@
(define_insn "movdf_media" (define_insn "movdf_media"
[(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m") [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
(match_operand:DF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,rU"))] (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
"TARGET_SHMEDIA_FPU "TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], DFmode) && (register_operand (operands[0], DFmode)
|| sh_register_operand (operands[1], DFmode))" || sh_register_operand (operands[1], DFmode))"
...@@ -4112,7 +4122,7 @@ ...@@ -4112,7 +4122,7 @@
(define_insn "movdf_media_nofpu" (define_insn "movdf_media_nofpu"
[(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m") [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
(match_operand:DF 1 "general_movsrc_operand" "r,F,m,rU"))] (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (register_operand (operands[0], DFmode) && (register_operand (operands[0], DFmode)
|| sh_register_operand (operands[1], DFmode))" || sh_register_operand (operands[1], DFmode))"
...@@ -4637,7 +4647,7 @@ ...@@ -4637,7 +4647,7 @@
(define_insn_and_split "movv2sf_i" (define_insn_and_split "movv2sf_i"
[(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf") [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
(match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfU?"))] (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
"TARGET_SHMEDIA_FPU" "TARGET_SHMEDIA_FPU"
"#" "#"
"TARGET_SHMEDIA_FPU && reload_completed" "TARGET_SHMEDIA_FPU && reload_completed"
...@@ -4704,7 +4714,7 @@ ...@@ -4704,7 +4714,7 @@
(define_insn_and_split "*movv4sf_i" (define_insn_and_split "*movv4sf_i"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=f,f,m") [(set (match_operand:V4SF 0 "nonimmediate_operand" "=f,f,m")
(match_operand:V4SF 1 "general_operand" "fU,m,fU"))] (match_operand:V4SF 1 "general_operand" "fZ,m,fZ"))]
"TARGET_SHMEDIA_FPU" "TARGET_SHMEDIA_FPU"
"#" "#"
"&& reload_completed" "&& reload_completed"
...@@ -4802,7 +4812,7 @@ ...@@ -4802,7 +4812,7 @@
(define_insn "movsf_media" (define_insn "movsf_media"
[(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m") [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
(match_operand:SF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,rU"))] (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
"TARGET_SHMEDIA_FPU "TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], SFmode) && (register_operand (operands[0], SFmode)
|| sh_register_operand (operands[1], SFmode))" || sh_register_operand (operands[1], SFmode))"
...@@ -4820,7 +4830,7 @@ ...@@ -4820,7 +4830,7 @@
(define_insn "movsf_media_nofpu" (define_insn "movsf_media_nofpu"
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m") [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
(match_operand:SF 1 "general_movsrc_operand" "r,F,m,rU"))] (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (register_operand (operands[0], SFmode) && (register_operand (operands[0], SFmode)
|| sh_register_operand (operands[1], SFmode))" || sh_register_operand (operands[1], SFmode))"
...@@ -4851,7 +4861,7 @@ ...@@ -4851,7 +4861,7 @@
(define_insn "movsf_i" (define_insn "movsf_i"
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r") [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
(match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))] (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
"TARGET_SH1 "TARGET_SH1
&& (! TARGET_SH2E && (! TARGET_SH2E
/* ??? We provide some insn so that direct_{load,store}[SFmode] get set */ /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
...@@ -4861,7 +4871,7 @@ ...@@ -4861,7 +4871,7 @@
|| arith_reg_operand (operands[1], SFmode))" || arith_reg_operand (operands[1], SFmode))"
"@ "@
mov %1,%0 mov %1,%0
mov %1,%0 mov #0,%0
mov.l %1,%0 mov.l %1,%0
mov.l %1,%0 mov.l %1,%0
mov.l %1,%0 mov.l %1,%0
...@@ -4878,7 +4888,7 @@ ...@@ -4878,7 +4888,7 @@
(match_operand:SF 1 "general_movsrc_operand" (match_operand:SF 1 "general_movsrc_operand"
"f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y")) "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
(use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")) (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
(clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))] (clobber (match_scratch:SI 3 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
"TARGET_SH2E "TARGET_SH2E
&& (arith_reg_operand (operands[0], SFmode) && (arith_reg_operand (operands[0], SFmode)
...@@ -4978,7 +4988,7 @@ ...@@ -4978,7 +4988,7 @@
(define_insn "*movsi_y" (define_insn "*movsi_y"
[(set (match_operand:SI 0 "register_operand" "=y,y") [(set (match_operand:SI 0 "register_operand" "=y,y")
(match_operand:SI 1 "immediate_operand" "Qi,I")) (match_operand:SI 1 "immediate_operand" "Qi,I08"))
(clobber (match_scratch:SI 2 "=&z,r"))] (clobber (match_scratch:SI 2 "=&z,r"))]
"TARGET_SH2E "TARGET_SH2E
&& (reload_in_progress || reload_completed)" && (reload_in_progress || reload_completed)"
...@@ -5064,7 +5074,7 @@ ...@@ -5064,7 +5074,7 @@
(define_expand "beq_media" (define_expand "beq_media"
[(set (pc) [(set (pc)
(if_then_else (eq (match_operand:DI 1 "arith_reg_operand" "r,r") (if_then_else (eq (match_operand:DI 1 "arith_reg_operand" "r,r")
(match_operand:DI 2 "arith_operand" "r,O")) (match_operand:DI 2 "arith_operand" "r,I06"))
(label_ref:DI (match_operand 0 "" "")) (label_ref:DI (match_operand 0 "" ""))
(pc)))] (pc)))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
...@@ -5074,7 +5084,7 @@ ...@@ -5074,7 +5084,7 @@
[(set (pc) [(set (pc)
(if_then_else (match_operator 3 "equality_comparison_operator" (if_then_else (match_operator 3 "equality_comparison_operator"
[(match_operand:DI 1 "arith_reg_operand" "r,r") [(match_operand:DI 1 "arith_reg_operand" "r,r")
(match_operand:DI 2 "arith_operand" "r,O")]) (match_operand:DI 2 "arith_operand" "r,I06")])
(match_operand:DI 0 "target_operand" "b,b") (match_operand:DI 0 "target_operand" "b,b")
(pc)))] (pc)))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
...@@ -5086,7 +5096,7 @@ ...@@ -5086,7 +5096,7 @@
(define_expand "bne_media" (define_expand "bne_media"
[(set (pc) [(set (pc)
(if_then_else (ne (match_operand:DI 1 "arith_reg_operand" "r,r") (if_then_else (ne (match_operand:DI 1 "arith_reg_operand" "r,r")
(match_operand:DI 2 "arith_operand" "r,O")) (match_operand:DI 2 "arith_operand" "r,I06"))
(label_ref:DI (match_operand 0 "" "")) (label_ref:DI (match_operand 0 "" ""))
(pc)))] (pc)))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
...@@ -6633,19 +6643,19 @@ ...@@ -6633,19 +6643,19 @@
;; non-branch-target registers. ;; non-branch-target registers.
(define_insn "*pt" (define_insn "*pt"
[(set (match_operand:DI 0 "target_reg_operand" "=b") [(set (match_operand:DI 0 "target_reg_operand" "=b")
(match_operand:DI 1 "" "T"))] (match_operand:DI 1 "" "Csy"))]
"TARGET_SHMEDIA && flag_pic "TARGET_SHMEDIA && flag_pic
&& EXTRA_CONSTRAINT_T (operands[1])" && EXTRA_CONSTRAINT_Csy (operands[1])"
"pt %1, %0" "pt %1, %0"
[(set_attr "type" "pt_media") [(set_attr "type" "pt_media")
(set_attr "length" "*")]) (set_attr "length" "*")])
(define_insn "*ptb" (define_insn "*ptb"
[(set (match_operand:DI 0 "target_reg_operand" "=b") [(set (match_operand:DI 0 "target_reg_operand" "=b")
(const:DI (unspec:DI [(match_operand:DI 1 "" "T")] (const:DI (unspec:DI [(match_operand:DI 1 "" "Csy")]
UNSPEC_DATALABEL)))] UNSPEC_DATALABEL)))]
"TARGET_SHMEDIA && flag_pic "TARGET_SHMEDIA && flag_pic
&& EXTRA_CONSTRAINT_T (operands[1])" && EXTRA_CONSTRAINT_Csy (operands[1])"
"ptb/u datalabel %1, %0" "ptb/u datalabel %1, %0"
[(set_attr "type" "pt_media") [(set_attr "type" "pt_media")
(set_attr "length" "*")]) (set_attr "length" "*")])
...@@ -9354,7 +9364,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -9354,7 +9364,7 @@ mov.l\\t1f,r0\\n\\
(define_insn "movv8qi_i" (define_insn "movv8qi_i"
[(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m") [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
(match_operand:V8QI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))] (match_operand:V8QI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (register_operand (operands[0], V8QImode) && (register_operand (operands[0], V8QImode)
|| sh_register_operand (operands[1], V8QImode))" || sh_register_operand (operands[1], V8QImode))"
...@@ -9446,7 +9456,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -9446,7 +9456,7 @@ mov.l\\t1f,r0\\n\\
(define_insn "movv2hi_i" (define_insn "movv2hi_i"
[(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m") [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
(match_operand:V2HI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))] (match_operand:V2HI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (register_operand (operands[0], V2HImode) && (register_operand (operands[0], V2HImode)
|| sh_register_operand (operands[1], V2HImode))" || sh_register_operand (operands[1], V2HImode))"
...@@ -9467,7 +9477,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -9467,7 +9477,7 @@ mov.l\\t1f,r0\\n\\
(define_insn "movv4hi_i" (define_insn "movv4hi_i"
[(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m") [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
(match_operand:V4HI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))] (match_operand:V4HI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (register_operand (operands[0], V4HImode) && (register_operand (operands[0], V4HImode)
|| sh_register_operand (operands[1], V4HImode))" || sh_register_operand (operands[1], V4HImode))"
...@@ -9488,7 +9498,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -9488,7 +9498,7 @@ mov.l\\t1f,r0\\n\\
(define_insn "movv2si_i" (define_insn "movv2si_i"
[(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m") [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
(match_operand:V2SI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))] (match_operand:V2SI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (register_operand (operands[0], V2SImode) && (register_operand (operands[0], V2SImode)
|| sh_register_operand (operands[1], V2SImode))" || sh_register_operand (operands[1], V2SImode))"
...@@ -9559,55 +9569,55 @@ mov.l\\t1f,r0\\n\\ ...@@ -9559,55 +9569,55 @@ mov.l\\t1f,r0\\n\\
(define_insn "negcmpeqv8qi" (define_insn "negcmpeqv8qi"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r") [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(neg:V8QI (eq:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rU") (neg:V8QI (eq:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))))] (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpeq.b %N1, %N2, %0" "mcmpeq.b %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
(define_insn "negcmpeqv2si" (define_insn "negcmpeqv2si"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r") [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(neg:V2SI (eq:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rU") (neg:V2SI (eq:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))))] (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpeq.l %N1, %N2, %0" "mcmpeq.l %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
(define_insn "negcmpeqv4hi" (define_insn "negcmpeqv4hi"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(neg:V4HI (eq:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rU") (neg:V4HI (eq:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))] (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpeq.w %N1, %N2, %0" "mcmpeq.w %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
(define_insn "negcmpgtuv8qi" (define_insn "negcmpgtuv8qi"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r") [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(neg:V8QI (gtu:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rU") (neg:V8QI (gtu:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))))] (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpgt.ub %N1, %N2, %0" "mcmpgt.ub %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
(define_insn "negcmpgtv2si" (define_insn "negcmpgtv2si"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r") [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(neg:V2SI (gt:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rU") (neg:V2SI (gt:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))))] (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpgt.l %N1, %N2, %0" "mcmpgt.l %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
(define_insn "negcmpgtv4hi" (define_insn "negcmpgtv4hi"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(neg:V4HI (gt:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rU") (neg:V4HI (gt:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))] (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcmpgt.w %N1, %N2, %0" "mcmpgt.w %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
(define_insn "mcmv" (define_insn "mcmv"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU") (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:DI 2 "arith_reg_operand" "r")) (match_operand:DI 2 "arith_reg_operand" "r"))
(and:DI (match_operand:DI 3 "arith_reg_operand" "0") (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
(not:DI (match_dup 2)))))] (not:DI (match_dup 2)))))]
...@@ -9618,8 +9628,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -9618,8 +9628,8 @@ mov.l\\t1f,r0\\n\\
(define_insn "mcnvs_lw" (define_insn "mcnvs_lw"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_concat:V4HI (vec_concat:V4HI
(ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")) (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
(ss_truncate:V2HI (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))))] (ss_truncate:V2HI (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcnvs.lw %N1, %N2, %0" "mcnvs.lw %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
...@@ -9627,8 +9637,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -9627,8 +9637,8 @@ mov.l\\t1f,r0\\n\\
(define_insn "mcnvs_wb" (define_insn "mcnvs_wb"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r") [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_concat:V8QI (vec_concat:V8QI
(ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")) (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
(ss_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))] (ss_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcnvs.wb %N1, %N2, %0" "mcnvs.wb %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
...@@ -9636,17 +9646,17 @@ mov.l\\t1f,r0\\n\\ ...@@ -9636,17 +9646,17 @@ mov.l\\t1f,r0\\n\\
(define_insn "mcnvs_wub" (define_insn "mcnvs_wub"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r") [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_concat:V8QI (vec_concat:V8QI
(us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")) (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
(us_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))] (us_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mcnvs.wub %N1, %N2, %0" "mcnvs.wub %N1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
(define_insn "mextr_rl" (define_insn "mextr_rl"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU") (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 3 "mextr_bit_offset" "i")) (match_operand:HI 3 "mextr_bit_offset" "i"))
(ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU") (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 4 "mextr_bit_offset" "i"))))] (match_operand:HI 4 "mextr_bit_offset" "i"))))]
"TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64" "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
"* "*
...@@ -9661,9 +9671,9 @@ mov.l\\t1f,r0\\n\\ ...@@ -9661,9 +9671,9 @@ mov.l\\t1f,r0\\n\\
(define_insn "*mextr_lr" (define_insn "*mextr_lr"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU") (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 3 "mextr_bit_offset" "i")) (match_operand:HI 3 "mextr_bit_offset" "i"))
(lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU") (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 4 "mextr_bit_offset" "i"))))] (match_operand:HI 4 "mextr_bit_offset" "i"))))]
"TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64" "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
"* "*
...@@ -9680,8 +9690,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -9680,8 +9690,8 @@ mov.l\\t1f,r0\\n\\
; vector then varies depending on endianness. ; vector then varies depending on endianness.
(define_expand "mextr1" (define_expand "mextr1"
[(match_operand:DI 0 "arith_reg_dest" "") [(match_operand:DI 0 "arith_reg_dest" "")
(match_operand:DI 1 "arith_reg_or_0_operand" "rU") (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:DI 2 "arith_reg_or_0_operand" "rU")] (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -9692,8 +9702,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -9692,8 +9702,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mextr2" (define_expand "mextr2"
[(match_operand:DI 0 "arith_reg_dest" "") [(match_operand:DI 0 "arith_reg_dest" "")
(match_operand:DI 1 "arith_reg_or_0_operand" "rU") (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:DI 2 "arith_reg_or_0_operand" "rU")] (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -9704,8 +9714,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -9704,8 +9714,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mextr3" (define_expand "mextr3"
[(match_operand:DI 0 "arith_reg_dest" "") [(match_operand:DI 0 "arith_reg_dest" "")
(match_operand:DI 1 "arith_reg_or_0_operand" "rU") (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:DI 2 "arith_reg_or_0_operand" "rU")] (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -9716,8 +9726,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -9716,8 +9726,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mextr4" (define_expand "mextr4"
[(match_operand:DI 0 "arith_reg_dest" "") [(match_operand:DI 0 "arith_reg_dest" "")
(match_operand:DI 1 "arith_reg_or_0_operand" "rU") (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:DI 2 "arith_reg_or_0_operand" "rU")] (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -9728,8 +9738,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -9728,8 +9738,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mextr5" (define_expand "mextr5"
[(match_operand:DI 0 "arith_reg_dest" "") [(match_operand:DI 0 "arith_reg_dest" "")
(match_operand:DI 1 "arith_reg_or_0_operand" "rU") (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:DI 2 "arith_reg_or_0_operand" "rU")] (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -9740,8 +9750,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -9740,8 +9750,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mextr6" (define_expand "mextr6"
[(match_operand:DI 0 "arith_reg_dest" "") [(match_operand:DI 0 "arith_reg_dest" "")
(match_operand:DI 1 "arith_reg_or_0_operand" "rU") (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:DI 2 "arith_reg_or_0_operand" "rU")] (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -9752,8 +9762,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -9752,8 +9762,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mextr7" (define_expand "mextr7"
[(match_operand:DI 0 "arith_reg_dest" "") [(match_operand:DI 0 "arith_reg_dest" "")
(match_operand:DI 1 "arith_reg_or_0_operand" "rU") (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:DI 2 "arith_reg_or_0_operand" "rU")] (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -9962,7 +9972,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -9962,7 +9972,7 @@ mov.l\\t1f,r0\\n\\
(define_expand "mperm_w" (define_expand "mperm_w"
[(match_operand:V4HI 0 "arith_reg_dest" "=r") [(match_operand:V4HI 0 "arith_reg_dest" "=r")
(match_operand:V4HI 1 "arith_reg_operand" "r") (match_operand:V4HI 1 "arith_reg_operand" "r")
(match_operand:QI 2 "extend_reg_or_0_operand" "rU")] (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -9978,7 +9988,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -9978,7 +9988,7 @@ mov.l\\t1f,r0\\n\\
(vec_select:V4HI (vec_select:V4HI
(match_operand:V4HI 1 "arith_reg_operand" "r") (match_operand:V4HI 1 "arith_reg_operand" "r")
(parallel (parallel
[(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rU") [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
(const_int 2) (const_int 0)) (const_int 2) (const_int 0))
(zero_extract:QI (match_dup 2) (const_int 2) (const_int 2)) (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
(zero_extract:QI (match_dup 2) (const_int 2) (const_int 4)) (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
...@@ -9993,7 +10003,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -9993,7 +10003,7 @@ mov.l\\t1f,r0\\n\\
(match_operand:V4HI 1 "arith_reg_operand" "r") (match_operand:V4HI 1 "arith_reg_operand" "r")
(parallel (parallel
[(zero_extract:QI (not:QI (match_operand:QI 2 [(zero_extract:QI (not:QI (match_operand:QI 2
"extend_reg_or_0_operand" "rU")) "extend_reg_or_0_operand" "rZ"))
(const_int 2) (const_int 0)) (const_int 2) (const_int 0))
(zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2)) (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
(zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4)) (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
...@@ -10034,9 +10044,9 @@ mov.l\\t1f,r0\\n\\ ...@@ -10034,9 +10044,9 @@ mov.l\\t1f,r0\\n\\
(abs:DI (vec_select:DI (abs:DI (vec_select:DI
(minus:V8DI (minus:V8DI
(zero_extend:V8DI (zero_extend:V8DI
(match_operand:V8QI 2 "arith_reg_or_0_operand" "r")) (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
(zero_extend:V8DI (zero_extend:V8DI
(match_operand:V8QI 3 "arith_reg_or_0_operand" "r"))) (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
(parallel [(const_int 0)])))) (parallel [(const_int 0)]))))
(abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2)) (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
(zero_extend:V8DI (match_dup 3))) (zero_extend:V8DI (match_dup 3)))
...@@ -10109,15 +10119,15 @@ mov.l\\t1f,r0\\n\\ ...@@ -10109,15 +10119,15 @@ mov.l\\t1f,r0\\n\\
[(set (match_operand:HI 0 "arith_reg_dest" "=r") [(set (match_operand:HI 0 "arith_reg_dest" "=r")
(ss_truncate:HI (ss_truncate:HI
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r") (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "arith_reg_or_0_operand" "rU"))))] (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mshards.q %1, %N2, %0" "mshards.q %1, %N2, %0"
[(set_attr "type" "mcmp_media")]) [(set_attr "type" "mcmp_media")])
(define_expand "mshfhi_b" (define_expand "mshfhi_b"
[(match_operand:V8QI 0 "arith_reg_dest" "") [(match_operand:V8QI 0 "arith_reg_dest" "")
(match_operand:V8QI 1 "arith_reg_or_0_operand" "rU") (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rU")] (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -10128,8 +10138,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10128,8 +10138,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mshflo_b" (define_expand "mshflo_b"
[(match_operand:V8QI 0 "arith_reg_dest" "") [(match_operand:V8QI 0 "arith_reg_dest" "")
(match_operand:V8QI 1 "arith_reg_or_0_operand" "rU") (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rU")] (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -10142,8 +10152,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10142,8 +10152,8 @@ mov.l\\t1f,r0\\n\\
[(set [(set
(match_operand:V8QI 0 "arith_reg_dest" "=r") (match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_select:V8QI (vec_select:V8QI
(vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU") (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rU")) (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13) (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
(const_int 6) (const_int 14) (const_int 7) (const_int 15)])))] (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
...@@ -10156,8 +10166,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10156,8 +10166,8 @@ mov.l\\t1f,r0\\n\\
[(set [(set
(match_operand:V8QI 0 "arith_reg_dest" "=r") (match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_select:V8QI (vec_select:V8QI
(vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU") (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V8QI 2 "arith_reg_or_0_operand" "rU")) (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9) (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
(const_int 2) (const_int 10) (const_int 3) (const_int 11)])))] (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
...@@ -10168,8 +10178,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10168,8 +10178,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mshfhi_l" (define_expand "mshfhi_l"
[(match_operand:V2SI 0 "arith_reg_dest" "") [(match_operand:V2SI 0 "arith_reg_dest" "")
(match_operand:V2SI 1 "arith_reg_or_0_operand" "rU") (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rU")] (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -10180,8 +10190,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10180,8 +10190,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mshflo_l" (define_expand "mshflo_l"
[(match_operand:V2SI 0 "arith_reg_dest" "") [(match_operand:V2SI 0 "arith_reg_dest" "")
(match_operand:V2SI 1 "arith_reg_or_0_operand" "rU") (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rU")] (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -10193,8 +10203,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10193,8 +10203,8 @@ mov.l\\t1f,r0\\n\\
(define_insn "mshf4_l" (define_insn "mshf4_l"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r") [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(vec_select:V2SI (vec_select:V2SI
(vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU") (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rU")) (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 1) (const_int 3)])))] (parallel [(const_int 1) (const_int 3)])))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"* return (TARGET_LITTLE_ENDIAN "* return (TARGET_LITTLE_ENDIAN
...@@ -10205,8 +10215,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10205,8 +10215,8 @@ mov.l\\t1f,r0\\n\\
(define_insn "mshf0_l" (define_insn "mshf0_l"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r") [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(vec_select:V2SI (vec_select:V2SI
(vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU") (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V2SI 2 "arith_reg_or_0_operand" "rU")) (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 0) (const_int 2)])))] (parallel [(const_int 0) (const_int 2)])))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"* return (TARGET_LITTLE_ENDIAN "* return (TARGET_LITTLE_ENDIAN
...@@ -10216,8 +10226,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10216,8 +10226,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mshfhi_w" (define_expand "mshfhi_w"
[(match_operand:V4HI 0 "arith_reg_dest" "") [(match_operand:V4HI 0 "arith_reg_dest" "")
(match_operand:V4HI 1 "arith_reg_or_0_operand" "rU") (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rU")] (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -10228,8 +10238,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10228,8 +10238,8 @@ mov.l\\t1f,r0\\n\\
(define_expand "mshflo_w" (define_expand "mshflo_w"
[(match_operand:V4HI 0 "arith_reg_dest" "") [(match_operand:V4HI 0 "arith_reg_dest" "")
(match_operand:V4HI 1 "arith_reg_or_0_operand" "rU") (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rU")] (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
" "
{ {
...@@ -10241,8 +10251,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10241,8 +10251,8 @@ mov.l\\t1f,r0\\n\\
(define_insn "mshf4_w" (define_insn "mshf4_w"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_select:V4HI (vec_select:V4HI
(vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU") (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rU")) (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"* return (TARGET_LITTLE_ENDIAN "* return (TARGET_LITTLE_ENDIAN
...@@ -10253,8 +10263,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10253,8 +10263,8 @@ mov.l\\t1f,r0\\n\\
(define_insn "mshf0_w" (define_insn "mshf0_w"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_select:V4HI (vec_select:V4HI
(vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU") (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V4HI 2 "arith_reg_or_0_operand" "rU")) (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"* return (TARGET_LITTLE_ENDIAN "* return (TARGET_LITTLE_ENDIAN
...@@ -10265,8 +10275,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10265,8 +10275,8 @@ mov.l\\t1f,r0\\n\\
(define_insn "mshflo_w_x" (define_insn "mshflo_w_x"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_select:V4HI (vec_select:V4HI
(vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rU") (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
(match_operand:V2HI 2 "extend_reg_or_0_operand" "rU")) (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
(parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))] (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mshflo.w %N1, %N2, %0" "mshflo.w %N1, %N2, %0"
...@@ -10275,9 +10285,9 @@ mov.l\\t1f,r0\\n\\ ...@@ -10275,9 +10285,9 @@ mov.l\\t1f,r0\\n\\
/* These are useful to expand ANDs and as combiner patterns. */ /* These are useful to expand ANDs and as combiner patterns. */
(define_insn_and_split "mshfhi_l_di" (define_insn_and_split "mshfhi_l_di"
[(set (match_operand:DI 0 "arith_reg_dest" "=r,f") [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
(ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU,f") (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
(const_int 32)) (const_int 32))
(and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU,?f") (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
(const_int -4294967296))))] (const_int -4294967296))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"@ "@
...@@ -10298,9 +10308,9 @@ mov.l\\t1f,r0\\n\\ ...@@ -10298,9 +10308,9 @@ mov.l\\t1f,r0\\n\\
(define_insn "*mshfhi_l_di_rev" (define_insn "*mshfhi_l_di_rev"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU") (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int -4294967296)) (const_int -4294967296))
(lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU") (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 32))))] (const_int 32))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mshfhi.l %N2, %N1, %0" "mshfhi.l %N2, %N1, %0"
...@@ -10327,9 +10337,9 @@ mov.l\\t1f,r0\\n\\ ...@@ -10327,9 +10337,9 @@ mov.l\\t1f,r0\\n\\
(define_insn "mshflo_l_di" (define_insn "mshflo_l_di"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU") (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int 4294967295)) (const_int 4294967295))
(ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU") (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 32))))] (const_int 32))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
...@@ -10338,9 +10348,9 @@ mov.l\\t1f,r0\\n\\ ...@@ -10338,9 +10348,9 @@ mov.l\\t1f,r0\\n\\
(define_insn "*mshflo_l_di_rev" (define_insn "*mshflo_l_di_rev"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU") (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int 32)) (const_int 32))
(and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU") (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 4294967295))))] (const_int 4294967295))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
...@@ -10373,8 +10383,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -10373,8 +10383,8 @@ mov.l\\t1f,r0\\n\\
(define_insn "*mshflo_l_di_x" (define_insn "*mshflo_l_di_x"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand" (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
"rU")) "rZ"))
(ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU") (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 32))))] (const_int 32))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
...@@ -10383,9 +10393,9 @@ mov.l\\t1f,r0\\n\\ ...@@ -10383,9 +10393,9 @@ mov.l\\t1f,r0\\n\\
(define_insn_and_split "concat_v2sf" (define_insn_and_split "concat_v2sf"
[(set (match_operand:V2SF 0 "register_operand" "=r,f,f?") [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rU,0,f") ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
(vec_concat:V2SF (match_operand:SF 1 "register_operand" "rU,f,f") (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
(match_operand:SF 2 "register_operand" "rU,f,f")))] (match_operand:SF 2 "register_operand" "rZ,f,f")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"@ "@
...@@ -10405,9 +10415,9 @@ mov.l\\t1f,r0\\n\\ ...@@ -10405,9 +10415,9 @@ mov.l\\t1f,r0\\n\\
(define_insn "*mshflo_l_di_x_rev" (define_insn "*mshflo_l_di_x_rev"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU") (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int 32)) (const_int 32))
(zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rU"))))] (zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"mshflo.l %N2, %N1, %0" "mshflo.l %N2, %N1, %0"
...@@ -10447,7 +10457,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -10447,7 +10457,7 @@ mov.l\\t1f,r0\\n\\
(define_insn "subv2si3" (define_insn "subv2si3"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r") [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU") (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V2SI 2 "arith_reg_operand" "r")))] (match_operand:V2SI 2 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"msub.l %N1, %2, %0" "msub.l %N1, %2, %0"
...@@ -10455,7 +10465,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -10455,7 +10465,7 @@ mov.l\\t1f,r0\\n\\
(define_insn "subv4hi3" (define_insn "subv4hi3"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU") (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V4HI 2 "arith_reg_operand" "r")))] (match_operand:V4HI 2 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"msub.w %N1, %2, %0" "msub.w %N1, %2, %0"
...@@ -10463,7 +10473,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -10463,7 +10473,7 @@ mov.l\\t1f,r0\\n\\
(define_insn "sssubv2si3" (define_insn "sssubv2si3"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r") [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU") (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V2SI 2 "arith_reg_operand" "r")))] (match_operand:V2SI 2 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"msubs.l %N1, %2, %0" "msubs.l %N1, %2, %0"
...@@ -10479,7 +10489,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -10479,7 +10489,7 @@ mov.l\\t1f,r0\\n\\
(define_insn "sssubv4hi3" (define_insn "sssubv4hi3"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r") [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU") (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V4HI 2 "arith_reg_operand" "r")))] (match_operand:V4HI 2 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"msubs.w %N1, %2, %0" "msubs.w %N1, %2, %0"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment