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riscv-gcc-1
Commit 71d8eff1 by Chung-Ju Wu Committed by Chung-Ju Wu
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[NDS32] Reserve more register numbers for new registers in the future. 

gcc/
	* config/nds32/nds32.h (FIRST_PSEUDO_REGISTER): Modify.
	(FIXED_REGISTERS): Reserve more register numbers.
	(CALL_USED_REGISTERS): Likewise.
	(REG_ALLOC_ORDER): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	(REGISTER_NAMES): Likewise.

Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com>

From-SVN: r254854
parent 3d7f09de
Showing with 93 additions and 32 deletions
gcc/ChangeLog
2017-11-17 Chung-Ju Wu <jasonwucj@gmail.com> 2017-11-17 Chung-Ju Wu <jasonwucj@gmail.com>
Monk Chiang <sh.chiang04@gmail.com>
* config/nds32/nds32.h (FIRST_PSEUDO_REGISTER): Modify.
(FIXED_REGISTERS): Reserve more register numbers.
(CALL_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(REGISTER_NAMES): Likewise.
2017-11-17 Chung-Ju Wu <jasonwucj@gmail.com>
Kito Cheng <kito.cheng@gmail.com> Kito Cheng <kito.cheng@gmail.com>
* config/nds32/nds32-modes.def: Add vector mode V4QI V2HI V8QI V4HI * config/nds32/nds32-modes.def: Add vector mode V4QI V2HI V8QI V4HI
gcc/config/nds32/nds32.h
...@@ -530,7 +530,7 @@ enum nds32_builtins ...@@ -530,7 +530,7 @@ enum nds32_builtins
from 0 to just below FIRST_PSEUDO_REGISTER. from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers, All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers. */ even those that are not normally considered general registers. */
#define FIRST_PSEUDO_REGISTER 34 #define FIRST_PSEUDO_REGISTER 101
/* An initializer that says which registers are used for fixed /* An initializer that says which registers are used for fixed
purposes all throughout the compiled code and are therefore purposes all throughout the compiled code and are therefore
...@@ -555,10 +555,24 @@ enum nds32_builtins ...@@ -555,10 +555,24 @@ enum nds32_builtins
0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \
/* r24 r25 r26 r27 r28 r29 r30 r31 */ \ /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
1, 1, 1, 1, 0, 1, 0, 1, \ 1, 1, 1, 1, 0, 1, 0, 1, \
/* ARG_POINTER:32 */ \ /* AP FP Reserved.................... */ \
1, \ 1, 1, 1, 1, 1, 1, 1, 1, \
/* FRAME_POINTER:33 */ \ /* Reserved............................... */ \
1 \ 1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1 \
} }
/* Identifies the registers that are not available for /* Identifies the registers that are not available for
...@@ -576,10 +590,24 @@ enum nds32_builtins ...@@ -576,10 +590,24 @@ enum nds32_builtins
1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \
/* r24 r25 r26 r27 r28 r29 r30 r31 */ \ /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
1, 1, 1, 1, 0, 1, 0, 1, \ 1, 1, 1, 1, 0, 1, 0, 1, \
/* ARG_POINTER:32 */ \ /* AP FP Reserved.................... */ \
1, \ 1, 1, 1, 1, 1, 1, 1, 1, \
/* FRAME_POINTER:33 */ \ /* Reserved............................... */ \
1 \ 1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* Reserved............................... */ \
1, 1, 1, 1, 1 \
} }
/* In nds32 target, we have three levels of registers: /* In nds32 target, we have three levels of registers:
...@@ -587,13 +615,19 @@ enum nds32_builtins ...@@ -587,13 +615,19 @@ enum nds32_builtins
MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19 MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */ HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
#define REG_ALLOC_ORDER \ #define REG_ALLOC_ORDER \
{ \ { 0, 1, 2, 3, 4, 5, 6, 7, \
0, 1, 2, 3, 4, 5, 6, 7, \ 16, 17, 18, 19, 9, 10, 11, 12, \
8, 9, 10, 11, 16, 17, 18, 19, \ 13, 14, 8, 15, 20, 21, 22, 23, \
12, 13, 14, 15, 20, 21, 22, 23, \
24, 25, 26, 27, 28, 29, 30, 31, \ 24, 25, 26, 27, 28, 29, 30, 31, \
32, \ 32, 33, 34, 35, 36, 37, 38, 39, \
33 \ 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, \
64, 65, 66, 67, 68, 69, 70, 71, \
72, 73, 74, 75, 76, 77, 78, 79, \
80, 81, 82, 83, 84, 85, 86, 87, \
88, 89, 90, 91, 92, 93, 94, 95, \
96, 97, 98, 99, 100, \
} }
/* Tell IRA to use the order we define rather than messing it up with its /* Tell IRA to use the order we define rather than messing it up with its
...@@ -646,19 +680,30 @@ enum reg_class ...@@ -646,19 +680,30 @@ enum reg_class
} }
#define REG_CLASS_CONTENTS \ #define REG_CLASS_CONTENTS \
{ \ { /* NO_REGS */ \
{0x00000000, 0x00000000}, /* NO_REGS */ \ {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
{0x00000020, 0x00000000}, /* R5_REG : 5 */ \ /* R5_REG : 5 */ \
{0x00000100, 0x00000000}, /* R8_REG : 8 */ \ {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
{0x00008000, 0x00000000}, /* R15_TA_REG : 15 */ \ /* R8_REG : 8 */ \
{0x80000000, 0x00000000}, /* STACK_REG : 31 */ \ {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
{0x10000000, 0x00000000}, /* FRAME_POINTER_REG : 28 */ \ /* R15_TA_REG : 15 */ \
{0x000000ff, 0x00000000}, /* LOW_REGS : 0-7 */ \ {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
{0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19 */ \ /* STACK_REG : 31 */ \
{0xfff07000, 0x00000000}, /* HIGH_REGS : 12-14, 20-31 */ \ {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
{0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31 */ \ /* FRAME_POINTER_REG : 28 */ \
{0x00000000, 0x00000003}, /* FRAME_REGS : 32, 33 */ \ {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
{0xffffffff, 0x00000003} /* ALL_REGS : 0-31, 32, 33 */ \ /* LOW_REGS : 0-7 */ \
{0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
/* MIDDLE_REGS : 0-11, 16-19 */ \
{0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
/* HIGH_REGS : 12-14, 20-31 */ \
{0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
/* GENERAL_REGS : 0-31 */ \
{0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
/* FRAME_REGS : 32, 33 */ \
{0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
/* ALL_REGS : 0-100 */ \
{0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f} \
} }
#define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno) #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
...@@ -870,13 +915,19 @@ enum reg_class ...@@ -870,13 +915,19 @@ enum reg_class
#define LOCAL_LABEL_PREFIX "." #define LOCAL_LABEL_PREFIX "."
#define REGISTER_NAMES \ #define REGISTER_NAMES \
{ \ { "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
"$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
"$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \ "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
"$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \ "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
"$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \ "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
"$AP", \ "$AP", "$SFP", "NA", "NA", "NA", "NA", "NA", "NA", \
"$SFP" \ "NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
"NA", "NA", "NA", "NA", "NA" \
} }
/* Output normal jump table entry. */ /* Output normal jump table entry. */
......
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