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riscv-gcc-1
Commit 7159e638 by Uros Bizjak Committed by Uros Bizjak
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alpha.md: Remove empty predicates and/or constraints. 

	* config/alpha/alpha.md: Remove empty predicates and/or constraints.
	* config/alpha/sync.md: Ditto.

From-SVN: r192431
parent 0c3da4c5
Showing with 632 additions and 661 deletions
gcc/ChangeLog
2012-10-14 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/alpha.md: Remove empty predicates and/or constraints.
* config/alpha/sync.md: Ditto.
2012-10-13 Uros Bizjak <ubizjak@gmail.com> 2012-10-13 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/alpha.md (I24MODE): New mode iterator. * config/alpha/alpha.md (I24MODE): New mode iterator.
gcc/config/alpha/alpha.md
...@@ -234,10 +234,8 @@ ...@@ -234,10 +234,8 @@
;; code for that case. But we don't reject the possibility. ;; code for that case. But we don't reject the possibility.
(define_expand "extendsidi2" (define_expand "extendsidi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))])
""
"")
(define_insn "*cvtlq" (define_insn "*cvtlq"
[(set (match_operand:DI 0 "register_operand" "=f") [(set (match_operand:DI 0 "register_operand" "=f")
...@@ -260,8 +258,8 @@ ...@@ -260,8 +258,8 @@
(set_attr "length" "*,*,8")]) (set_attr "length" "*,*,8")])
(define_split (define_split
[(set (match_operand:DI 0 "hard_fp_register_operand" "") [(set (match_operand:DI 0 "hard_fp_register_operand")
(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))] (sign_extend:DI (match_operand:SI 1 "memory_operand")))]
"reload_completed" "reload_completed"
[(set (match_dup 2) (match_dup 1)) [(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
...@@ -274,15 +272,14 @@ ...@@ -274,15 +272,14 @@
;; reload when converting fp->int. ;; reload when converting fp->int.
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "hard_int_register_operand" "") [(set (match_operand:SI 0 "hard_int_register_operand")
(match_operand:SI 1 "memory_operand" "")) (match_operand:SI 1 "memory_operand"))
(set (match_operand:DI 2 "hard_int_register_operand" "") (set (match_operand:DI 2 "hard_int_register_operand")
(sign_extend:DI (match_dup 0)))] (sign_extend:DI (match_dup 0)))]
"true_regnum (operands[0]) == true_regnum (operands[2]) "true_regnum (operands[0]) == true_regnum (operands[2])
|| peep2_reg_dead_p (2, operands[0])" || peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) [(set (match_dup 2)
(sign_extend:DI (match_dup 1)))] (sign_extend:DI (match_dup 1)))])
"")
(define_insn "addsi3" (define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
...@@ -296,9 +293,9 @@ ...@@ -296,9 +293,9 @@
ldah %0,%h2(%r1)") ldah %0,%h2(%r1)")
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand")
(plus:SI (match_operand:SI 1 "register_operand" "") (plus:SI (match_operand:SI 1 "register_operand")
(match_operand:SI 2 "const_int_operand" "")))] (match_operand:SI 2 "const_int_operand")))]
"! add_operand (operands[2], SImode)" "! add_operand (operands[2], SImode)"
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
...@@ -333,11 +330,11 @@ ...@@ -333,11 +330,11 @@
subl %r1,%n2,%0") subl %r1,%n2,%0")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI (sign_extend:DI
(plus:SI (match_operand:SI 1 "reg_not_elim_operand" "") (plus:SI (match_operand:SI 1 "reg_not_elim_operand")
(match_operand:SI 2 "const_int_operand" "")))) (match_operand:SI 2 "const_int_operand"))))
(clobber (match_operand:SI 3 "reg_not_elim_operand" ""))] (clobber (match_operand:SI 3 "reg_not_elim_operand"))]
"! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) % 4 == 0" && INTVAL (operands[2]) % 4 == 0"
[(set (match_dup 3) (match_dup 4)) [(set (match_dup 3) (match_dup 4))
...@@ -356,13 +353,13 @@ ...@@ -356,13 +353,13 @@
}) })
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI (sign_extend:DI
(plus:SI (match_operator:SI 1 "comparison_operator" (plus:SI (match_operator:SI 1 "comparison_operator"
[(match_operand 2 "" "") [(match_operand 2)
(match_operand 3 "" "")]) (match_operand 3)])
(match_operand:SI 4 "add_operand" "")))) (match_operand:SI 4 "add_operand"))))
(clobber (match_operand:DI 5 "register_operand" ""))] (clobber (match_operand:DI 5 "register_operand"))]
"" ""
[(set (match_dup 5) (match_dup 6)) [(set (match_dup 5) (match_dup 6))
(set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
...@@ -373,65 +370,63 @@ ...@@ -373,65 +370,63 @@
}) })
(define_expand "adddi3" (define_expand "adddi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(plus:DI (match_operand:DI 1 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "add_operand" "")))] (match_operand:DI 2 "add_operand")))])
""
"")
(define_insn "*adddi_er_lo16_dtp" (define_insn "*adddi_er_lo16_dtp"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "dtp16_symbolic_operand" "")))] (match_operand:DI 2 "dtp16_symbolic_operand")))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
"lda %0,%2(%1)\t\t!dtprel") "lda %0,%2(%1)\t\t!dtprel")
(define_insn "*adddi_er_hi32_dtp" (define_insn "*adddi_er_hi32_dtp"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "r") (plus:DI (match_operand:DI 1 "register_operand" "r")
(high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))] (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
"ldah %0,%2(%1)\t\t!dtprelhi") "ldah %0,%2(%1)\t\t!dtprelhi")
(define_insn "*adddi_er_lo32_dtp" (define_insn "*adddi_er_lo32_dtp"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "dtp32_symbolic_operand" "")))] (match_operand:DI 2 "dtp32_symbolic_operand")))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
"lda %0,%2(%1)\t\t!dtprello") "lda %0,%2(%1)\t\t!dtprello")
(define_insn "*adddi_er_lo16_tp" (define_insn "*adddi_er_lo16_tp"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "tp16_symbolic_operand" "")))] (match_operand:DI 2 "tp16_symbolic_operand")))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
"lda %0,%2(%1)\t\t!tprel") "lda %0,%2(%1)\t\t!tprel")
(define_insn "*adddi_er_hi32_tp" (define_insn "*adddi_er_hi32_tp"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "r") (plus:DI (match_operand:DI 1 "register_operand" "r")
(high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))] (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
"ldah %0,%2(%1)\t\t!tprelhi") "ldah %0,%2(%1)\t\t!tprelhi")
(define_insn "*adddi_er_lo32_tp" (define_insn "*adddi_er_lo32_tp"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "tp32_symbolic_operand" "")))] (match_operand:DI 2 "tp32_symbolic_operand")))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
"lda %0,%2(%1)\t\t!tprello") "lda %0,%2(%1)\t\t!tprello")
(define_insn "*adddi_er_high_l" (define_insn "*adddi_er_high_l"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "r") (plus:DI (match_operand:DI 1 "register_operand" "r")
(high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))] (high:DI (match_operand:DI 2 "local_symbolic_operand"))))]
"TARGET_EXPLICIT_RELOCS && reload_completed" "TARGET_EXPLICIT_RELOCS && reload_completed"
"ldah %0,%2(%1)\t\t!gprelhigh" "ldah %0,%2(%1)\t\t!gprelhigh"
[(set_attr "usegp" "yes")]) [(set_attr "usegp" "yes")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(high:DI (match_operand:DI 1 "local_symbolic_operand" "")))] (high:DI (match_operand:DI 1 "local_symbolic_operand")))]
"TARGET_EXPLICIT_RELOCS && reload_completed" "TARGET_EXPLICIT_RELOCS && reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(plus:DI (match_dup 2) (high:DI (match_dup 1))))] (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
...@@ -493,9 +488,9 @@ ...@@ -493,9 +488,9 @@
;; Don't do this if we are adjusting SP since we don't want to do it ;; Don't do this if we are adjusting SP since we don't want to do it
;; in two steps. Don't split FP sources for the reason listed above. ;; in two steps. Don't split FP sources for the reason listed above.
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(plus:DI (match_operand:DI 1 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "const_int_operand" "")))] (match_operand:DI 2 "const_int_operand")))]
"! add_operand (operands[2], DImode) "! add_operand (operands[2], DImode)
&& operands[0] != stack_pointer_rtx && operands[0] != stack_pointer_rtx
&& operands[1] != frame_pointer_rtx && operands[1] != frame_pointer_rtx
...@@ -545,14 +540,14 @@ ...@@ -545,14 +540,14 @@
s%2subl %1,%n3,%0") s%2subl %1,%n3,%0")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI (sign_extend:DI
(plus:SI (mult:SI (match_operator:SI 1 "comparison_operator" (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
[(match_operand 2 "" "") [(match_operand 2)
(match_operand 3 "" "")]) (match_operand 3)])
(match_operand:SI 4 "const48_operand" "")) (match_operand:SI 4 "const48_operand"))
(match_operand:SI 5 "sext_add_operand" "")))) (match_operand:SI 5 "sext_add_operand"))))
(clobber (match_operand:DI 6 "reg_not_elim_operand" ""))] (clobber (match_operand:DI 6 "reg_not_elim_operand"))]
"" ""
[(set (match_dup 6) (match_dup 7)) [(set (match_dup 6) (match_dup 7))
(set (match_dup 0) (set (match_dup 0)
...@@ -609,8 +604,9 @@ ...@@ -609,8 +604,9 @@
(define_insn "*subsi_se" (define_insn "*subsi_se"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (sign_extend:DI
(match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
"" ""
"subl %r1,%2,%0") "subl %r1,%2,%0")
...@@ -687,12 +683,12 @@ ...@@ -687,12 +683,12 @@
(set_attr "opsize" "<mode>")]) (set_attr "opsize" "<mode>")])
(define_expand "umuldi3_highpart" (define_expand "umuldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(truncate:DI (truncate:DI
(lshiftrt:TI (lshiftrt:TI
(mult:TI (zero_extend:TI (mult:TI (zero_extend:TI
(match_operand:DI 1 "register_operand" "")) (match_operand:DI 1 "register_operand"))
(match_operand:DI 2 "reg_or_8bit_operand" "")) (match_operand:DI 2 "reg_or_8bit_operand"))
(const_int 64))))] (const_int 64))))]
"" ""
{ {
...@@ -739,15 +735,15 @@ ...@@ -739,15 +735,15 @@
(define_expand "<code>si3" (define_expand "<code>si3"
[(set (match_dup 3) [(set (match_dup 3)
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))) (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))
(set (match_dup 4) (set (match_dup 4)
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand")))
(parallel [(set (match_dup 5) (parallel [(set (match_dup 5)
(sign_extend:DI (sign_extend:DI
(any_divmod:SI (match_dup 3) (match_dup 4)))) (any_divmod:SI (match_dup 3) (match_dup 4))))
(clobber (reg:DI 23)) (clobber (reg:DI 23))
(clobber (reg:DI 28))]) (clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand" "") (set (match_operand:SI 0 "nonimmediate_operand")
(subreg:SI (match_dup 5) 0))] (subreg:SI (match_dup 5) 0))]
"TARGET_ABI_OSF" "TARGET_ABI_OSF"
{ {
...@@ -757,14 +753,13 @@ ...@@ -757,14 +753,13 @@
}) })
(define_expand "<code>di3" (define_expand "<code>di3"
[(parallel [(set (match_operand:DI 0 "register_operand" "") [(parallel [(set (match_operand:DI 0 "register_operand")
(any_divmod:DI (any_divmod:DI
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "register_operand" ""))) (match_operand:DI 2 "register_operand")))
(clobber (reg:DI 23)) (clobber (reg:DI 23))
(clobber (reg:DI 28))])] (clobber (reg:DI 28))])]
"TARGET_ABI_OSF" "TARGET_ABI_OSF")
"")
;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
;; expanded by the assembler. ;; expanded by the assembler.
...@@ -818,7 +813,7 @@ ...@@ -818,7 +813,7 @@
[(match_operand:DI 1 "register_operand" "a") [(match_operand:DI 1 "register_operand" "a")
(match_operand:DI 2 "register_operand" "b")]))) (match_operand:DI 2 "register_operand" "b")])))
(use (match_operand:DI 4 "register_operand" "c")) (use (match_operand:DI 4 "register_operand" "c"))
(use (match_operand 5 "const_int_operand" "")) (use (match_operand 5 "const_int_operand"))
(clobber (reg:DI 23)) (clobber (reg:DI 23))
(clobber (reg:DI 28))] (clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
...@@ -886,7 +881,7 @@ ...@@ -886,7 +881,7 @@
[(match_operand:DI 1 "register_operand" "a") [(match_operand:DI 1 "register_operand" "a")
(match_operand:DI 2 "register_operand" "b")])) (match_operand:DI 2 "register_operand" "b")]))
(use (match_operand:DI 4 "register_operand" "c")) (use (match_operand:DI 4 "register_operand" "c"))
(use (match_operand 5 "const_int_operand" "")) (use (match_operand 5 "const_int_operand"))
(clobber (reg:DI 23)) (clobber (reg:DI 23))
(clobber (reg:DI 28))] (clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
...@@ -939,9 +934,9 @@ ...@@ -939,9 +934,9 @@
;; too messy otherwise. ;; too messy otherwise.
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(and:DI (match_operand:DI 1 "register_operand" "") (and:DI (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "const_int_operand" "")))] (match_operand:DI 2 "const_int_operand")))]
"HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)" "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
[(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
(set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
...@@ -1076,10 +1071,10 @@ ...@@ -1076,10 +1071,10 @@
(define_expand "ffsdi2" (define_expand "ffsdi2"
[(set (match_dup 2) [(set (match_dup 2)
(ctz:DI (match_operand:DI 1 "register_operand" ""))) (ctz:DI (match_operand:DI 1 "register_operand")))
(set (match_dup 3) (set (match_dup 3)
(plus:DI (match_dup 2) (const_int 1))) (plus:DI (match_dup 2) (const_int 1)))
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (eq (match_dup 1) (const_int 0)) (if_then_else:DI (eq (match_dup 1) (const_int 0))
(const_int 0) (match_dup 3)))] (const_int 0) (match_dup 3)))]
"TARGET_CIX" "TARGET_CIX"
...@@ -1110,8 +1105,8 @@ ...@@ -1110,8 +1105,8 @@
[(set_attr "type" "mvi")]) [(set_attr "type" "mvi")])
(define_expand "bswapsi2" (define_expand "bswapsi2"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand")
(bswap:SI (match_operand:SI 1 "register_operand" "")))] (bswap:SI (match_operand:SI 1 "register_operand")))]
"!optimize_size" "!optimize_size"
{ {
rtx t0, t1; rtx t0, t1;
...@@ -1132,8 +1127,8 @@ ...@@ -1132,8 +1127,8 @@
}) })
(define_expand "bswapdi2" (define_expand "bswapdi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(bswap:DI (match_operand:DI 1 "register_operand" "")))] (bswap:DI (match_operand:DI 1 "register_operand")))]
"!optimize_size" "!optimize_size"
{ {
rtx t0, t1; rtx t0, t1;
...@@ -1225,8 +1220,8 @@ ...@@ -1225,8 +1220,8 @@
[(set_attr "type" "shift")]) [(set_attr "type" "shift")])
(define_expand "extendqidi2" (define_expand "extendqidi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI (match_operand:QI 1 "some_operand" "")))] (sign_extend:DI (match_operand:QI 1 "some_operand")))]
"" ""
{ {
if (TARGET_BWX) if (TARGET_BWX)
...@@ -1270,8 +1265,8 @@ ...@@ -1270,8 +1265,8 @@
[(set_attr "type" "shift")]) [(set_attr "type" "shift")])
(define_expand "extendhidi2" (define_expand "extendhidi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI (match_operand:HI 1 "some_operand" "")))] (sign_extend:DI (match_operand:HI 1 "some_operand")))]
"" ""
{ {
if (TARGET_BWX) if (TARGET_BWX)
...@@ -1315,14 +1310,14 @@ ...@@ -1315,14 +1310,14 @@
(define_expand "unaligned_extendqidi" (define_expand "unaligned_extendqidi"
[(set (match_dup 3) [(set (match_dup 3)
(mem:DI (and:DI (match_operand:DI 1 "address_operand" "") (const_int -8)))) (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8))))
(set (match_dup 4) (set (match_dup 4)
(ashift:DI (match_dup 3) (ashift:DI (match_dup 3)
(minus:DI (const_int 64) (minus:DI (const_int 64)
(ashift:DI (ashift:DI
(and:DI (match_dup 2) (const_int 7)) (and:DI (match_dup 2) (const_int 7))
(const_int 3))))) (const_int 3)))))
(set (match_operand:QI 0 "register_operand" "") (set (match_operand:QI 0 "register_operand")
(ashiftrt:DI (match_dup 4) (const_int 56)))] (ashiftrt:DI (match_dup 4) (const_int 56)))]
"" ""
{ {
...@@ -1334,14 +1329,14 @@ ...@@ -1334,14 +1329,14 @@
(define_expand "unaligned_extendhidi" (define_expand "unaligned_extendhidi"
[(set (match_dup 3) [(set (match_dup 3)
(mem:DI (and:DI (match_operand:DI 1 "address_operand" "") (const_int -8)))) (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8))))
(set (match_dup 4) (set (match_dup 4)
(ashift:DI (match_dup 3) (ashift:DI (match_dup 3)
(minus:DI (const_int 64) (minus:DI (const_int 64)
(ashift:DI (ashift:DI
(and:DI (match_dup 2) (const_int 7)) (and:DI (match_dup 2) (const_int 7))
(const_int 3))))) (const_int 3)))))
(set (match_operand:HI 0 "register_operand" "") (set (match_operand:HI 0 "register_operand")
(ashiftrt:DI (match_dup 4) (const_int 48)))] (ashiftrt:DI (match_dup 4) (const_int 48)))]
"" ""
{ {
...@@ -1362,10 +1357,11 @@ ...@@ -1362,10 +1357,11 @@
(define_insn "extxl" (define_insn "extxl"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (zero_extract:DI
(match_operand:DI 2 "mode_width_operand" "n") (match_operand:DI 1 "reg_or_0_operand" "rJ")
(ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") (match_operand:DI 2 "mode_width_operand" "n")
(const_int 3))))] (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
(const_int 3))))]
"" ""
"ext%M2l %r1,%3,%0" "ext%M2l %r1,%3,%0"
[(set_attr "type" "shift")]) [(set_attr "type" "shift")])
...@@ -1441,13 +1437,13 @@ ...@@ -1441,13 +1437,13 @@
;; to the address calculation. ;; to the address calculation.
;;(define_split ;;(define_split
;; [(set (match_operand:DI 0 "register_operand" "") ;; [(set (match_operand:DI 0 "register_operand")
;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "") ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand")
;; (match_operand:DI 2 "mode_width_operand" "") ;; (match_operand:DI 2 "mode_width_operand")
;; (ashift:DI (match_operand:DI 3 "" "") ;; (ashift:DI (match_operand:DI 3)
;; (const_int 3))) ;; (const_int 3)))
;; (match_operand:DI 4 "const_int_operand" ""))) ;; (match_operand:DI 4 "const_int_operand")))
;; (clobber (match_operand:DI 5 "register_operand" ""))] ;; (clobber (match_operand:DI 5 "register_operand"))]
;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
;; [(set (match_dup 5) (match_dup 6)) ;; [(set (match_dup 5) (match_dup 6))
;; (set (match_dup 0) ;; (set (match_dup 0)
...@@ -1605,8 +1601,8 @@ ...@@ -1605,8 +1601,8 @@
[(set_attr "type" "fadd")]) [(set_attr "type" "fadd")])
(define_expand "abstf2" (define_expand "abstf2"
[(parallel [(set (match_operand:TF 0 "register_operand" "") [(parallel [(set (match_operand:TF 0 "register_operand")
(abs:TF (match_operand:TF 1 "reg_or_0_operand" ""))) (abs:TF (match_operand:TF 1 "reg_or_0_operand")))
(use (match_dup 2))])] (use (match_dup 2))])]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
{ {
...@@ -1635,8 +1631,8 @@ ...@@ -1635,8 +1631,8 @@
[(set_attr "type" "fadd")]) [(set_attr "type" "fadd")])
(define_expand "negtf2" (define_expand "negtf2"
[(parallel [(set (match_operand:TF 0 "register_operand" "") [(parallel [(set (match_operand:TF 0 "register_operand")
(neg:TF (match_operand:TF 1 "reg_or_0_operand" ""))) (neg:TF (match_operand:TF 1 "reg_or_0_operand")))
(use (match_dup 2))])] (use (match_dup 2))])]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
{ {
...@@ -1724,9 +1720,9 @@ ...@@ -1724,9 +1720,9 @@
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_expand "addtf3" (define_expand "addtf3"
[(use (match_operand:TF 0 "register_operand" "")) [(use (match_operand:TF 0 "register_operand"))
(use (match_operand:TF 1 "general_operand" "")) (use (match_operand:TF 1 "general_operand"))
(use (match_operand:TF 2 "general_operand" ""))] (use (match_operand:TF 2 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (PLUS, operands); DONE;") "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
...@@ -1790,9 +1786,9 @@ ...@@ -1790,9 +1786,9 @@
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_expand "subtf3" (define_expand "subtf3"
[(use (match_operand:TF 0 "register_operand" "")) [(use (match_operand:TF 0 "register_operand"))
(use (match_operand:TF 1 "general_operand" "")) (use (match_operand:TF 1 "general_operand"))
(use (match_operand:TF 2 "general_operand" ""))] (use (match_operand:TF 2 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (MINUS, operands); DONE;") "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
...@@ -1844,9 +1840,9 @@ ...@@ -1844,9 +1840,9 @@
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_expand "multf3" (define_expand "multf3"
[(use (match_operand:TF 0 "register_operand" "")) [(use (match_operand:TF 0 "register_operand"))
(use (match_operand:TF 1 "general_operand" "")) (use (match_operand:TF 1 "general_operand"))
(use (match_operand:TF 2 "general_operand" ""))] (use (match_operand:TF 2 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (MULT, operands); DONE;") "alpha_emit_xfloating_arith (MULT, operands); DONE;")
...@@ -1899,8 +1895,10 @@ ...@@ -1899,8 +1895,10 @@
(define_insn "*divdf_ext3" (define_insn "*divdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) (div:DF (float_extend:DF
(float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))] (match_operand:SF 1 "reg_or_0_operand" "fG"))
(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0" "div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv") [(set_attr "type" "fdiv")
...@@ -1909,9 +1907,9 @@ ...@@ -1909,9 +1907,9 @@
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_expand "divtf3" (define_expand "divtf3"
[(use (match_operand:TF 0 "register_operand" "")) [(use (match_operand:TF 0 "register_operand"))
(use (match_operand:TF 1 "general_operand" "")) (use (match_operand:TF 1 "general_operand"))
(use (match_operand:TF 2 "general_operand" ""))] (use (match_operand:TF 2 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (DIV, operands); DONE;") "alpha_emit_xfloating_arith (DIV, operands); DONE;")
...@@ -2017,16 +2015,14 @@ ...@@ -2017,16 +2015,14 @@
(set_attr "trap_suffix" "v_sv_svi")]) (set_attr "trap_suffix" "v_sv_svi")])
(define_expand "fix_truncdfdi2" (define_expand "fix_truncdfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "") [(set (match_operand:DI 0 "reg_no_subreg_operand")
(fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))] (fix:DI (match_operand:DF 1 "reg_or_0_operand")))]
"TARGET_FP" "TARGET_FP")
"")
(define_expand "fixuns_truncdfdi2" (define_expand "fixuns_truncdfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "") [(set (match_operand:DI 0 "reg_no_subreg_operand")
(unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))] (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))]
"TARGET_FP" "TARGET_FP")
"")
;; Likewise between SFmode and SImode. ;; Likewise between SFmode and SImode.
...@@ -2044,9 +2040,7 @@ ...@@ -2044,9 +2040,7 @@
[(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))])) [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
(set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 5) (match_dup 3))] (set (match_dup 5) (match_dup 3))]
{ "operands[5] = adjust_address (operands[0], SFmode, 0);"
operands[5] = adjust_address (operands[0], SFmode, 0);
}
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "trap" "yes")]) (set_attr "trap" "yes")])
...@@ -2093,27 +2087,25 @@ ...@@ -2093,27 +2087,25 @@
(set_attr "trap_suffix" "v_sv_svi")]) (set_attr "trap_suffix" "v_sv_svi")])
(define_expand "fix_truncsfdi2" (define_expand "fix_truncsfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "") [(set (match_operand:DI 0 "reg_no_subreg_operand")
(fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))] (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))]
"TARGET_FP" "TARGET_FP")
"")
(define_expand "fixuns_truncsfdi2" (define_expand "fixuns_truncsfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "") [(set (match_operand:DI 0 "reg_no_subreg_operand")
(unsigned_fix:DI (unsigned_fix:DI
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))] (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))]
"TARGET_FP" "TARGET_FP")
"")
(define_expand "fix_trunctfdi2" (define_expand "fix_trunctfdi2"
[(use (match_operand:DI 0 "register_operand" "")) [(use (match_operand:DI 0 "register_operand"))
(use (match_operand:TF 1 "general_operand" ""))] (use (match_operand:TF 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FIX, operands); DONE;") "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
(define_expand "fixuns_trunctfdi2" (define_expand "fixuns_trunctfdi2"
[(use (match_operand:DI 0 "register_operand" "")) [(use (match_operand:DI 0 "register_operand"))
(use (match_operand:TF 1 "general_operand" ""))] (use (match_operand:TF 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;") "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
...@@ -2148,9 +2140,7 @@ ...@@ -2148,9 +2140,7 @@
[(set (match_dup 3) (match_dup 1)) [(set (match_dup 3) (match_dup 1))
(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
(set (match_dup 0) (float:SF (match_dup 2)))] (set (match_dup 0) (float:SF (match_dup 2)))]
{ "operands[1] = adjust_address (operands[1], SFmode, 0);")
operands[1] = adjust_address (operands[1], SFmode, 0);
})
(define_insn_and_split "*floatsisf2" (define_insn_and_split "*floatsisf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
...@@ -2197,9 +2187,7 @@ ...@@ -2197,9 +2187,7 @@
[(set (match_dup 3) (match_dup 1)) [(set (match_dup 3) (match_dup 1))
(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
(set (match_dup 0) (float:DF (match_dup 2)))] (set (match_dup 0) (float:DF (match_dup 2)))]
{ "operands[1] = adjust_address (operands[1], SFmode, 0);")
operands[1] = adjust_address (operands[1], SFmode, 0);
})
(define_insn_and_split "*floatsidf2" (define_insn_and_split "*floatsidf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
...@@ -2217,32 +2205,32 @@ ...@@ -2217,32 +2205,32 @@
}) })
(define_expand "floatditf2" (define_expand "floatditf2"
[(use (match_operand:TF 0 "register_operand" "")) [(use (match_operand:TF 0 "register_operand"))
(use (match_operand:DI 1 "general_operand" ""))] (use (match_operand:DI 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FLOAT, operands); DONE;") "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
(define_expand "floatunsdisf2" (define_expand "floatunsdisf2"
[(use (match_operand:SF 0 "register_operand" "")) [(use (match_operand:SF 0 "register_operand"))
(use (match_operand:DI 1 "register_operand" ""))] (use (match_operand:DI 1 "register_operand"))]
"TARGET_FP" "TARGET_FP"
"alpha_emit_floatuns (operands); DONE;") "alpha_emit_floatuns (operands); DONE;")
(define_expand "floatunsdidf2" (define_expand "floatunsdidf2"
[(use (match_operand:DF 0 "register_operand" "")) [(use (match_operand:DF 0 "register_operand"))
(use (match_operand:DI 1 "register_operand" ""))] (use (match_operand:DI 1 "register_operand"))]
"TARGET_FP" "TARGET_FP"
"alpha_emit_floatuns (operands); DONE;") "alpha_emit_floatuns (operands); DONE;")
(define_expand "floatunsditf2" (define_expand "floatunsditf2"
[(use (match_operand:TF 0 "register_operand" "")) [(use (match_operand:TF 0 "register_operand"))
(use (match_operand:DI 1 "general_operand" ""))] (use (match_operand:DI 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;") "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
(define_expand "extendsfdf2" (define_expand "extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "") [(set (match_operand:DF 0 "register_operand")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))]
"TARGET_FP" "TARGET_FP"
{ {
if (alpha_fptm >= ALPHA_FPTM_SU) if (alpha_fptm >= ALPHA_FPTM_SU)
...@@ -2274,8 +2262,8 @@ ...@@ -2274,8 +2262,8 @@
;; from doing something silly. When optimizing we'll put things back ;; from doing something silly. When optimizing we'll put things back
;; together anyway. ;; together anyway.
(define_expand "extendsftf2" (define_expand "extendsftf2"
[(use (match_operand:TF 0 "register_operand" "")) [(use (match_operand:TF 0 "register_operand"))
(use (match_operand:SF 1 "register_operand" ""))] (use (match_operand:SF 1 "register_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
{ {
rtx tmp = gen_reg_rtx (DFmode); rtx tmp = gen_reg_rtx (DFmode);
...@@ -2285,8 +2273,8 @@ ...@@ -2285,8 +2273,8 @@
}) })
(define_expand "extenddftf2" (define_expand "extenddftf2"
[(use (match_operand:TF 0 "register_operand" "")) [(use (match_operand:TF 0 "register_operand"))
(use (match_operand:DF 1 "register_operand" ""))] (use (match_operand:DF 1 "register_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;") "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
...@@ -2311,14 +2299,14 @@ ...@@ -2311,14 +2299,14 @@
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_expand "trunctfdf2" (define_expand "trunctfdf2"
[(use (match_operand:DF 0 "register_operand" "")) [(use (match_operand:DF 0 "register_operand"))
(use (match_operand:TF 1 "general_operand" ""))] (use (match_operand:TF 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;") "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
(define_expand "trunctfsf2" (define_expand "trunctfsf2"
[(use (match_operand:SF 0 "register_operand" "")) [(use (match_operand:SF 0 "register_operand"))
(use (match_operand:TF 1 "general_operand" ""))] (use (match_operand:TF 1 "general_operand"))]
"TARGET_FP && TARGET_HAS_XFLOATING_LIBS" "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
{ {
rtx tmpf, sticky, arg, lo, hi; rtx tmpf, sticky, arg, lo, hi;
...@@ -2440,8 +2428,8 @@ ...@@ -2440,8 +2428,8 @@
;; For ABS, we have two choices, depending on whether the input and output ;; For ABS, we have two choices, depending on whether the input and output
;; registers are the same or not. ;; registers are the same or not.
(define_expand "absdi2" (define_expand "absdi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(abs:DI (match_operand:DI 1 "register_operand" "")))] (abs:DI (match_operand:DI 1 "register_operand")))]
"" ""
{ {
if (rtx_equal_p (operands[0], operands[1])) if (rtx_equal_p (operands[0], operands[1]))
...@@ -2452,62 +2440,54 @@ ...@@ -2452,62 +2440,54 @@
}) })
(define_expand "absdi2_same" (define_expand "absdi2_same"
[(set (match_operand:DI 1 "register_operand" "") [(set (match_operand:DI 1 "register_operand")
(neg:DI (match_operand:DI 0 "register_operand" ""))) (neg:DI (match_operand:DI 0 "register_operand")))
(set (match_dup 0) (set (match_dup 0)
(if_then_else:DI (ge (match_dup 0) (const_int 0)) (if_then_else:DI (ge (match_dup 0) (const_int 0))
(match_dup 0) (match_dup 0)
(match_dup 1)))] (match_dup 1)))])
""
"")
(define_expand "absdi2_diff" (define_expand "absdi2_diff"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(neg:DI (match_operand:DI 1 "register_operand" ""))) (neg:DI (match_operand:DI 1 "register_operand")))
(set (match_dup 0) (set (match_dup 0)
(if_then_else:DI (lt (match_dup 1) (const_int 0)) (if_then_else:DI (lt (match_dup 1) (const_int 0))
(match_dup 0) (match_dup 0)
(match_dup 1)))] (match_dup 1)))])
""
"")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(abs:DI (match_dup 0))) (abs:DI (match_dup 0)))
(clobber (match_operand:DI 1 "register_operand" ""))] (clobber (match_operand:DI 1 "register_operand"))]
"" ""
[(set (match_dup 1) (neg:DI (match_dup 0))) [(set (match_dup 1) (neg:DI (match_dup 0)))
(set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
(match_dup 0) (match_dup 1)))] (match_dup 0) (match_dup 1)))])
"")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(abs:DI (match_operand:DI 1 "register_operand" "")))] (abs:DI (match_operand:DI 1 "register_operand")))]
"! rtx_equal_p (operands[0], operands[1])" "! rtx_equal_p (operands[0], operands[1])"
[(set (match_dup 0) (neg:DI (match_dup 1))) [(set (match_dup 0) (neg:DI (match_dup 1)))
(set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
(match_dup 0) (match_dup 1)))] (match_dup 0) (match_dup 1)))])
"")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(neg:DI (abs:DI (match_dup 0)))) (neg:DI (abs:DI (match_dup 0))))
(clobber (match_operand:DI 1 "register_operand" ""))] (clobber (match_operand:DI 1 "register_operand"))]
"" ""
[(set (match_dup 1) (neg:DI (match_dup 0))) [(set (match_dup 1) (neg:DI (match_dup 0)))
(set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
(match_dup 0) (match_dup 1)))] (match_dup 0) (match_dup 1)))])
"")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))] (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))]
"! rtx_equal_p (operands[0], operands[1])" "! rtx_equal_p (operands[0], operands[1])"
[(set (match_dup 0) (neg:DI (match_dup 1))) [(set (match_dup 0) (neg:DI (match_dup 1)))
(set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
(match_dup 0) (match_dup 1)))] (match_dup 0) (match_dup 1)))])
"")
(define_insn "<code><mode>3" (define_insn "<code><mode>3"
[(set (match_operand:I12MODE 0 "register_operand" "=r") [(set (match_operand:I12MODE 0 "register_operand" "=r")
...@@ -2520,24 +2500,23 @@ ...@@ -2520,24 +2500,23 @@
(define_expand "smaxdi3" (define_expand "smaxdi3"
[(set (match_dup 3) [(set (match_dup 3)
(le:DI (match_operand:DI 1 "reg_or_0_operand" "") (le:DI (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" ""))) (match_operand:DI 2 "reg_or_8bit_operand")))
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (eq (match_dup 3) (const_int 0)) (if_then_else:DI (eq (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"" ""
{ operands[3] = gen_reg_rtx (DImode); }) "operands[3] = gen_reg_rtx (DImode);")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(smax:DI (match_operand:DI 1 "reg_or_0_operand" "") (smax:DI (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" ""))) (match_operand:DI 2 "reg_or_8bit_operand")))
(clobber (match_operand:DI 3 "register_operand" ""))] (clobber (match_operand:DI 3 "register_operand"))]
"operands[2] != const0_rtx" "operands[2] != const0_rtx"
[(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))])
"")
(define_insn "*smax_const0" (define_insn "*smax_const0"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2549,24 +2528,23 @@ ...@@ -2549,24 +2528,23 @@
(define_expand "smindi3" (define_expand "smindi3"
[(set (match_dup 3) [(set (match_dup 3)
(lt:DI (match_operand:DI 1 "reg_or_0_operand" "") (lt:DI (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" ""))) (match_operand:DI 2 "reg_or_8bit_operand")))
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (ne (match_dup 3) (const_int 0)) (if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"" ""
{ operands[3] = gen_reg_rtx (DImode); }) "operands[3] = gen_reg_rtx (DImode);")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(smin:DI (match_operand:DI 1 "reg_or_0_operand" "") (smin:DI (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" ""))) (match_operand:DI 2 "reg_or_8bit_operand")))
(clobber (match_operand:DI 3 "register_operand" ""))] (clobber (match_operand:DI 3 "register_operand"))]
"operands[2] != const0_rtx" "operands[2] != const0_rtx"
[(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))])
"")
(define_insn "*smin_const0" (define_insn "*smin_const0"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2578,45 +2556,43 @@ ...@@ -2578,45 +2556,43 @@
(define_expand "umaxdi3" (define_expand "umaxdi3"
[(set (match_dup 3) [(set (match_dup 3)
(leu:DI (match_operand:DI 1 "reg_or_0_operand" "") (leu:DI (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" ""))) (match_operand:DI 2 "reg_or_8bit_operand")))
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (eq (match_dup 3) (const_int 0)) (if_then_else:DI (eq (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"" ""
"operands[3] = gen_reg_rtx (DImode);") "operands[3] = gen_reg_rtx (DImode);")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(umax:DI (match_operand:DI 1 "reg_or_0_operand" "") (umax:DI (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" ""))) (match_operand:DI 2 "reg_or_8bit_operand")))
(clobber (match_operand:DI 3 "register_operand" ""))] (clobber (match_operand:DI 3 "register_operand"))]
"operands[2] != const0_rtx" "operands[2] != const0_rtx"
[(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))])
"")
(define_expand "umindi3" (define_expand "umindi3"
[(set (match_dup 3) [(set (match_dup 3)
(ltu:DI (match_operand:DI 1 "reg_or_0_operand" "") (ltu:DI (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" ""))) (match_operand:DI 2 "reg_or_8bit_operand")))
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (ne (match_dup 3) (const_int 0)) (if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"" ""
"operands[3] = gen_reg_rtx (DImode);") "operands[3] = gen_reg_rtx (DImode);")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(umin:DI (match_operand:DI 1 "reg_or_0_operand" "") (umin:DI (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" ""))) (match_operand:DI 2 "reg_or_8bit_operand")))
(clobber (match_operand:DI 3 "register_operand" ""))] (clobber (match_operand:DI 3 "register_operand"))]
"operands[2] != const0_rtx" "operands[2] != const0_rtx"
[(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))])
"")
(define_insn "*bcc_normal" (define_insn "*bcc_normal"
[(set (pc) [(set (pc)
...@@ -2624,7 +2600,7 @@ ...@@ -2624,7 +2600,7 @@
(match_operator 1 "signed_comparison_operator" (match_operator 1 "signed_comparison_operator"
[(match_operand:DI 2 "reg_or_0_operand" "rJ") [(match_operand:DI 2 "reg_or_0_operand" "rJ")
(const_int 0)]) (const_int 0)])
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0))
(pc)))] (pc)))]
"" ""
"b%C1 %r2,%0" "b%C1 %r2,%0"
...@@ -2638,7 +2614,7 @@ ...@@ -2638,7 +2614,7 @@
(const_int 0)]) (const_int 0)])
(pc) (pc)
(label_ref (match_operand 0 "" ""))))] (label_ref (match_operand 0))))]
"" ""
"b%c1 %2,%0" "b%c1 %2,%0"
[(set_attr "type" "ibr")]) [(set_attr "type" "ibr")])
...@@ -2650,7 +2626,7 @@ ...@@ -2650,7 +2626,7 @@
(const_int 1) (const_int 1)
(const_int 0)) (const_int 0))
(const_int 0)) (const_int 0))
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0))
(pc)))] (pc)))]
"" ""
"blbs %r1,%0" "blbs %r1,%0"
...@@ -2663,7 +2639,7 @@ ...@@ -2663,7 +2639,7 @@
(const_int 1) (const_int 1)
(const_int 0)) (const_int 0))
(const_int 0)) (const_int 0))
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0))
(pc)))] (pc)))]
"" ""
"blbc %r1,%0" "blbc %r1,%0"
...@@ -2674,13 +2650,13 @@ ...@@ -2674,13 +2650,13 @@
[(set (pc) [(set (pc)
(if_then_else (if_then_else
(match_operator 1 "comparison_operator" (match_operator 1 "comparison_operator"
[(zero_extract:DI (match_operand:DI 2 "register_operand" "") [(zero_extract:DI (match_operand:DI 2 "register_operand")
(const_int 1) (const_int 1)
(match_operand:DI 3 "const_int_operand" "")) (match_operand:DI 3 "const_int_operand"))
(const_int 0)]) (const_int 0)])
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0))
(pc))) (pc)))
(clobber (match_operand:DI 4 "register_operand" ""))])] (clobber (match_operand:DI 4 "register_operand"))])]
"INTVAL (operands[3]) != 0" "INTVAL (operands[3]) != 0"
[(set (match_dup 4) [(set (match_dup 4)
(lshiftrt:DI (match_dup 2) (match_dup 3))) (lshiftrt:DI (match_dup 2) (match_dup 3)))
...@@ -2692,7 +2668,7 @@ ...@@ -2692,7 +2668,7 @@
(const_int 0)]) (const_int 0)])
(label_ref (match_dup 0)) (label_ref (match_dup 0))
(pc)))] (pc)))]
"") )
;; The following are the corresponding floating-point insns. Recall ;; The following are the corresponding floating-point insns. Recall
;; we need to have variants that expand the arguments from SFmode ;; we need to have variants that expand the arguments from SFmode
...@@ -2832,9 +2808,9 @@ ...@@ -2832,9 +2808,9 @@
(define_expand "smaxdf3" (define_expand "smaxdf3"
[(set (match_dup 3) [(set (match_dup 3)
(le:DF (match_operand:DF 1 "reg_or_0_operand" "") (le:DF (match_operand:DF 1 "reg_or_0_operand")
(match_operand:DF 2 "reg_or_0_operand" ""))) (match_operand:DF 2 "reg_or_0_operand")))
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand")
(if_then_else:DF (eq (match_dup 3) (match_dup 4)) (if_then_else:DF (eq (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"TARGET_FP" "TARGET_FP"
...@@ -2845,9 +2821,9 @@ ...@@ -2845,9 +2821,9 @@
(define_expand "smindf3" (define_expand "smindf3"
[(set (match_dup 3) [(set (match_dup 3)
(lt:DF (match_operand:DF 1 "reg_or_0_operand" "") (lt:DF (match_operand:DF 1 "reg_or_0_operand")
(match_operand:DF 2 "reg_or_0_operand" ""))) (match_operand:DF 2 "reg_or_0_operand")))
(set (match_operand:DF 0 "register_operand" "") (set (match_operand:DF 0 "register_operand")
(if_then_else:DF (ne (match_dup 3) (match_dup 4)) (if_then_else:DF (ne (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"TARGET_FP" "TARGET_FP"
...@@ -2858,9 +2834,9 @@ ...@@ -2858,9 +2834,9 @@
(define_expand "smaxsf3" (define_expand "smaxsf3"
[(set (match_dup 3) [(set (match_dup 3)
(le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "")) (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))
(float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "")))) (float_extend:DF (match_operand:SF 2 "reg_or_0_operand"))))
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand")
(if_then_else:SF (eq (match_dup 3) (match_dup 4)) (if_then_else:SF (eq (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
...@@ -2871,9 +2847,9 @@ ...@@ -2871,9 +2847,9 @@
(define_expand "sminsf3" (define_expand "sminsf3"
[(set (match_dup 3) [(set (match_dup 3)
(lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "")) (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))
(float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "")))) (float_extend:DF (match_operand:SF 2 "reg_or_0_operand"))))
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand")
(if_then_else:SF (ne (match_dup 3) (match_dup 4)) (if_then_else:SF (ne (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
...@@ -2888,7 +2864,7 @@ ...@@ -2888,7 +2864,7 @@
(match_operator 1 "signed_comparison_operator" (match_operator 1 "signed_comparison_operator"
[(match_operand:DF 2 "reg_or_0_operand" "fG") [(match_operand:DF 2 "reg_or_0_operand" "fG")
(match_operand:DF 3 "const0_operand" "G")]) (match_operand:DF 3 "const0_operand" "G")])
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0))
(pc)))] (pc)))]
"TARGET_FP" "TARGET_FP"
"fb%C1 %R2,%0" "fb%C1 %R2,%0"
...@@ -2901,7 +2877,7 @@ ...@@ -2901,7 +2877,7 @@
[(float_extend:DF [(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG")) (match_operand:SF 2 "reg_or_0_operand" "fG"))
(match_operand:DF 3 "const0_operand" "G")]) (match_operand:DF 3 "const0_operand" "G")])
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0))
(pc)))] (pc)))]
"TARGET_FP" "TARGET_FP"
"fb%C1 %R2,%0" "fb%C1 %R2,%0"
...@@ -2912,27 +2888,27 @@ ...@@ -2912,27 +2888,27 @@
(define_expand "cbranchdf4" (define_expand "cbranchdf4"
[(use (match_operator 0 "alpha_cbranch_operator" [(use (match_operator 0 "alpha_cbranch_operator"
[(match_operand:DF 1 "reg_or_0_operand" "") [(match_operand:DF 1 "reg_or_0_operand")
(match_operand:DF 2 "reg_or_0_operand" "")])) (match_operand:DF 2 "reg_or_0_operand")]))
(use (match_operand 3 ""))] (use (match_operand 3))]
"TARGET_FP" "TARGET_FP"
{ alpha_emit_conditional_branch (operands, DFmode); DONE; }) "alpha_emit_conditional_branch (operands, DFmode); DONE;")
(define_expand "cbranchtf4" (define_expand "cbranchtf4"
[(use (match_operator 0 "alpha_cbranch_operator" [(use (match_operator 0 "alpha_cbranch_operator"
[(match_operand:TF 1 "general_operand") [(match_operand:TF 1 "general_operand")
(match_operand:TF 2 "general_operand")])) (match_operand:TF 2 "general_operand")]))
(use (match_operand 3 ""))] (use (match_operand 3))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
{ alpha_emit_conditional_branch (operands, TFmode); DONE; }) "alpha_emit_conditional_branch (operands, TFmode); DONE;")
(define_expand "cbranchdi4" (define_expand "cbranchdi4"
[(use (match_operator 0 "alpha_cbranch_operator" [(use (match_operator 0 "alpha_cbranch_operator"
[(match_operand:DI 1 "some_operand") [(match_operand:DI 1 "some_operand")
(match_operand:DI 2 "some_operand")])) (match_operand:DI 2 "some_operand")]))
(use (match_operand 3 ""))] (use (match_operand 3))]
"" ""
{ alpha_emit_conditional_branch (operands, DImode); DONE; }) "alpha_emit_conditional_branch (operands, DImode); DONE;")
(define_expand "cstoredf4" (define_expand "cstoredf4"
[(use (match_operator:DI 1 "alpha_cbranch_operator" [(use (match_operator:DI 1 "alpha_cbranch_operator"
...@@ -2940,7 +2916,12 @@ ...@@ -2940,7 +2916,12 @@
(match_operand:DF 3 "reg_or_0_operand")])) (match_operand:DF 3 "reg_or_0_operand")]))
(clobber (match_operand:DI 0 "register_operand"))] (clobber (match_operand:DI 0 "register_operand"))]
"TARGET_FP" "TARGET_FP"
{ if (!alpha_emit_setcc (operands, DFmode)) FAIL; else DONE; }) {
if (alpha_emit_setcc (operands, DFmode))
DONE;
else
FAIL;
})
(define_expand "cstoretf4" (define_expand "cstoretf4"
[(use (match_operator:DI 1 "alpha_cbranch_operator" [(use (match_operator:DI 1 "alpha_cbranch_operator"
...@@ -2948,7 +2929,12 @@ ...@@ -2948,7 +2929,12 @@
(match_operand:TF 3 "general_operand")])) (match_operand:TF 3 "general_operand")]))
(clobber (match_operand:DI 0 "register_operand"))] (clobber (match_operand:DI 0 "register_operand"))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
{ if (!alpha_emit_setcc (operands, TFmode)) FAIL; else DONE; }) {
if (alpha_emit_setcc (operands, TFmode))
DONE;
else
FAIL;
})
(define_expand "cstoredi4" (define_expand "cstoredi4"
[(use (match_operator:DI 1 "alpha_cbranch_operator" [(use (match_operator:DI 1 "alpha_cbranch_operator"
...@@ -2956,16 +2942,21 @@ ...@@ -2956,16 +2942,21 @@
(match_operand:DI 3 "some_operand")])) (match_operand:DI 3 "some_operand")]))
(clobber (match_operand:DI 0 "register_operand"))] (clobber (match_operand:DI 0 "register_operand"))]
"" ""
{ if (!alpha_emit_setcc (operands, DImode)) FAIL; else DONE; }) {
if (alpha_emit_setcc (operands, DImode))
DONE;
else
FAIL;
})
;; These are the main define_expand's used to make conditional moves. ;; These are the main define_expand's used to make conditional moves.
(define_expand "mov<mode>cc" (define_expand "mov<mode>cc"
[(set (match_operand:I48MODE 0 "register_operand" "") [(set (match_operand:I48MODE 0 "register_operand")
(if_then_else:I48MODE (if_then_else:I48MODE
(match_operand 1 "comparison_operator" "") (match_operand 1 "comparison_operator")
(match_operand:I48MODE 2 "reg_or_8bit_operand" "") (match_operand:I48MODE 2 "reg_or_8bit_operand")
(match_operand:I48MODE 3 "reg_or_8bit_operand" "")))] (match_operand:I48MODE 3 "reg_or_8bit_operand")))]
"" ""
{ {
operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode);
...@@ -2974,11 +2965,11 @@ ...@@ -2974,11 +2965,11 @@
}) })
(define_expand "mov<mode>cc" (define_expand "mov<mode>cc"
[(set (match_operand:FMODE 0 "register_operand" "") [(set (match_operand:FMODE 0 "register_operand")
(if_then_else:FMODE (if_then_else:FMODE
(match_operand 1 "comparison_operator" "") (match_operand 1 "comparison_operator")
(match_operand:FMODE 2 "reg_or_8bit_operand" "") (match_operand:FMODE 2 "reg_or_8bit_operand")
(match_operand:FMODE 3 "reg_or_8bit_operand" "")))] (match_operand:FMODE 3 "reg_or_8bit_operand")))]
"" ""
{ {
operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode);
...@@ -3004,14 +2995,14 @@ ...@@ -3004,14 +2995,14 @@
;; operation could have been generated. ;; operation could have been generated.
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(if_then_else:DI (if_then_else:DI
(match_operator 1 "comparison_operator" (match_operator 1 "comparison_operator"
[(match_operand:DI 2 "reg_or_0_operand" "") [(match_operand:DI 2 "reg_or_0_operand")
(match_operand:DI 3 "reg_or_cint_operand" "")]) (match_operand:DI 3 "reg_or_cint_operand")])
(match_operand:DI 4 "reg_or_cint_operand" "") (match_operand:DI 4 "reg_or_cint_operand")
(match_operand:DI 5 "reg_or_cint_operand" ""))) (match_operand:DI 5 "reg_or_cint_operand")))
(clobber (match_operand:DI 6 "register_operand" ""))] (clobber (match_operand:DI 6 "register_operand"))]
"operands[3] != const0_rtx" "operands[3] != const0_rtx"
[(set (match_dup 6) (match_dup 7)) [(set (match_dup 6) (match_dup 7))
(set (match_dup 0) (set (match_dup 0)
...@@ -3061,14 +3052,14 @@ ...@@ -3061,14 +3052,14 @@
}) })
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(if_then_else:DI (if_then_else:DI
(match_operator 1 "comparison_operator" (match_operator 1 "comparison_operator"
[(match_operand:SI 2 "reg_or_0_operand" "") [(match_operand:SI 2 "reg_or_0_operand")
(match_operand:SI 3 "reg_or_cint_operand" "")]) (match_operand:SI 3 "reg_or_cint_operand")])
(match_operand:DI 4 "reg_or_8bit_operand" "") (match_operand:DI 4 "reg_or_8bit_operand")
(match_operand:DI 5 "reg_or_8bit_operand" ""))) (match_operand:DI 5 "reg_or_8bit_operand")))
(clobber (match_operand:DI 6 "register_operand" ""))] (clobber (match_operand:DI 6 "register_operand"))]
"operands[3] != const0_rtx "operands[3] != const0_rtx
&& (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
[(set (match_dup 6) (match_dup 7)) [(set (match_dup 6) (match_dup 7))
...@@ -3098,12 +3089,12 @@ ...@@ -3098,12 +3089,12 @@
;; Prefer to use cmp and arithmetic when possible instead of a cmove. ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
(define_split (define_split
[(set (match_operand 0 "register_operand" "") [(set (match_operand 0 "register_operand")
(if_then_else (match_operator 1 "signed_comparison_operator" (if_then_else (match_operator 1 "signed_comparison_operator"
[(match_operand:DI 2 "reg_or_0_operand" "") [(match_operand:DI 2 "reg_or_0_operand")
(const_int 0)]) (const_int 0)])
(match_operand 3 "const_int_operand" "") (match_operand 3 "const_int_operand")
(match_operand 4 "const_int_operand" "")))] (match_operand 4 "const_int_operand")))]
"" ""
[(const_int 0)] [(const_int 0)]
{ {
...@@ -3117,12 +3108,12 @@ ...@@ -3117,12 +3108,12 @@
;; ??? Why combine is allowed to create such non-canonical rtl, I don't know. ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
;; Oh well, we match it in movcc, so it must be partially our fault. ;; Oh well, we match it in movcc, so it must be partially our fault.
(define_split (define_split
[(set (match_operand 0 "register_operand" "") [(set (match_operand 0 "register_operand")
(if_then_else (match_operator 1 "signed_comparison_operator" (if_then_else (match_operator 1 "signed_comparison_operator"
[(const_int 0) [(const_int 0)
(match_operand:DI 2 "reg_or_0_operand" "")]) (match_operand:DI 2 "reg_or_0_operand")])
(match_operand 3 "const_int_operand" "") (match_operand 3 "const_int_operand")
(match_operand 4 "const_int_operand" "")))] (match_operand 4 "const_int_operand")))]
"" ""
[(const_int 0)] [(const_int 0)]
{ {
...@@ -3298,10 +3289,10 @@ ...@@ -3298,10 +3289,10 @@
;; work differently, so we have different patterns for each. ;; work differently, so we have different patterns for each.
(define_expand "call" (define_expand "call"
[(use (match_operand:DI 0 "" "")) [(use (match_operand:DI 0))
(use (match_operand 1 "" "")) (use (match_operand 1))
(use (match_operand 2 "" "")) (use (match_operand 2))
(use (match_operand 3 "" ""))] (use (match_operand 3))]
"" ""
{ {
if (TARGET_ABI_OPEN_VMS) if (TARGET_ABI_OPEN_VMS)
...@@ -3312,8 +3303,8 @@ ...@@ -3312,8 +3303,8 @@
}) })
(define_expand "sibcall" (define_expand "sibcall"
[(parallel [(call (mem:DI (match_operand 0 "" "")) [(parallel [(call (mem:DI (match_operand 0))
(match_operand 1 "" "")) (match_operand 1))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF" "TARGET_ABI_OSF"
{ {
...@@ -3322,8 +3313,8 @@ ...@@ -3322,8 +3313,8 @@
}) })
(define_expand "call_osf" (define_expand "call_osf"
[(parallel [(call (mem:DI (match_operand 0 "" "")) [(parallel [(call (mem:DI (match_operand 0))
(match_operand 1 "" "")) (match_operand 1))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))])] (clobber (reg:DI 26))])]
"" ""
...@@ -3341,8 +3332,8 @@ ...@@ -3341,8 +3332,8 @@
;; op 1: next_arg_reg (argument information value for R25) ;; op 1: next_arg_reg (argument information value for R25)
;; ;;
(define_expand "call_vms" (define_expand "call_vms"
[(parallel [(call (mem:DI (match_operand 0 "" "")) [(parallel [(call (mem:DI (match_operand 0))
(match_operand 1 "" "")) (match_operand 1))
(use (match_dup 2)) (use (match_dup 2))
(use (reg:DI 25)) (use (reg:DI 25))
(use (reg:DI 26)) (use (reg:DI 26))
...@@ -3369,15 +3360,14 @@ ...@@ -3369,15 +3360,14 @@
operands[0], 8))); operands[0], 8)));
operands[2] = operands[0]; operands[2] = operands[0];
} }
}) })
(define_expand "call_value" (define_expand "call_value"
[(use (match_operand 0 "" "")) [(use (match_operand 0))
(use (match_operand:DI 1 "" "")) (use (match_operand:DI 1))
(use (match_operand 2 "" "")) (use (match_operand 2))
(use (match_operand 3 "" "")) (use (match_operand 3))
(use (match_operand 4 "" ""))] (use (match_operand 4))]
"" ""
{ {
if (TARGET_ABI_OPEN_VMS) if (TARGET_ABI_OPEN_VMS)
...@@ -3390,9 +3380,9 @@ ...@@ -3390,9 +3380,9 @@
}) })
(define_expand "sibcall_value" (define_expand "sibcall_value"
[(parallel [(set (match_operand 0 "" "") [(parallel [(set (match_operand 0)
(call (mem:DI (match_operand 1 "" "")) (call (mem:DI (match_operand 1))
(match_operand 2 "" ""))) (match_operand 2)))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF" "TARGET_ABI_OSF"
{ {
...@@ -3401,9 +3391,9 @@ ...@@ -3401,9 +3391,9 @@
}) })
(define_expand "call_value_osf" (define_expand "call_value_osf"
[(parallel [(set (match_operand 0 "" "") [(parallel [(set (match_operand 0)
(call (mem:DI (match_operand 1 "" "")) (call (mem:DI (match_operand 1))
(match_operand 2 "" ""))) (match_operand 2)))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))])] (clobber (reg:DI 26))])]
"" ""
...@@ -3416,9 +3406,9 @@ ...@@ -3416,9 +3406,9 @@
}) })
(define_expand "call_value_vms" (define_expand "call_value_vms"
[(parallel [(set (match_operand 0 "" "") [(parallel [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "" "")) (call (mem:DI (match_operand:DI 1))
(match_operand 2 "" ""))) (match_operand 2)))
(use (match_dup 3)) (use (match_dup 3))
(use (reg:DI 25)) (use (reg:DI 25))
(use (reg:DI 26)) (use (reg:DI 26))
...@@ -3449,7 +3439,7 @@ ...@@ -3449,7 +3439,7 @@
(define_insn "*call_osf_1_er_noreturn" (define_insn "*call_osf_1_er_noreturn"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
(match_operand 1 "" "")) (match_operand 1))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
...@@ -3463,7 +3453,7 @@ ...@@ -3463,7 +3453,7 @@
(define_insn "*call_osf_1_er" (define_insn "*call_osf_1_er"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
(match_operand 1 "" "")) (match_operand 1))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
...@@ -3477,8 +3467,8 @@ ...@@ -3477,8 +3467,8 @@
;; We must use peep2 instead of a split because we need accurate life ;; We must use peep2 instead of a split because we need accurate life
;; information for $gp. Consider the case of { bar(); while (1); }. ;; information for $gp. Consider the case of { bar(); while (1); }.
(define_peephole2 (define_peephole2
[(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" "")) [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand"))
(match_operand 1 "" "")) (match_operand 1))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))])] (clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
...@@ -3508,8 +3498,8 @@ ...@@ -3508,8 +3498,8 @@
}) })
(define_peephole2 (define_peephole2
[(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" "")) [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand"))
(match_operand 1 "" "")) (match_operand 1))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))])] (clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
...@@ -3545,10 +3535,10 @@ ...@@ -3545,10 +3535,10 @@
(define_insn "*call_osf_2_er_nogp" (define_insn "*call_osf_2_er_nogp"
[(call (mem:DI (match_operand:DI 0 "register_operand" "c")) [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
(match_operand 1 "" "")) (match_operand 1))
(use (reg:DI 29)) (use (reg:DI 29))
(use (match_operand 2 "" "")) (use (match_operand 2))
(use (match_operand 3 "const_int_operand" "")) (use (match_operand 3 "const_int_operand"))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"jsr $26,(%0),%2%J3" "jsr $26,(%0),%2%J3"
...@@ -3556,12 +3546,12 @@ ...@@ -3556,12 +3546,12 @@
(define_insn "*call_osf_2_er" (define_insn "*call_osf_2_er"
[(call (mem:DI (match_operand:DI 0 "register_operand" "c")) [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
(match_operand 1 "" "")) (match_operand 1))
(set (reg:DI 29) (set (reg:DI 29)
(unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand" "")] (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")]
UNSPEC_LDGP1)) UNSPEC_LDGP1))
(use (match_operand 2 "" "")) (use (match_operand 2))
(use (match_operand 3 "const_int_operand" "")) (use (match_operand 3 "const_int_operand"))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4" "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4"
...@@ -3571,7 +3561,7 @@ ...@@ -3571,7 +3561,7 @@
(define_insn "*call_osf_1_noreturn" (define_insn "*call_osf_1_noreturn"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
(match_operand 1 "" "")) (match_operand 1))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
...@@ -3585,7 +3575,7 @@ ...@@ -3585,7 +3575,7 @@
(define_insn "*call_osf_1" (define_insn "*call_osf_1"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
(match_operand 1 "" "")) (match_operand 1))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
...@@ -3598,7 +3588,7 @@ ...@@ -3598,7 +3588,7 @@
(define_insn "*sibcall_osf_1_er" (define_insn "*sibcall_osf_1_er"
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
(match_operand 1 "" "")) (match_operand 1))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)] (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@ "@
...@@ -3611,7 +3601,7 @@ ...@@ -3611,7 +3601,7 @@
;; doesn't do what we want. ;; doesn't do what we want.
(define_insn "*sibcall_osf_1" (define_insn "*sibcall_osf_1"
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
(match_operand 1 "" "")) (match_operand 1))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)] (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@ "@
...@@ -3625,7 +3615,7 @@ ...@@ -3625,7 +3615,7 @@
; Please do not molest. ; Please do not molest.
(define_insn "*call_vms_1" (define_insn "*call_vms_1"
[(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
(match_operand 1 "" "")) (match_operand 1))
(use (match_operand:DI 2 "nonmemory_operand" "r,n")) (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
(use (reg:DI 25)) (use (reg:DI 25))
(use (reg:DI 26)) (use (reg:DI 26))
...@@ -3650,10 +3640,10 @@ ...@@ -3650,10 +3640,10 @@
;; Call subroutine returning any type. ;; Call subroutine returning any type.
(define_expand "untyped_call" (define_expand "untyped_call"
[(parallel [(call (match_operand 0 "" "") [(parallel [(call (match_operand 0)
(const_int 0)) (const_int 0))
(match_operand 1 "" "") (match_operand 1)
(match_operand 2 "" "")])] (match_operand 2)])]
"" ""
{ {
int i; int i;
...@@ -3687,15 +3677,14 @@ ...@@ -3687,15 +3677,14 @@
(define_insn "jump" (define_insn "jump"
[(set (pc) [(set (pc)
(label_ref (match_operand 0 "" "")))] (label_ref (match_operand 0)))]
"" ""
"br $31,%l0" "br $31,%l0"
[(set_attr "type" "ibr")]) [(set_attr "type" "ibr")])
(define_expand "return" (define_expand "return"
[(return)] [(return)]
"direct_return ()" "direct_return ()")
"")
(define_insn "*return_internal" (define_insn "*return_internal"
[(return)] [(return)]
...@@ -3711,8 +3700,8 @@ ...@@ -3711,8 +3700,8 @@
(define_expand "tablejump" (define_expand "tablejump"
[(parallel [(set (pc) [(parallel [(set (pc)
(match_operand 0 "register_operand" "")) (match_operand 0 "register_operand"))
(use (label_ref:DI (match_operand 1 "" "")))])] (use (label_ref:DI (match_operand 1)))])]
"" ""
{ {
if (TARGET_ABI_OSF) if (TARGET_ABI_OSF)
...@@ -3727,7 +3716,7 @@ ...@@ -3727,7 +3716,7 @@
(define_insn "*tablejump_internal" (define_insn "*tablejump_internal"
[(set (pc) [(set (pc)
(match_operand:DI 0 "register_operand" "r")) (match_operand:DI 0 "register_operand" "r"))
(use (label_ref (match_operand 1 "" "")))] (use (label_ref (match_operand 1)))]
"" ""
"jmp $31,(%0),0" "jmp $31,(%0),0"
[(set_attr "type" "ibr")]) [(set_attr "type" "ibr")])
...@@ -3741,8 +3730,8 @@ ...@@ -3741,8 +3730,8 @@
[(set_attr "type" "callpal")]) [(set_attr "type" "callpal")])
(define_expand "clear_cache" (define_expand "clear_cache"
[(match_operand:DI 0 "") ; region start [(match_operand:DI 0) ; region start
(match_operand:DI 1 "")] ; region end (match_operand:DI 1)] ; region end
"" ""
{ {
emit_insn (gen_imb ()); emit_insn (gen_imb ());
...@@ -3777,10 +3766,9 @@ ...@@ -3777,10 +3766,9 @@
;; not much point in creating an R16_REG register class. ;; not much point in creating an R16_REG register class.
(define_expand "set_thread_pointerdi" (define_expand "set_thread_pointerdi"
[(set (reg:DI 16) (match_operand:DI 0 "input_operand" "")) [(set (reg:DI 16) (match_operand:DI 0 "input_operand"))
(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
"TARGET_ABI_OSF" "TARGET_ABI_OSF")
"")
(define_insn "*set_tp" (define_insn "*set_tp"
[(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
...@@ -3796,8 +3784,8 @@ ...@@ -3796,8 +3784,8 @@
;; Special builtins for establishing and reverting VMS condition handlers. ;; Special builtins for establishing and reverting VMS condition handlers.
(define_expand "builtin_establish_vms_condition_handler" (define_expand "builtin_establish_vms_condition_handler"
[(set (reg:DI 0) (match_operand:DI 0 "register_operand" "")) [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))
(use (match_operand:DI 1 "address_operand" ""))] (use (match_operand:DI 1 "address_operand"))]
"TARGET_ABI_OPEN_VMS" "TARGET_ABI_OPEN_VMS"
{ {
alpha_expand_builtin_establish_vms_condition_handler (operands[0], alpha_expand_builtin_establish_vms_condition_handler (operands[0],
...@@ -3805,19 +3793,17 @@ ...@@ -3805,19 +3793,17 @@
}) })
(define_expand "builtin_revert_vms_condition_handler" (define_expand "builtin_revert_vms_condition_handler"
[(set (reg:DI 0) (match_operand:DI 0 "register_operand" ""))] [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))]
"TARGET_ABI_OPEN_VMS" "TARGET_ABI_OPEN_VMS"
{ "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);")
alpha_expand_builtin_revert_vms_condition_handler (operands[0]);
})
;; Finally, we have the basic data motion insns. The byte and word insns ;; Finally, we have the basic data motion insns. The byte and word insns
;; are done via define_expand. Start with the floating-point insns, since ;; are done via define_expand. Start with the floating-point insns, since
;; they are simpler. ;; they are simpler.
(define_expand "movsf" (define_expand "movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "") [(set (match_operand:SF 0 "nonimmediate_operand")
(match_operand:SF 1 "general_operand" ""))] (match_operand:SF 1 "general_operand"))]
"" ""
{ {
if (MEM_P (operands[0]) if (MEM_P (operands[0])
...@@ -3843,8 +3829,8 @@ ...@@ -3843,8 +3829,8 @@
(set_attr "isa" "*,*,*,*,*,*,fix,fix")]) (set_attr "isa" "*,*,*,*,*,*,fix,fix")])
(define_expand "movdf" (define_expand "movdf"
[(set (match_operand:DF 0 "nonimmediate_operand" "") [(set (match_operand:DF 0 "nonimmediate_operand")
(match_operand:DF 1 "general_operand" ""))] (match_operand:DF 1 "general_operand"))]
"" ""
{ {
if (MEM_P (operands[0]) if (MEM_P (operands[0])
...@@ -3874,8 +3860,8 @@ ...@@ -3874,8 +3860,8 @@
;; ??? Is this still true now that we have the lower-subreg pass? ;; ??? Is this still true now that we have the lower-subreg pass?
(define_expand "movtf" (define_expand "movtf"
[(set (match_operand:TF 0 "nonimmediate_operand" "") [(set (match_operand:TF 0 "nonimmediate_operand")
(match_operand:TF 1 "general_operand" ""))] (match_operand:TF 1 "general_operand"))]
"" ""
{ {
if (MEM_P (operands[0]) if (MEM_P (operands[0])
...@@ -3892,16 +3878,14 @@ ...@@ -3892,16 +3878,14 @@
"reload_completed" "reload_completed"
[(set (match_dup 0) (match_dup 2)) [(set (match_dup 0) (match_dup 2))
(set (match_dup 1) (match_dup 3))] (set (match_dup 1) (match_dup 3))]
{ "alpha_split_tmode_pair (operands, TFmode, true);")
alpha_split_tmode_pair (operands, TFmode, true);
})
;; We do two major things here: handle mem->mem and construct long ;; We do two major things here: handle mem->mem and construct long
;; constants. ;; constants.
(define_expand "movsi" (define_expand "movsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "") [(set (match_operand:SI 0 "nonimmediate_operand")
(match_operand:SI 1 "general_operand" ""))] (match_operand:SI 1 "general_operand"))]
"" ""
{ {
if (alpha_expand_mov (SImode, operands)) if (alpha_expand_mov (SImode, operands))
...@@ -3928,8 +3912,8 @@ ...@@ -3928,8 +3912,8 @@
;; sequence. ;; sequence.
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand")
(match_operand:SI 1 "non_add_const_operand" ""))] (match_operand:SI 1 "non_add_const_operand"))]
"" ""
[(const_int 0)] [(const_int 0)]
{ {
...@@ -3942,7 +3926,7 @@ ...@@ -3942,7 +3926,7 @@
(define_insn "*movdi_er_low_l" (define_insn "*movdi_er_low_l"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "local_symbolic_operand" "")))] (match_operand:DI 2 "local_symbolic_operand")))]
"TARGET_EXPLICIT_RELOCS" "TARGET_EXPLICIT_RELOCS"
{ {
if (true_regnum (operands[1]) == 29) if (true_regnum (operands[1]) == 29)
...@@ -3953,16 +3937,16 @@ ...@@ -3953,16 +3937,16 @@
[(set_attr "usegp" "yes")]) [(set_attr "usegp" "yes")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(match_operand:DI 1 "small_symbolic_operand" ""))] (match_operand:DI 1 "small_symbolic_operand"))]
"TARGET_EXPLICIT_RELOCS && reload_completed" "TARGET_EXPLICIT_RELOCS && reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(lo_sum:DI (match_dup 2) (match_dup 1)))] (lo_sum:DI (match_dup 2) (match_dup 1)))]
"operands[2] = pic_offset_table_rtx;") "operands[2] = pic_offset_table_rtx;")
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(match_operand:DI 1 "local_symbolic_operand" ""))] (match_operand:DI 1 "local_symbolic_operand"))]
"TARGET_EXPLICIT_RELOCS && reload_completed" "TARGET_EXPLICIT_RELOCS && reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(plus:DI (match_dup 2) (high:DI (match_dup 1)))) (plus:DI (match_dup 2) (high:DI (match_dup 1))))
...@@ -3971,7 +3955,7 @@ ...@@ -3971,7 +3955,7 @@
"operands[2] = pic_offset_table_rtx;") "operands[2] = pic_offset_table_rtx;")
(define_split (define_split
[(match_operand 0 "some_small_symbolic_operand" "")] [(match_operand 0 "some_small_symbolic_operand")]
"" ""
[(match_dup 0)] [(match_dup 0)]
"operands[0] = split_small_symbolic_operand (operands[0]);") "operands[0] = split_small_symbolic_operand (operands[0]);")
...@@ -3981,8 +3965,8 @@ ...@@ -3981,8 +3965,8 @@
(define_insn "movdi_er_high_g" (define_insn "movdi_er_high_g"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "") (match_operand:DI 2 "symbolic_operand")
(match_operand 3 "const_int_operand" "")] (match_operand 3 "const_int_operand")]
UNSPEC_LITERAL))] UNSPEC_LITERAL))]
"TARGET_EXPLICIT_RELOCS" "TARGET_EXPLICIT_RELOCS"
{ {
...@@ -3994,8 +3978,8 @@ ...@@ -3994,8 +3978,8 @@
[(set_attr "type" "ldsym")]) [(set_attr "type" "ldsym")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(match_operand:DI 1 "global_symbolic_operand" ""))] (match_operand:DI 1 "global_symbolic_operand"))]
"TARGET_EXPLICIT_RELOCS && reload_completed" "TARGET_EXPLICIT_RELOCS && reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(unspec:DI [(match_dup 2) (unspec:DI [(match_dup 2)
...@@ -4006,8 +3990,8 @@ ...@@ -4006,8 +3990,8 @@
(define_insn "movdi_er_tlsgd" (define_insn "movdi_er_tlsgd"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "") (match_operand:DI 2 "symbolic_operand")
(match_operand 3 "const_int_operand" "")] (match_operand 3 "const_int_operand")]
UNSPEC_TLSGD))] UNSPEC_TLSGD))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
{ {
...@@ -4020,7 +4004,7 @@ ...@@ -4020,7 +4004,7 @@
(define_insn "movdi_er_tlsldm" (define_insn "movdi_er_tlsldm"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "")] (match_operand 2 "const_int_operand")]
UNSPEC_TLSLDM))] UNSPEC_TLSLDM))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
{ {
...@@ -4033,7 +4017,7 @@ ...@@ -4033,7 +4017,7 @@
(define_insn "*movdi_er_gotdtp" (define_insn "*movdi_er_gotdtp"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "")] (match_operand:DI 2 "symbolic_operand")]
UNSPEC_DTPREL))] UNSPEC_DTPREL))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
"ldq %0,%2(%1)\t\t!gotdtprel" "ldq %0,%2(%1)\t\t!gotdtprel"
...@@ -4041,8 +4025,8 @@ ...@@ -4041,8 +4025,8 @@
(set_attr "usegp" "yes")]) (set_attr "usegp" "yes")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(match_operand:DI 1 "gotdtp_symbolic_operand" ""))] (match_operand:DI 1 "gotdtp_symbolic_operand"))]
"HAVE_AS_TLS && reload_completed" "HAVE_AS_TLS && reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(unspec:DI [(match_dup 2) (unspec:DI [(match_dup 2)
...@@ -4055,7 +4039,7 @@ ...@@ -4055,7 +4039,7 @@
(define_insn "*movdi_er_gottp" (define_insn "*movdi_er_gottp"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "")] (match_operand:DI 2 "symbolic_operand")]
UNSPEC_TPREL))] UNSPEC_TPREL))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
"ldq %0,%2(%1)\t\t!gottprel" "ldq %0,%2(%1)\t\t!gottprel"
...@@ -4063,8 +4047,8 @@ ...@@ -4063,8 +4047,8 @@
(set_attr "usegp" "yes")]) (set_attr "usegp" "yes")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(match_operand:DI 1 "gottp_symbolic_operand" ""))] (match_operand:DI 1 "gottp_symbolic_operand"))]
"HAVE_AS_TLS && reload_completed" "HAVE_AS_TLS && reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(unspec:DI [(match_dup 2) (unspec:DI [(match_dup 2)
...@@ -4116,8 +4100,8 @@ ...@@ -4116,8 +4100,8 @@
;; memory, and construct long 32-bit constants. ;; memory, and construct long 32-bit constants.
(define_expand "movdi" (define_expand "movdi"
[(set (match_operand:DI 0 "nonimmediate_operand" "") [(set (match_operand:DI 0 "nonimmediate_operand")
(match_operand:DI 1 "general_operand" ""))] (match_operand:DI 1 "general_operand"))]
"" ""
{ {
if (alpha_expand_mov (DImode, operands)) if (alpha_expand_mov (DImode, operands))
...@@ -4128,8 +4112,8 @@ ...@@ -4128,8 +4112,8 @@
;; sequence. ;; sequence.
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(match_operand:DI 1 "non_add_const_operand" ""))] (match_operand:DI 1 "non_add_const_operand"))]
"" ""
[(const_int 0)] [(const_int 0)]
{ {
...@@ -4155,13 +4139,11 @@ ...@@ -4155,13 +4139,11 @@
"reload_completed" "reload_completed"
[(set (match_dup 0) (match_dup 2)) [(set (match_dup 0) (match_dup 2))
(set (match_dup 1) (match_dup 3))] (set (match_dup 1) (match_dup 3))]
{ "alpha_split_tmode_pair (operands, TImode, true);")
alpha_split_tmode_pair (operands, TImode, true);
})
(define_expand "movti" (define_expand "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "") [(set (match_operand:TI 0 "nonimmediate_operand")
(match_operand:TI 1 "general_operand" ""))] (match_operand:TI 1 "general_operand"))]
"" ""
{ {
if (MEM_P (operands[0]) if (MEM_P (operands[0])
...@@ -4223,26 +4205,20 @@ ...@@ -4223,26 +4205,20 @@
;; same register. It is allowed to conflict with operand 1 as well. ;; same register. It is allowed to conflict with operand 1 as well.
(define_expand "aligned_loadqi" (define_expand "aligned_loadqi"
[(set (match_operand:SI 3 "register_operand" "") [(set (match_operand:SI 3 "register_operand")
(match_operand:SI 1 "memory_operand" "")) (match_operand:SI 1 "memory_operand"))
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand")
(zero_extract:DI (subreg:DI (match_dup 3) 0) (zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 8) (const_int 8)
(match_operand:DI 2 "const_int_operand" "")))] (match_operand:DI 2 "const_int_operand")))])
""
"")
(define_expand "aligned_loadhi" (define_expand "aligned_loadhi"
[(set (match_operand:SI 3 "register_operand" "") [(set (match_operand:SI 3 "register_operand")
(match_operand:SI 1 "memory_operand" "")) (match_operand:SI 1 "memory_operand"))
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand")
(zero_extract:DI (subreg:DI (match_dup 3) 0) (zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 16) (const_int 16)
(match_operand:DI 2 "const_int_operand" "")))] (match_operand:DI 2 "const_int_operand")))])
""
"")
;; Similar for unaligned loads, where we use the sequence from the ;; Similar for unaligned loads, where we use the sequence from the
;; Alpha Architecture manual. We have to distinguish between little-endian ;; Alpha Architecture manual. We have to distinguish between little-endian
...@@ -4252,30 +4228,26 @@ ...@@ -4252,30 +4228,26 @@
;; operand 3 can overlap the input and output registers. ;; operand 3 can overlap the input and output registers.
(define_expand "unaligned_loadqi" (define_expand "unaligned_loadqi"
[(set (match_operand:DI 2 "register_operand" "") [(set (match_operand:DI 2 "register_operand")
(mem:DI (and:DI (match_operand:DI 1 "address_operand" "") (mem:DI (and:DI (match_operand:DI 1 "address_operand")
(const_int -8)))) (const_int -8))))
(set (match_operand:DI 3 "register_operand" "") (set (match_operand:DI 3 "register_operand")
(match_dup 1)) (match_dup 1))
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand")
(zero_extract:DI (match_dup 2) (zero_extract:DI (match_dup 2)
(const_int 8) (const_int 8)
(ashift:DI (match_dup 3) (const_int 3))))] (ashift:DI (match_dup 3) (const_int 3))))])
""
"")
(define_expand "unaligned_loadhi" (define_expand "unaligned_loadhi"
[(set (match_operand:DI 2 "register_operand" "") [(set (match_operand:DI 2 "register_operand")
(mem:DI (and:DI (match_operand:DI 1 "address_operand" "") (mem:DI (and:DI (match_operand:DI 1 "address_operand")
(const_int -8)))) (const_int -8))))
(set (match_operand:DI 3 "register_operand" "") (set (match_operand:DI 3 "register_operand")
(match_dup 1)) (match_dup 1))
(set (match_operand:DI 0 "register_operand" "") (set (match_operand:DI 0 "register_operand")
(zero_extract:DI (match_dup 2) (zero_extract:DI (match_dup 2)
(const_int 16) (const_int 16)
(ashift:DI (match_dup 3) (const_int 3))))] (ashift:DI (match_dup 3) (const_int 3))))])
""
"")
;; Storing an aligned byte or word requires two temporaries. Operand 0 is the ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
;; aligned SImode MEM. Operand 1 is the register containing the ;; aligned SImode MEM. Operand 1 is the register containing the
...@@ -4283,13 +4255,13 @@ ...@@ -4283,13 +4255,13 @@
;; the value should be placed. Operands 3 and 4 are SImode temporaries. ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
(define_expand "aligned_store" (define_expand "aligned_store"
[(set (match_operand:SI 3 "register_operand" "") [(set (match_operand:SI 3 "register_operand")
(match_operand:SI 0 "memory_operand" "")) (match_operand:SI 0 "memory_operand"))
(set (subreg:DI (match_dup 3) 0) (set (subreg:DI (match_dup 3) 0)
(and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
(set (subreg:DI (match_operand:SI 4 "register_operand" "") 0) (set (subreg:DI (match_operand:SI 4 "register_operand") 0)
(ashift:DI (zero_extend:DI (match_operand 1 "register_operand" "")) (ashift:DI (zero_extend:DI (match_operand 1 "register_operand"))
(match_operand:DI 2 "const_int_operand" ""))) (match_operand:DI 2 "const_int_operand")))
(set (subreg:DI (match_dup 4) 0) (set (subreg:DI (match_dup 4) 0)
(ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
(set (match_dup 0) (match_dup 4))] (set (match_dup 0) (match_dup 4))]
...@@ -4307,18 +4279,18 @@ ...@@ -4307,18 +4279,18 @@
;; operand 2 can be that register. ;; operand 2 can be that register.
(define_expand "unaligned_store<mode>" (define_expand "unaligned_store<mode>"
[(set (match_operand:DI 3 "register_operand" "") [(set (match_operand:DI 3 "register_operand")
(mem:DI (and:DI (match_operand:DI 0 "address_operand" "") (mem:DI (and:DI (match_operand:DI 0 "address_operand")
(const_int -8)))) (const_int -8))))
(set (match_operand:DI 2 "register_operand" "") (set (match_operand:DI 2 "register_operand")
(match_dup 0)) (match_dup 0))
(set (match_dup 3) (set (match_dup 3)
(and:DI (not:DI (ashift:DI (match_dup 5) (and:DI (not:DI (ashift:DI (match_dup 5)
(ashift:DI (match_dup 2) (const_int 3)))) (ashift:DI (match_dup 2) (const_int 3))))
(match_dup 3))) (match_dup 3)))
(set (match_operand:DI 4 "register_operand" "") (set (match_operand:DI 4 "register_operand")
(ashift:DI (zero_extend:DI (ashift:DI (zero_extend:DI
(match_operand:I12MODE 1 "register_operand" "")) (match_operand:I12MODE 1 "register_operand"))
(ashift:DI (match_dup 2) (const_int 3)))) (ashift:DI (match_dup 2) (const_int 3))))
(set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
(set (mem:DI (and:DI (match_dup 0) (const_int -8))) (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
...@@ -4331,8 +4303,8 @@ ...@@ -4331,8 +4303,8 @@
;; registers for reload. ;; registers for reload.
(define_expand "mov<mode>" (define_expand "mov<mode>"
[(set (match_operand:I12MODE 0 "nonimmediate_operand" "") [(set (match_operand:I12MODE 0 "nonimmediate_operand")
(match_operand:I12MODE 1 "general_operand" ""))] (match_operand:I12MODE 1 "general_operand"))]
"" ""
{ {
if (TARGET_BWX if (TARGET_BWX
...@@ -4370,8 +4342,8 @@ ...@@ -4370,8 +4342,8 @@
;; We need to hook into the extra support that we have for HImode ;; We need to hook into the extra support that we have for HImode
;; reloads when BWX insns are not available. ;; reloads when BWX insns are not available.
(define_expand "movcqi" (define_expand "movcqi"
[(set (match_operand:CQI 0 "nonimmediate_operand" "") [(set (match_operand:CQI 0 "nonimmediate_operand")
(match_operand:CQI 1 "general_operand" ""))] (match_operand:CQI 1 "general_operand"))]
"!TARGET_BWX" "!TARGET_BWX"
{ {
if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT) if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT)
...@@ -4530,8 +4502,8 @@ ...@@ -4530,8 +4502,8 @@
(define_mode_iterator VEC12 [V8QI V4HI]) (define_mode_iterator VEC12 [V8QI V4HI])
(define_expand "mov<mode>" (define_expand "mov<mode>"
[(set (match_operand:VEC 0 "nonimmediate_operand" "") [(set (match_operand:VEC 0 "nonimmediate_operand")
(match_operand:VEC 1 "general_operand" ""))] (match_operand:VEC 1 "general_operand"))]
"" ""
{ {
if (alpha_expand_mov (<MODE>mode, operands)) if (alpha_expand_mov (<MODE>mode, operands))
...@@ -4539,8 +4511,8 @@ ...@@ -4539,8 +4511,8 @@
}) })
(define_split (define_split
[(set (match_operand:VEC 0 "register_operand" "") [(set (match_operand:VEC 0 "register_operand")
(match_operand:VEC 1 "non_zero_const_operand" ""))] (match_operand:VEC 1 "non_zero_const_operand"))]
"" ""
[(const_int 0)] [(const_int 0)]
{ {
...@@ -4552,8 +4524,8 @@ ...@@ -4552,8 +4524,8 @@
(define_expand "movmisalign<mode>" (define_expand "movmisalign<mode>"
[(set (match_operand:VEC 0 "nonimmediate_operand" "") [(set (match_operand:VEC 0 "nonimmediate_operand")
(match_operand:VEC 1 "general_operand" ""))] (match_operand:VEC 1 "general_operand"))]
"" ""
{ {
alpha_expand_movmisalign (<MODE>mode, operands); alpha_expand_movmisalign (<MODE>mode, operands);
...@@ -4643,9 +4615,9 @@ ...@@ -4643,9 +4615,9 @@
[(set_attr "type" "ilog")]) [(set_attr "type" "ilog")])
(define_expand "vec_shl_<mode>" (define_expand "vec_shl_<mode>"
[(set (match_operand:VEC 0 "register_operand" "") [(set (match_operand:VEC 0 "register_operand")
(ashift:DI (match_operand:VEC 1 "register_operand" "") (ashift:DI (match_operand:VEC 1 "register_operand")
(match_operand:DI 2 "reg_or_6bit_operand" "")))] (match_operand:DI 2 "reg_or_6bit_operand")))]
"" ""
{ {
operands[0] = gen_lowpart (DImode, operands[0]); operands[0] = gen_lowpart (DImode, operands[0]);
...@@ -4653,9 +4625,9 @@ ...@@ -4653,9 +4625,9 @@
}) })
(define_expand "vec_shr_<mode>" (define_expand "vec_shr_<mode>"
[(set (match_operand:VEC 0 "register_operand" "") [(set (match_operand:VEC 0 "register_operand")
(lshiftrt:DI (match_operand:VEC 1 "register_operand" "") (lshiftrt:DI (match_operand:VEC 1 "register_operand")
(match_operand:DI 2 "reg_or_6bit_operand" "")))] (match_operand:DI 2 "reg_or_6bit_operand")))]
"" ""
{ {
operands[0] = gen_lowpart (DImode, operands[0]); operands[0] = gen_lowpart (DImode, operands[0]);
...@@ -4665,10 +4637,10 @@ ...@@ -4665,10 +4637,10 @@
;; Bit field extract patterns which use ext[wlq][lh] ;; Bit field extract patterns which use ext[wlq][lh]
(define_expand "extv" (define_expand "extv"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(sign_extract:DI (match_operand:QI 1 "memory_operand" "") (sign_extract:DI (match_operand:QI 1 "memory_operand")
(match_operand:DI 2 "immediate_operand" "") (match_operand:DI 2 "immediate_operand")
(match_operand:DI 3 "immediate_operand" "")))] (match_operand:DI 3 "immediate_operand")))]
"" ""
{ {
int ofs; int ofs;
...@@ -4695,10 +4667,10 @@ ...@@ -4695,10 +4667,10 @@
}) })
(define_expand "extzv" (define_expand "extzv"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "") (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand")
(match_operand:DI 2 "immediate_operand" "") (match_operand:DI 2 "immediate_operand")
(match_operand:DI 3 "immediate_operand" "")))] (match_operand:DI 3 "immediate_operand")))]
"" ""
{ {
/* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
...@@ -4728,10 +4700,10 @@ ...@@ -4728,10 +4700,10 @@
}) })
(define_expand "insv" (define_expand "insv"
[(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "") [(set (zero_extract:DI (match_operand:QI 0 "memory_operand")
(match_operand:DI 1 "immediate_operand" "") (match_operand:DI 1 "immediate_operand")
(match_operand:DI 2 "immediate_operand" "")) (match_operand:DI 2 "immediate_operand"))
(match_operand:DI 3 "register_operand" ""))] (match_operand:DI 3 "register_operand"))]
"" ""
{ {
int ofs; int ofs;
...@@ -4763,10 +4735,10 @@ ...@@ -4763,10 +4735,10 @@
;; Argument 3 is the alignment ;; Argument 3 is the alignment
(define_expand "movmemqi" (define_expand "movmemqi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "") [(parallel [(set (match_operand:BLK 0 "memory_operand")
(match_operand:BLK 1 "memory_operand" "")) (match_operand:BLK 1 "memory_operand"))
(use (match_operand:DI 2 "immediate_operand" "")) (use (match_operand:DI 2 "immediate_operand"))
(use (match_operand:DI 3 "immediate_operand" ""))])] (use (match_operand:DI 3 "immediate_operand"))])]
"" ""
{ {
if (alpha_expand_block_move (operands)) if (alpha_expand_block_move (operands))
...@@ -4776,10 +4748,10 @@ ...@@ -4776,10 +4748,10 @@
}) })
(define_expand "movmemdi" (define_expand "movmemdi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "") [(parallel [(set (match_operand:BLK 0 "memory_operand")
(match_operand:BLK 1 "memory_operand" "")) (match_operand:BLK 1 "memory_operand"))
(use (match_operand:DI 2 "immediate_operand" "")) (use (match_operand:DI 2 "immediate_operand"))
(use (match_operand:DI 3 "immediate_operand" "")) (use (match_operand:DI 3 "immediate_operand"))
(use (match_dup 4)) (use (match_dup 4))
(clobber (reg:DI 25)) (clobber (reg:DI 25))
(clobber (reg:DI 16)) (clobber (reg:DI 16))
...@@ -4790,15 +4762,13 @@ ...@@ -4790,15 +4762,13 @@
(clobber (reg:DI 26)) (clobber (reg:DI 26))
(clobber (reg:DI 27))])] (clobber (reg:DI 27))])]
"TARGET_ABI_OPEN_VMS" "TARGET_ABI_OPEN_VMS"
{ "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");")
operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
})
(define_insn "*movmemdi_1" (define_insn "*movmemdi_1"
[(set (match_operand:BLK 0 "memory_operand" "=m,=m") [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
(match_operand:BLK 1 "memory_operand" "m,m")) (match_operand:BLK 1 "memory_operand" "m,m"))
(use (match_operand:DI 2 "nonmemory_operand" "r,i")) (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
(use (match_operand:DI 3 "immediate_operand" "")) (use (match_operand:DI 3 "immediate_operand"))
(use (match_operand:DI 4 "call_operand" "i,i")) (use (match_operand:DI 4 "call_operand" "i,i"))
(clobber (reg:DI 25)) (clobber (reg:DI 25))
(clobber (reg:DI 16)) (clobber (reg:DI 16))
...@@ -4825,10 +4795,10 @@ ...@@ -4825,10 +4795,10 @@
(set_attr "length" "28")]) (set_attr "length" "28")])
(define_expand "setmemqi" (define_expand "setmemqi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "") [(parallel [(set (match_operand:BLK 0 "memory_operand")
(match_operand 2 "const_int_operand" "")) (match_operand 2 "const_int_operand"))
(use (match_operand:DI 1 "immediate_operand" "")) (use (match_operand:DI 1 "immediate_operand"))
(use (match_operand:DI 3 "immediate_operand" ""))])] (use (match_operand:DI 3 "immediate_operand"))])]
"" ""
{ {
/* If value to set is not zero, use the library routine. */ /* If value to set is not zero, use the library routine. */
...@@ -4842,10 +4812,10 @@ ...@@ -4842,10 +4812,10 @@
}) })
(define_expand "setmemdi" (define_expand "setmemdi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "") [(parallel [(set (match_operand:BLK 0 "memory_operand")
(match_operand 2 "const_int_operand" "")) (match_operand 2 "const_int_operand"))
(use (match_operand:DI 1 "immediate_operand" "")) (use (match_operand:DI 1 "immediate_operand"))
(use (match_operand:DI 3 "immediate_operand" "")) (use (match_operand:DI 3 "immediate_operand"))
(use (match_dup 4)) (use (match_dup 4))
(clobber (reg:DI 25)) (clobber (reg:DI 25))
(clobber (reg:DI 16)) (clobber (reg:DI 16))
...@@ -4865,7 +4835,7 @@ ...@@ -4865,7 +4835,7 @@
[(set (match_operand:BLK 0 "memory_operand" "=m,=m") [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
(const_int 0)) (const_int 0))
(use (match_operand:DI 1 "nonmemory_operand" "r,i")) (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
(use (match_operand:DI 2 "immediate_operand" "")) (use (match_operand:DI 2 "immediate_operand"))
(use (match_operand:DI 3 "call_operand" "i,i")) (use (match_operand:DI 3 "call_operand" "i,i"))
(clobber (reg:DI 25)) (clobber (reg:DI 25))
(clobber (reg:DI 16)) (clobber (reg:DI 16))
...@@ -4891,7 +4861,7 @@ ...@@ -4891,7 +4861,7 @@
;; Subroutine of stack space allocation. Perform a stack probe. ;; Subroutine of stack space allocation. Perform a stack probe.
(define_expand "probe_stack" (define_expand "probe_stack"
[(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))] [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))]
"" ""
{ {
operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx, operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx,
...@@ -4910,7 +4880,7 @@ ...@@ -4910,7 +4880,7 @@
(define_expand "allocate_stack" (define_expand "allocate_stack"
[(set (reg:DI 30) [(set (reg:DI 30)
(plus:DI (reg:DI 30) (plus:DI (reg:DI 30)
(match_operand:DI 1 "reg_or_cint_operand" ""))) (match_operand:DI 1 "reg_or_cint_operand")))
(set (match_operand:DI 0 "register_operand" "=r") (set (match_operand:DI 0 "register_operand" "=r")
(match_dup 2))] (match_dup 2))]
"" ""
...@@ -4998,7 +4968,7 @@ ...@@ -4998,7 +4968,7 @@
(set_attr "type" "multi")]) (set_attr "type" "multi")])
(define_expand "prologue" (define_expand "prologue"
[(clobber (const_int 0))] [(const_int 0)]
"" ""
{ {
alpha_expand_prologue (); alpha_expand_prologue ();
...@@ -5029,7 +4999,7 @@ ...@@ -5029,7 +4999,7 @@
(define_insn "*ldgp_er_1" (define_insn "*ldgp_er_1"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "")] (match_operand 2 "const_int_operand")]
UNSPECV_LDGP1))] UNSPECV_LDGP1))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"ldah %0,0(%1)\t\t!gpdisp!%2" "ldah %0,0(%1)\t\t!gpdisp!%2"
...@@ -5038,7 +5008,7 @@ ...@@ -5038,7 +5008,7 @@
(define_insn "*ldgp_er_2" (define_insn "*ldgp_er_2"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "")] (match_operand 2 "const_int_operand")]
UNSPEC_LDGP2))] UNSPEC_LDGP2))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"lda %0,0(%1)\t\t!gpdisp!%2" "lda %0,0(%1)\t\t!gpdisp!%2"
...@@ -5047,7 +5017,7 @@ ...@@ -5047,7 +5017,7 @@
(define_insn "*prologue_ldgp_er_2" (define_insn "*prologue_ldgp_er_2"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "")] (match_operand 2 "const_int_operand")]
UNSPECV_PLDGP2))] UNSPECV_PLDGP2))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:" "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
...@@ -5056,7 +5026,7 @@ ...@@ -5056,7 +5026,7 @@
(define_insn "*prologue_ldgp_1" (define_insn "*prologue_ldgp_1"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "")] (match_operand 2 "const_int_operand")]
UNSPECV_LDGP1))] UNSPECV_LDGP1))]
"" ""
"ldgp %0,0(%1)\n$%~..ng:" "ldgp %0,0(%1)\n$%~..ng:"
...@@ -5065,10 +5035,10 @@ ...@@ -5065,10 +5035,10 @@
(define_insn "*prologue_ldgp_2" (define_insn "*prologue_ldgp_2"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "")] (match_operand 2 "const_int_operand")]
UNSPECV_PLDGP2))] UNSPECV_PLDGP2))]
"" ""
"") )
;; The _mcount profiling hook has special calling conventions, and ;; The _mcount profiling hook has special calling conventions, and
;; does not clobber all the registers that a normal call would. So ;; does not clobber all the registers that a normal call would. So
...@@ -5098,9 +5068,7 @@ ...@@ -5098,9 +5068,7 @@
(define_expand "epilogue" (define_expand "epilogue"
[(return)] [(return)]
"" ""
{ "alpha_expand_epilogue ();")
alpha_expand_epilogue ();
})
(define_expand "sibcall_epilogue" (define_expand "sibcall_epilogue"
[(return)] [(return)]
...@@ -5146,12 +5114,11 @@ ...@@ -5146,12 +5114,11 @@
[(set_attr "type" "ibr")]) [(set_attr "type" "ibr")])
(define_expand "builtin_setjmp_receiver" (define_expand "builtin_setjmp_receiver"
[(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)] [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)]
"TARGET_ABI_OSF" "TARGET_ABI_OSF")
"")
(define_insn_and_split "*builtin_setjmp_receiver_1" (define_insn_and_split "*builtin_setjmp_receiver_1"
[(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)] [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)]
"TARGET_ABI_OSF" "TARGET_ABI_OSF"
{ {
if (TARGET_EXPLICIT_RELOCS) if (TARGET_EXPLICIT_RELOCS)
...@@ -5176,7 +5143,7 @@ ...@@ -5176,7 +5143,7 @@
(set_attr "type" "multi")]) (set_attr "type" "multi")])
(define_insn "*builtin_setjmp_receiver_er_sl_1" (define_insn "*builtin_setjmp_receiver_er_sl_1"
[(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)] [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)]
"TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS" "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
"lda $27,$LSJ%=-%l0($27)\n$LSJ%=:") "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
...@@ -5230,8 +5197,7 @@ ...@@ -5230,8 +5197,7 @@
(set (reg:DI 27) (mem:DI (reg:DI 29))) (set (reg:DI 27) (mem:DI (reg:DI 29)))
(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
(use (reg:DI 27))] (use (reg:DI 27))]
"TARGET_ABI_OPEN_VMS" "TARGET_ABI_OPEN_VMS")
"")
(define_insn "arg_home" (define_insn "arg_home"
[(unspec [(const_int 0)] UNSPEC_ARG_HOME) [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
...@@ -5346,9 +5312,9 @@ ...@@ -5346,9 +5312,9 @@
[(set_attr "type" "icmp")]) [(set_attr "type" "icmp")])
(define_expand "extbl" (define_expand "extbl"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2])); emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2]));
...@@ -5356,9 +5322,9 @@ ...@@ -5356,9 +5322,9 @@
}) })
(define_expand "extwl" (define_expand "extwl"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2])); emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2]));
...@@ -5366,9 +5332,9 @@ ...@@ -5366,9 +5332,9 @@
}) })
(define_expand "extll" (define_expand "extll"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2])); emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2]));
...@@ -5376,9 +5342,9 @@ ...@@ -5376,9 +5342,9 @@
}) })
(define_expand "extql" (define_expand "extql"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2])); emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2]));
...@@ -5386,9 +5352,9 @@ ...@@ -5386,9 +5352,9 @@
}) })
(define_expand "builtin_insbl" (define_expand "builtin_insbl"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
operands[1] = gen_lowpart (QImode, operands[1]); operands[1] = gen_lowpart (QImode, operands[1]);
...@@ -5397,9 +5363,9 @@ ...@@ -5397,9 +5363,9 @@
}) })
(define_expand "builtin_inswl" (define_expand "builtin_inswl"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
operands[1] = gen_lowpart (HImode, operands[1]); operands[1] = gen_lowpart (HImode, operands[1]);
...@@ -5408,9 +5374,9 @@ ...@@ -5408,9 +5374,9 @@
}) })
(define_expand "builtin_insll" (define_expand "builtin_insll"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
operands[1] = gen_lowpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]);
...@@ -5419,9 +5385,9 @@ ...@@ -5419,9 +5385,9 @@
}) })
(define_expand "inswh" (define_expand "inswh"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
...@@ -5429,9 +5395,9 @@ ...@@ -5429,9 +5395,9 @@
}) })
(define_expand "inslh" (define_expand "inslh"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
...@@ -5439,9 +5405,9 @@ ...@@ -5439,9 +5405,9 @@
}) })
(define_expand "insqh" (define_expand "insqh"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
...@@ -5449,9 +5415,9 @@ ...@@ -5449,9 +5415,9 @@
}) })
(define_expand "mskbl" (define_expand "mskbl"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
rtx mask = GEN_INT (0xff); rtx mask = GEN_INT (0xff);
...@@ -5460,9 +5426,9 @@ ...@@ -5460,9 +5426,9 @@
}) })
(define_expand "mskwl" (define_expand "mskwl"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
rtx mask = GEN_INT (0xffff); rtx mask = GEN_INT (0xffff);
...@@ -5471,9 +5437,9 @@ ...@@ -5471,9 +5437,9 @@
}) })
(define_expand "mskll" (define_expand "mskll"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
rtx mask = immed_double_const (0xffffffff, 0, DImode); rtx mask = immed_double_const (0xffffffff, 0, DImode);
...@@ -5482,9 +5448,9 @@ ...@@ -5482,9 +5448,9 @@
}) })
(define_expand "mskql" (define_expand "mskql"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
rtx mask = constm1_rtx; rtx mask = constm1_rtx;
...@@ -5493,9 +5459,9 @@ ...@@ -5493,9 +5459,9 @@
}) })
(define_expand "mskwh" (define_expand "mskwh"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
...@@ -5503,9 +5469,9 @@ ...@@ -5503,9 +5469,9 @@
}) })
(define_expand "msklh" (define_expand "msklh"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
...@@ -5513,9 +5479,9 @@ ...@@ -5513,9 +5479,9 @@
}) })
(define_expand "mskqh" (define_expand "mskqh"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "") (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "reg_or_8bit_operand" "")] (match_operand:DI 2 "reg_or_8bit_operand")]
"" ""
{ {
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
...@@ -5523,11 +5489,11 @@ ...@@ -5523,11 +5489,11 @@
}) })
(define_expand "builtin_zap" (define_expand "builtin_zap"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(and:DI (unspec:DI (and:DI (unspec:DI
[(match_operand:DI 2 "reg_or_cint_operand" "")] [(match_operand:DI 2 "reg_or_cint_operand")]
UNSPEC_ZAP) UNSPEC_ZAP)
(match_operand:DI 1 "reg_or_cint_operand" "")))] (match_operand:DI 1 "reg_or_cint_operand")))]
"" ""
{ {
if (CONST_INT_P (operands[2])) if (CONST_INT_P (operands[2]))
...@@ -5569,11 +5535,11 @@ ...@@ -5569,11 +5535,11 @@
[(set_attr "type" "shift,shift,ilog,shift")]) [(set_attr "type" "shift,shift,ilog,shift")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(and:DI (unspec:DI (and:DI (unspec:DI
[(match_operand:QI 2 "const_int_operand" "")] [(match_operand:QI 2 "const_int_operand")]
UNSPEC_ZAP) UNSPEC_ZAP)
(match_operand:DI 1 "const_int_operand" "")))] (match_operand:DI 1 "const_int_operand")))]
"" ""
[(const_int 0)] [(const_int 0)]
{ {
...@@ -5593,11 +5559,11 @@ ...@@ -5593,11 +5559,11 @@
}) })
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(and:DI (unspec:DI (and:DI (unspec:DI
[(match_operand:QI 2 "const_int_operand" "")] [(match_operand:QI 2 "const_int_operand")]
UNSPEC_ZAP) UNSPEC_ZAP)
(match_operand:DI 1 "register_operand" "")))] (match_operand:DI 1 "register_operand")))]
"" ""
[(set (match_dup 0) [(set (match_dup 0)
(and:DI (match_dup 1) (match_dup 2)))] (and:DI (match_dup 1) (match_dup 2)))]
...@@ -5616,11 +5582,11 @@ ...@@ -5616,11 +5582,11 @@
}) })
(define_expand "builtin_zapnot" (define_expand "builtin_zapnot"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(and:DI (unspec:DI (and:DI (unspec:DI
[(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))] [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))]
UNSPEC_ZAP) UNSPEC_ZAP)
(match_operand:DI 1 "reg_or_cint_operand" "")))] (match_operand:DI 1 "reg_or_cint_operand")))]
"" ""
{ {
if (CONST_INT_P (operands[2])) if (CONST_INT_P (operands[2]))
...@@ -5680,9 +5646,9 @@ ...@@ -5680,9 +5646,9 @@
[(set_attr "type" "ilog")]) [(set_attr "type" "ilog")])
(define_expand "builtin_minub8" (define_expand "builtin_minub8"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_0_operand" "")] (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX" "TARGET_MAX"
{ {
alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
...@@ -5691,9 +5657,9 @@ ...@@ -5691,9 +5657,9 @@
}) })
(define_expand "builtin_minsb8" (define_expand "builtin_minsb8"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_0_operand" "")] (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX" "TARGET_MAX"
{ {
alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
...@@ -5702,9 +5668,9 @@ ...@@ -5702,9 +5668,9 @@
}) })
(define_expand "builtin_minuw4" (define_expand "builtin_minuw4"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_0_operand" "")] (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX" "TARGET_MAX"
{ {
alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
...@@ -5713,9 +5679,9 @@ ...@@ -5713,9 +5679,9 @@
}) })
(define_expand "builtin_minsw4" (define_expand "builtin_minsw4"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_0_operand" "")] (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX" "TARGET_MAX"
{ {
alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
...@@ -5724,9 +5690,9 @@ ...@@ -5724,9 +5690,9 @@
}) })
(define_expand "builtin_maxub8" (define_expand "builtin_maxub8"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_0_operand" "")] (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX" "TARGET_MAX"
{ {
alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
...@@ -5735,9 +5701,9 @@ ...@@ -5735,9 +5701,9 @@
}) })
(define_expand "builtin_maxsb8" (define_expand "builtin_maxsb8"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_0_operand" "")] (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX" "TARGET_MAX"
{ {
alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
...@@ -5746,9 +5712,9 @@ ...@@ -5746,9 +5712,9 @@
}) })
(define_expand "builtin_maxuw4" (define_expand "builtin_maxuw4"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_0_operand" "")] (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX" "TARGET_MAX"
{ {
alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
...@@ -5757,9 +5723,9 @@ ...@@ -5757,9 +5723,9 @@
}) })
(define_expand "builtin_maxsw4" (define_expand "builtin_maxsw4"
[(match_operand:DI 0 "register_operand" "") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_0_operand")
(match_operand:DI 2 "reg_or_0_operand" "")] (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX" "TARGET_MAX"
{ {
alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
...@@ -5777,10 +5743,10 @@ ...@@ -5777,10 +5743,10 @@
[(set_attr "type" "mvi")]) [(set_attr "type" "mvi")])
(define_expand "builtin_pklb" (define_expand "builtin_pklb"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(vec_concat:V8QI (vec_concat:V8QI
(vec_concat:V4QI (vec_concat:V4QI
(truncate:V2QI (match_operand:DI 1 "register_operand" "")) (truncate:V2QI (match_operand:DI 1 "register_operand"))
(match_dup 2)) (match_dup 2))
(match_dup 3)))] (match_dup 3)))]
"TARGET_MAX" "TARGET_MAX"
...@@ -5796,16 +5762,16 @@ ...@@ -5796,16 +5762,16 @@
(vec_concat:V8QI (vec_concat:V8QI
(vec_concat:V4QI (vec_concat:V4QI
(truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
(match_operand:V2QI 2 "const0_operand" "")) (match_operand:V2QI 2 "const0_operand"))
(match_operand:V4QI 3 "const0_operand" "")))] (match_operand:V4QI 3 "const0_operand")))]
"TARGET_MAX" "TARGET_MAX"
"pklb %r1,%0" "pklb %r1,%0"
[(set_attr "type" "mvi")]) [(set_attr "type" "mvi")])
(define_expand "builtin_pkwb" (define_expand "builtin_pkwb"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(vec_concat:V8QI (vec_concat:V8QI
(truncate:V4QI (match_operand:DI 1 "register_operand" "")) (truncate:V4QI (match_operand:DI 1 "register_operand"))
(match_dup 2)))] (match_dup 2)))]
"TARGET_MAX" "TARGET_MAX"
{ {
...@@ -5818,15 +5784,15 @@ ...@@ -5818,15 +5784,15 @@
[(set (match_operand:V8QI 0 "register_operand" "=r") [(set (match_operand:V8QI 0 "register_operand" "=r")
(vec_concat:V8QI (vec_concat:V8QI
(truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
(match_operand:V4QI 2 "const0_operand" "")))] (match_operand:V4QI 2 "const0_operand")))]
"TARGET_MAX" "TARGET_MAX"
"pkwb %r1,%0" "pkwb %r1,%0"
[(set_attr "type" "mvi")]) [(set_attr "type" "mvi")])
(define_expand "builtin_unpkbl" (define_expand "builtin_unpkbl"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(zero_extend:V2SI (zero_extend:V2SI
(vec_select:V2QI (match_operand:DI 1 "register_operand" "") (vec_select:V2QI (match_operand:DI 1 "register_operand")
(parallel [(const_int 0) (const_int 1)]))))] (parallel [(const_int 0) (const_int 1)]))))]
"TARGET_MAX" "TARGET_MAX"
{ {
...@@ -5844,9 +5810,9 @@ ...@@ -5844,9 +5810,9 @@
[(set_attr "type" "mvi")]) [(set_attr "type" "mvi")])
(define_expand "builtin_unpkbw" (define_expand "builtin_unpkbw"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand")
(zero_extend:V4HI (zero_extend:V4HI
(vec_select:V4QI (match_operand:DI 1 "register_operand" "") (vec_select:V4QI (match_operand:DI 1 "register_operand")
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 1) (const_int 1)
(const_int 2) (const_int 2)
...@@ -5875,9 +5841,9 @@ ...@@ -5875,9 +5841,9 @@
;; wildcard operand0 interferes with nice recognition. ;; wildcard operand0 interferes with nice recognition.
(define_insn "*call_value_osf_1_er_noreturn" (define_insn "*call_value_osf_1_er_noreturn"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
(match_operand 2 "" ""))) (match_operand 2)))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
...@@ -5890,9 +5856,9 @@ ...@@ -5890,9 +5856,9 @@
(set_attr "length" "*,*,8")]) (set_attr "length" "*,*,8")])
(define_insn "*call_value_osf_1_er" (define_insn "*call_value_osf_1_er"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
(match_operand 2 "" ""))) (match_operand 2)))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
...@@ -5906,9 +5872,9 @@ ...@@ -5906,9 +5872,9 @@
;; We must use peep2 instead of a split because we need accurate life ;; We must use peep2 instead of a split because we need accurate life
;; information for $gp. Consider the case of { bar(); while (1); }. ;; information for $gp. Consider the case of { bar(); while (1); }.
(define_peephole2 (define_peephole2
[(parallel [(set (match_operand 0 "" "") [(parallel [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "")) (call (mem:DI (match_operand:DI 1 "call_operand"))
(match_operand 2 "" ""))) (match_operand 2)))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))])] (clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
...@@ -5939,9 +5905,9 @@ ...@@ -5939,9 +5905,9 @@
}) })
(define_peephole2 (define_peephole2
[(parallel [(set (match_operand 0 "" "") [(parallel [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "")) (call (mem:DI (match_operand:DI 1 "call_operand"))
(match_operand 2 "" ""))) (match_operand 2)))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))])] (clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
...@@ -5977,26 +5943,26 @@ ...@@ -5977,26 +5943,26 @@
}) })
(define_insn "*call_value_osf_2_er_nogp" (define_insn "*call_value_osf_2_er_nogp"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "register_operand" "c")) (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
(match_operand 2 "" ""))) (match_operand 2)))
(use (reg:DI 29)) (use (reg:DI 29))
(use (match_operand 3 "" "")) (use (match_operand 3))
(use (match_operand 4 "" "")) (use (match_operand 4))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"jsr $26,(%1),%3%J4" "jsr $26,(%1),%3%J4"
[(set_attr "type" "jsr")]) [(set_attr "type" "jsr")])
(define_insn "*call_value_osf_2_er" (define_insn "*call_value_osf_2_er"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "register_operand" "c")) (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
(match_operand 2 "" ""))) (match_operand 2)))
(set (reg:DI 29) (set (reg:DI 29)
(unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand" "")] (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")]
UNSPEC_LDGP1)) UNSPEC_LDGP1))
(use (match_operand 3 "" "")) (use (match_operand 3))
(use (match_operand 4 "" "")) (use (match_operand 4))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5" "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5"
...@@ -6005,9 +5971,9 @@ ...@@ -6005,9 +5971,9 @@
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "*call_value_osf_1_noreturn" (define_insn "*call_value_osf_1_noreturn"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
(match_operand 2 "" ""))) (match_operand 2)))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
...@@ -6020,10 +5986,10 @@ ...@@ -6020,10 +5986,10 @@
(set_attr "length" "*,*,8")]) (set_attr "length" "*,*,8")])
(define_insn_and_split "call_value_osf_tlsgd" (define_insn_and_split "call_value_osf_tlsgd"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "")) (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
(const_int 0))) (const_int 0)))
(unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL) (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSGD_CALL)
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
...@@ -6051,10 +6017,10 @@ ...@@ -6051,10 +6017,10 @@
[(set_attr "type" "multi")]) [(set_attr "type" "multi")])
(define_insn_and_split "call_value_osf_tlsldm" (define_insn_and_split "call_value_osf_tlsldm"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "")) (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
(const_int 0))) (const_int 0)))
(unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL) (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSLDM_CALL)
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"HAVE_AS_TLS" "HAVE_AS_TLS"
...@@ -6082,9 +6048,9 @@ ...@@ -6082,9 +6048,9 @@
[(set_attr "type" "multi")]) [(set_attr "type" "multi")])
(define_insn "*call_value_osf_1" (define_insn "*call_value_osf_1"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
(match_operand 2 "" ""))) (match_operand 2)))
(use (reg:DI 29)) (use (reg:DI 29))
(clobber (reg:DI 26))] (clobber (reg:DI 26))]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
...@@ -6096,9 +6062,9 @@ ...@@ -6096,9 +6062,9 @@
(set_attr "length" "12,*,16")]) (set_attr "length" "12,*,16")])
(define_insn "*sibcall_value_osf_1_er" (define_insn "*sibcall_value_osf_1_er"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
(match_operand 2 "" ""))) (match_operand 2)))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)] (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@ "@
...@@ -6108,9 +6074,9 @@ ...@@ -6108,9 +6074,9 @@
(set_attr "length" "*,8")]) (set_attr "length" "*,8")])
(define_insn "*sibcall_value_osf_1" (define_insn "*sibcall_value_osf_1"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
(match_operand 2 "" ""))) (match_operand 2)))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)] (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@ "@
...@@ -6123,9 +6089,9 @@ ...@@ -6123,9 +6089,9 @@
; to generate relocs for VMS link to potentially optimize the call. ; to generate relocs for VMS link to potentially optimize the call.
; Please do not molest. ; Please do not molest.
(define_insn "*call_value_vms_1" (define_insn "*call_value_vms_1"
[(set (match_operand 0 "" "") [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
(match_operand 2 "" ""))) (match_operand 2)))
(use (match_operand:DI 3 "nonmemory_operand" "r,n")) (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
(use (reg:DI 25)) (use (reg:DI 25))
(use (reg:DI 26)) (use (reg:DI 26))
......
gcc/config/alpha/sync.md
...@@ -37,7 +37,7 @@ ...@@ -37,7 +37,7 @@
}) })
(define_insn "*memory_barrier" (define_insn "*memory_barrier"
[(set (match_operand:BLK 0 "" "") [(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_MB))] (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
"" ""
"mb" "mb"
...@@ -71,18 +71,18 @@ ...@@ -71,18 +71,18 @@
(define_expand "atomic_compare_and_swap<mode>" (define_expand "atomic_compare_and_swap<mode>"
[(parallel [(parallel
[(set (match_operand:DI 0 "register_operand" "") ;; bool out [(set (match_operand:DI 0 "register_operand") ;; bool out
(unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG)) (unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG))
(set (match_operand:I48MODE 1 "register_operand" "") ;; val out (set (match_operand:I48MODE 1 "register_operand") ;; val out
(unspec_volatile:I48MODE [(const_int 0)] UNSPECV_CMPXCHG)) (unspec_volatile:I48MODE [(const_int 0)] UNSPECV_CMPXCHG))
(set (match_operand:I48MODE 2 "memory_operand" "") ;; memory (set (match_operand:I48MODE 2 "memory_operand") ;; memory
(unspec_volatile:I48MODE (unspec_volatile:I48MODE
[(match_dup 2) [(match_dup 2)
(match_operand:I48MODE 3 "reg_or_8bit_operand" "") ;; expected (match_operand:I48MODE 3 "reg_or_8bit_operand") ;; expected
(match_operand:I48MODE 4 "add_operand" "") ;; desired (match_operand:I48MODE 4 "add_operand") ;; desired
(match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; succ model (match_operand:SI 6 "const_int_operand") ;; succ model
(match_operand:SI 7 "const_int_operand" "")] ;; fail model (match_operand:SI 7 "const_int_operand")] ;; fail model
UNSPECV_CMPXCHG))])] UNSPECV_CMPXCHG))])]
"" ""
{ {
...@@ -103,9 +103,9 @@ ...@@ -103,9 +103,9 @@
[(match_dup 2) [(match_dup 2)
(match_operand:DI 3 "reg_or_8bit_operand" "rI") ;; expected (match_operand:DI 3 "reg_or_8bit_operand" "rI") ;; expected
(match_operand:DI 4 "add_operand" "rKL") ;; desired (match_operand:DI 4 "add_operand" "rKL") ;; desired
(match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; succ model (match_operand:SI 6 "const_int_operand") ;; succ model
(match_operand:SI 7 "const_int_operand" "")] ;; fail model (match_operand:SI 7 "const_int_operand")] ;; fail model
UNSPECV_CMPXCHG))] UNSPECV_CMPXCHG))]
"" ""
"#" "#"
...@@ -118,14 +118,14 @@ ...@@ -118,14 +118,14 @@
[(set_attr "type" "multi")]) [(set_attr "type" "multi")])
(define_expand "atomic_compare_and_swap<mode>" (define_expand "atomic_compare_and_swap<mode>"
[(match_operand:DI 0 "register_operand" "") ;; bool out [(match_operand:DI 0 "register_operand") ;; bool out
(match_operand:I12MODE 1 "register_operand" "") ;; val out (match_operand:I12MODE 1 "register_operand") ;; val out
(match_operand:I12MODE 2 "mem_noofs_operand" "") ;; memory (match_operand:I12MODE 2 "mem_noofs_operand") ;; memory
(match_operand:I12MODE 3 "register_operand" "") ;; expected (match_operand:I12MODE 3 "register_operand") ;; expected
(match_operand:I12MODE 4 "add_operand" "") ;; desired (match_operand:I12MODE 4 "add_operand") ;; desired
(match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; succ model (match_operand:SI 6 "const_int_operand") ;; succ model
(match_operand:SI 7 "const_int_operand" "")] ;; fail model (match_operand:SI 7 "const_int_operand")] ;; fail model
"" ""
{ {
alpha_expand_compare_and_swap_12 (operands); alpha_expand_compare_and_swap_12 (operands);
...@@ -144,9 +144,9 @@ ...@@ -144,9 +144,9 @@
(match_operand:DI 3 "reg_or_8bit_operand" "rI") ;; expected (match_operand:DI 3 "reg_or_8bit_operand" "rI") ;; expected
(match_operand:DI 4 "reg_or_0_operand" "rJ") ;; desired (match_operand:DI 4 "reg_or_0_operand" "rJ") ;; desired
(match_operand:DI 5 "register_operand" "r") ;; align (match_operand:DI 5 "register_operand" "r") ;; align
(match_operand:SI 6 "const_int_operand" "") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; is_weak
(match_operand:SI 7 "const_int_operand" "") ;; succ model (match_operand:SI 7 "const_int_operand") ;; succ model
(match_operand:SI 8 "const_int_operand" "")] ;; fail model (match_operand:SI 8 "const_int_operand")] ;; fail model
UNSPECV_CMPXCHG)) UNSPECV_CMPXCHG))
(clobber (match_scratch:DI 9 "=&r"))] (clobber (match_scratch:DI 9 "=&r"))]
"" ""
...@@ -165,7 +165,7 @@ ...@@ -165,7 +165,7 @@
(set (match_dup 1) (set (match_dup 1)
(unspec:I48MODE (unspec:I48MODE
[(match_operand:I48MODE 2 "add_operand" "rKL") ;; input [(match_operand:I48MODE 2 "add_operand" "rKL") ;; input
(match_operand:SI 3 "const_int_operand" "")] ;; model (match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_XCHG)) UNSPEC_XCHG))
(clobber (match_scratch:I48MODE 4 "=&r"))] (clobber (match_scratch:I48MODE 4 "=&r"))]
"" ""
...@@ -179,10 +179,10 @@ ...@@ -179,10 +179,10 @@
[(set_attr "type" "multi")]) [(set_attr "type" "multi")])
(define_expand "atomic_exchange<mode>" (define_expand "atomic_exchange<mode>"
[(match_operand:I12MODE 0 "register_operand" "") ;; output [(match_operand:I12MODE 0 "register_operand") ;; output
(match_operand:I12MODE 1 "mem_noofs_operand" "") ;; memory (match_operand:I12MODE 1 "mem_noofs_operand") ;; memory
(match_operand:I12MODE 2 "reg_or_0_operand" "") ;; input (match_operand:I12MODE 2 "reg_or_0_operand") ;; input
(match_operand:SI 3 "const_int_operand" "")] ;; model (match_operand:SI 3 "const_int_operand")] ;; model
"" ""
{ {
alpha_expand_atomic_exchange_12 (operands); alpha_expand_atomic_exchange_12 (operands);
...@@ -197,7 +197,7 @@ ...@@ -197,7 +197,7 @@
(unspec:I12MODE (unspec:I12MODE
[(match_operand:DI 2 "reg_or_8bit_operand" "rI") ;; input [(match_operand:DI 2 "reg_or_8bit_operand" "rI") ;; input
(match_operand:DI 3 "register_operand" "r") ;; align (match_operand:DI 3 "register_operand" "r") ;; align
(match_operand:SI 4 "const_int_operand" "")] ;; model (match_operand:SI 4 "const_int_operand")] ;; model
UNSPEC_XCHG)) UNSPEC_XCHG))
(clobber (match_scratch:DI 5 "=&r"))] (clobber (match_scratch:DI 5 "=&r"))]
"" ""
...@@ -215,7 +215,7 @@ ...@@ -215,7 +215,7 @@
(unspec:I48MODE (unspec:I48MODE
[(FETCHOP:I48MODE (match_dup 0) [(FETCHOP:I48MODE (match_dup 0)
(match_operand:I48MODE 1 "<fetchop_pred>" "<fetchop_constr>")) (match_operand:I48MODE 1 "<fetchop_pred>" "<fetchop_constr>"))
(match_operand:SI 2 "const_int_operand" "")] (match_operand:SI 2 "const_int_operand")]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (match_scratch:I48MODE 3 "=&r"))] (clobber (match_scratch:I48MODE 3 "=&r"))]
"" ""
...@@ -236,7 +236,7 @@ ...@@ -236,7 +236,7 @@
[(not:I48MODE [(not:I48MODE
(and:I48MODE (match_dup 0) (and:I48MODE (match_dup 0)
(match_operand:I48MODE 1 "register_operand" "r"))) (match_operand:I48MODE 1 "register_operand" "r")))
(match_operand:SI 2 "const_int_operand" "")] (match_operand:SI 2 "const_int_operand")]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (match_scratch:I48MODE 3 "=&r"))] (clobber (match_scratch:I48MODE 3 "=&r"))]
"" ""
...@@ -258,7 +258,7 @@ ...@@ -258,7 +258,7 @@
(unspec:I48MODE (unspec:I48MODE
[(FETCHOP:I48MODE (match_dup 1) [(FETCHOP:I48MODE (match_dup 1)
(match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>")) (match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>"))
(match_operand:SI 3 "const_int_operand" "")] (match_operand:SI 3 "const_int_operand")]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (match_scratch:I48MODE 4 "=&r"))] (clobber (match_scratch:I48MODE 4 "=&r"))]
"" ""
...@@ -281,7 +281,7 @@ ...@@ -281,7 +281,7 @@
[(not:I48MODE [(not:I48MODE
(and:I48MODE (match_dup 1) (and:I48MODE (match_dup 1)
(match_operand:I48MODE 2 "register_operand" "r"))) (match_operand:I48MODE 2 "register_operand" "r")))
(match_operand:SI 3 "const_int_operand" "")] (match_operand:SI 3 "const_int_operand")]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (match_scratch:I48MODE 4 "=&r"))] (clobber (match_scratch:I48MODE 4 "=&r"))]
"" ""
...@@ -304,7 +304,7 @@ ...@@ -304,7 +304,7 @@
(set (match_dup 1) (set (match_dup 1)
(unspec:I48MODE (unspec:I48MODE
[(FETCHOP:I48MODE (match_dup 1) (match_dup 2)) [(FETCHOP:I48MODE (match_dup 1) (match_dup 2))
(match_operand:SI 3 "const_int_operand" "")] (match_operand:SI 3 "const_int_operand")]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (match_scratch:I48MODE 4 "=&r"))] (clobber (match_scratch:I48MODE 4 "=&r"))]
"" ""
...@@ -327,7 +327,7 @@ ...@@ -327,7 +327,7 @@
(set (match_dup 1) (set (match_dup 1)
(unspec:I48MODE (unspec:I48MODE
[(not:I48MODE (and:I48MODE (match_dup 1) (match_dup 2))) [(not:I48MODE (and:I48MODE (match_dup 1) (match_dup 2)))
(match_operand:SI 3 "const_int_operand" "")] (match_operand:SI 3 "const_int_operand")]
UNSPEC_ATOMIC)) UNSPEC_ATOMIC))
(clobber (match_scratch:I48MODE 4 "=&r"))] (clobber (match_scratch:I48MODE 4 "=&r"))]
"" ""
......
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