re PR target/71720 (initialization of a vector of floats generates incorrect code for -mcpu=power9)

[gcc]
2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71720
	* config/rs6000/vsx.md (vsx_splat_v4sf_internal): When splitting
	the insns, use vsx_xxspltw_v4sf_direct which does not check for
	little endian.

[gcc/testsuite]
2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71720
	* gcc.target/powerpc/pr71720.c: New test.

From-SVN: r237920

gcc/ChangeLog

+2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/71720
+	* config/rs6000/vsx.md (vsx_splat_v4sf_internal): When splitting
+	the insns, use vsx_xxspltw_v4sf_direct which does not check for
+	little endian.
+
 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 
 	* varasm.c (get_variable_section): Validate initializer in

gcc/config/rs6000/vsx.md

@@ -2512,9 +2512,8 @@
   [(set (match_dup 0)
 	(unspec:V4SF [(match_dup 1)] UNSPEC_VSX_CVDPSPN))
    (set (match_dup 0)
-	(vec_duplicate:V4SF
-	 (vec_select:SF (match_dup 0)
-			(parallel [(const_int 0)]))))]
+	(unspec:V4SF [(match_dup 0)
+		      (const_int 0)] UNSPEC_VSX_XXSPLTW))]
   ""
   [(set_attr "type" "vecload,vecperm,mftgpr")
    (set_attr "length" "4,8,4")])

gcc/testsuite/ChangeLog

+2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/71720
+	* gcc.target/powerpc/pr71720.c: New test.
+
 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 
 	* gcc.dg/bss.c: New.

gcc/testsuite/gcc.target/powerpc/pr71720.c

+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+
+/* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat.  */
+
+vector float
+splat_v4sf (float f)
+{
+  return (vector float) { f, f, f, f };
+}
+
+/* { dg-final { scan-assembler "xscvdpspn "      } } */
+/* { dg-final { scan-assembler "xxspltw .*,.*,0" } } */