Correct the latency of loads in M5100

gcc/
	* config/mips/m5100.md (m51_int_load): Update the latency to 2.

From-SVN: r236288

gcc/ChangeLog

+2016-05-16  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* config/mips/m5100.md (m51_int_load): Update the latency to 2.
+
 2016-05-16  Nathan Sidwell  <nathan@acm.org>
 
 	* config/nvptx/nvptx.c (nvptx_mangle_decl_assembler_name): Revert.

gcc/config/mips/m5100.md

@@ -65,7 +65,7 @@
 
 ;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
 ;; prefetch: prefetch, prefetchx
-(define_insn_reservation "m51_int_load" 3
+(define_insn_reservation "m51_int_load" 2
   (and (eq_attr "cpu" "m5100")
        (eq_attr "type" "load,prefetch,prefetchx"))
   "m51_alu")