extend.texi: Copy-edit to fix incorrect hyphenation phrases involving "bit"...

2012-11-10  Sandra Loosemore  <sandra@codesourcery.com>

	gcc/
	* doc/extend.texi: Copy-edit to fix incorrect hyphenation phrases
	involving "bit", "byte", "word", "precision", and "floating"
	modifiers.

From-SVN: r193402

gcc/ChangeLog

 2012-11-10  Sandra Loosemore  <sandra@codesourcery.com>
 
+	* doc/extend.texi: Copy-edit to fix incorrect hyphenation phrases
+	involving "bit", "byte", "word", "precision", and "floating"
+	modifiers.
+
+2012-11-10  Sandra Loosemore  <sandra@codesourcery.com>
+
 	* doc/extend.texi: Copy-edit to fix incorrect uses of "which" 
 	and "that" throughout the file.
 

gcc/doc/extend.texi

@@ -812,11 +812,11 @@ effects of recomputing it.
 @cindex @code{__int128} data types
 
 As an extension the integer scalar type @code{__int128} is supported for
-targets having an integer mode wide enough to hold 128-bit.
+targets having an integer mode wide enough to hold 128 bits.
 Simply write @code{__int128} for a signed 128-bit integer, or
 @code{unsigned __int128} for an unsigned 128-bit integer.  There is no
 support in GCC to express an integer constant of type @code{__int128}
-for targets having @code{long long} integer with less then 128 bit width.
+for targets having @code{long long} integer less than 128 bits wide.
 
 @node Long Long
 @section Double-Word Integers
@@ -917,8 +917,8 @@ examine and set these two fictitious variables with your debugger.
 @cindex @code{Q} floating point suffix
 
 As an extension, the GNU C compiler supports additional floating
-types, @code{__float80} and @code{__float128} to support 80bit
-(@code{XFmode}) and 128 bit (@code{TFmode}) floating types.
+types, @code{__float80} and @code{__float128} to support 80-bit
+(@code{XFmode}) and 128-bit (@code{TFmode}) floating types.
 Support for additional types includes the arithmetic operators:
 add, subtract, multiply, divide; unary arithmetic operators;
 relational operators; equality operators; and conversions to and from
@@ -933,7 +933,7 @@ typedef _Complex float __attribute__((mode(TC))) _Complex128;
 typedef _Complex float __attribute__((mode(XC))) _Complex80;
 @end smallexample
 
-Not all targets support additional floating point types.  @code{__float80}
+Not all targets support additional floating-point types.  @code{__float80}
 and @code{__float128} types are supported on i386, x86_64 and ia64 targets.
 The @code{__float128} type is supported on hppa HP-UX targets.
 
@@ -2475,11 +2475,11 @@ referenced.  On Microsoft Windows targets, the attribute can be disabled
 for functions by setting the @option{-mnop-fun-dllimport} flag.
 
 @item eightbit_data
-@cindex eight bit data on the H8/300, H8/300H, and H8S
+@cindex eight-bit data on the H8/300, H8/300H, and H8S
 Use this attribute on the H8/300, H8/300H, and H8S to indicate that the specified
-variable should be placed into the eight bit data section.
+variable should be placed into the eight-bit data section.
 The compiler generates more efficient code for certain operations
-on data in the eight bit data area.  Note the eight bit data area is limited to
+on data in the eight-bit data area.  Note the eight-bit data area is limited to
 256 bytes of data.
 
 You must use GAS and GLD from GNU binutils version 2.7 or later for
@@ -2710,8 +2710,8 @@ from the special page vector table which contains the 16 low-order
 bits of the subroutine's entry address. Each vector table has special
 page number (18 to 255) that is used in @code{jsrs} instructions.
 Jump addresses of the routines are generated by adding 0x0F0000 (in
-case of M16C targets) or 0xFF0000 (in case of M32C targets), to the 2
-byte addresses set in the vector table. Therefore you need to ensure
+case of M16C targets) or 0xFF0000 (in case of M32C targets), to the
+2-byte addresses set in the vector table. Therefore you need to ensure
 that all the special page vector routines should get mapped within the
 address range 0x0F0000 to 0x0FFFFF (for M16C) and 0xFF0000 to 0xFFFFFF
 (for M32C).
@@ -2811,7 +2811,7 @@ void f () __attribute__ ((interrupt ("IRQ")));
 Permissible values for this parameter are: IRQ, FIQ, SWI, ABORT and UNDEF@.
 
 On ARMv7-M the interrupt type is ignored, and the attribute means the function
-may be called with a word aligned stack pointer.
+may be called with a word-aligned stack pointer.
 
 On Epiphany targets one or more optional parameters can be added like this:
 
@@ -3085,7 +3085,7 @@ caller pops the stack for hidden pointer.
 @item ms_hook_prologue
 @cindex @code{ms_hook_prologue} attribute
 
-On 32 bit i[34567]86-*-* targets and 64 bit x86_64-*-* targets, you can use
+On 32-bit i[34567]86-*-* targets and 64-bit x86_64-*-* targets, you can use
 this function attribute to make gcc generate the "hot-patching" function
 prologue used in Win32 API functions in Microsoft Windows XP Service Pack 2
 and newer.
@@ -3422,10 +3422,10 @@ problem.)
 @item sseregparm
 @cindex @code{sseregparm} attribute
 On the Intel 386 with SSE support, the @code{sseregparm} attribute
-causes the compiler to pass up to 3 floating point arguments in
+causes the compiler to pass up to 3 floating-point arguments in
 SSE registers instead of on the stack.  Functions that take a
 variable number of arguments continue to pass all of their
-floating point arguments on the stack.
+floating-point arguments on the stack.
 
 @item force_align_arg_pointer
 @cindex @code{force_align_arg_pointer} attribute
@@ -3696,7 +3696,7 @@ Enable/disable the generation of the CLD before string moves.
 @itemx no-fancy-math-387
 @cindex @code{target("fancy-math-387")} attribute
 Enable/disable the generation of the @code{sin}, @code{cos}, and
-@code{sqrt} instructions on the 387 floating point unit.
+@code{sqrt} instructions on the 387 floating-point unit.
 
 @item fused-madd
 @itemx no-fused-madd
@@ -3729,7 +3729,7 @@ Do/do not align destination of inlined string operations.
 @cindex @code{target("recip")} attribute
 Enable/disable the generation of RCPSS, RCPPS, RSQRTSS and RSQRTPS
 instructions followed an additional Newton-Raphson step instead of
-doing a floating point division.
+doing a floating-point division.
 
 @item arch=@var{ARCH}
 @cindex @code{target("arch=@var{ARCH}")} attribute
@@ -3741,7 +3741,7 @@ Specify the architecture to tune for in compiling the function.
 
 @item fpmath=@var{FPMATH}
 @cindex @code{target("fpmath=@var{FPMATH}")} attribute
-Specify which floating point unit to use.  The
+Specify which floating-point unit to use.  The
 @code{target("fpmath=sse,387")} option must be specified as
 @code{target("fpmath=sse+387")} because the comma would separate
 different options.
@@ -3781,7 +3781,7 @@ that support the PowerPC V2.03 architecture.
 @item hard-dfp
 @itemx no-hard-dfp
 @cindex @code{target("hard-dfp")} attribute
-Generate code that uses (does not use) the decimal floating point
+Generate code that uses (does not use) the decimal floating-point
 instructions implemented on some POWER processors.
 
 @item isel
@@ -3827,8 +3827,8 @@ location.
 @item popcntb
 @itemx no-popcntb
 @cindex @code{target("popcntb")} attribute
-Generate code that uses (does not use) the popcount and double
-precision FP reciprocal estimate instruction implemented on the POWER5
+Generate code that uses (does not use) the popcount and double-precision
+FP reciprocal estimate instruction implemented on the POWER5
 processor and other processors that support the PowerPC V2.02
 architecture.
 
@@ -3857,7 +3857,7 @@ floating-point square root.
 @itemx no-recip-precision
 @cindex @code{target("recip-precision")} attribute
 Assume (do not assume) that the reciprocal estimate instructions
-provide higher precision estimates than is mandated by the powerpc
+provide higher-precision estimates than is mandated by the powerpc
 ABI.
 
 @item string
@@ -3881,9 +3881,9 @@ cannot enable VSX or Altivec instructions unless
 @cindex @code{target("friz")} attribute
 Generate (do not generate) the @code{friz} instruction when the
 @option{-funsafe-math-optimizations} option is used to optimize
-rounding a floating point value to 64-bit integer and back to floating
+rounding a floating-point value to 64-bit integer and back to floating
 point.  The @code{friz} instruction does not return the same value if
-the floating point number is too large to fit in an integer.
+the floating-point number is too large to fit in an integer.
 
 @item avoid-indexed-addresses
 @itemx no-avoid-indexed-addresses
@@ -3939,7 +3939,7 @@ Use this attribute on the H8/300H and H8S to indicate that the specified
 variable should be placed into the tiny data section.
 The compiler generates more efficient code for loads and stores
 on data in the tiny data section.  Note the tiny data area is limited to
-slightly under 32kbytes of data.
+slightly under 32KB of data.
 
 @item trap_exit
 @cindex @code{trap_exit} attribute
@@ -4587,8 +4587,8 @@ by inherent limitations in your linker.  On many systems, the linker is
 only able to arrange for variables to be aligned up to a certain maximum
 alignment.  (For some linkers, the maximum supported alignment may
 be very very small.)  If your linker is only able to align variables
-up to a maximum of 8 byte alignment, then specifying @code{aligned(16)}
-in an @code{__attribute__} still only provides you with 8 byte
+up to a maximum of 8-byte alignment, then specifying @code{aligned(16)}
+in an @code{__attribute__} still only provides you with 8-byte
 alignment.  See your linker documentation for further information.
 
 The @code{aligned} attribute can also be used for functions
@@ -4652,7 +4652,7 @@ types (@pxref{Function Attributes}, @pxref{Type Attributes}.)
 @cindex @code{mode} attribute
 This attribute specifies the data type for the declaration---whichever
 type corresponds to the mode @var{mode}.  This in effect lets you
-request an integer or floating point type according to its width.
+request an integer or floating-point type according to its width.
 
 You may also specify a mode of @samp{byte} or @samp{__byte__} to
 indicate the mode corresponding to a one-byte integer, @samp{word} or
@@ -4931,9 +4931,9 @@ addresses).
 The MeP target has a number of addressing modes and busses.  The
 @code{near} space spans the standard memory space's first 16 megabytes
 (24 bits).  The @code{far} space spans the entire 32-bit memory space.
-The @code{based} space is a 128 byte region in the memory space that
+The @code{based} space is a 128-byte region in the memory space that
 is addressed relative to the @code{$tp} register.  The @code{tiny}
-space is a 65536 byte region relative to the @code{$gp} register.  In
+space is a 65536-byte region relative to the @code{$gp} register.  In
 addition to these memory regions, the MeP target has a separate 16-bit
 control bus which is specified with @code{cb} attributes.
 
@@ -5260,8 +5260,8 @@ by inherent limitations in your linker.  On many systems, the linker is
 only able to arrange for variables to be aligned up to a certain maximum
 alignment.  (For some linkers, the maximum supported alignment may
 be very very small.)  If your linker is only able to align variables
-up to a maximum of 8 byte alignment, then specifying @code{aligned(16)}
-in an @code{__attribute__} still only provides you with 8 byte
+up to a maximum of 8-byte alignment, then specifying @code{aligned(16)}
+in an @code{__attribute__} still only provides you with 8-byte
 alignment.  See your linker documentation for further information.
 
 @item packed
@@ -5814,7 +5814,7 @@ asm ("fsinx %1,%0" : "=f" (result) : "f" (angle));
 @noindent
 Here @code{angle} is the C expression for the input operand while
 @code{result} is that of the output operand.  Each has @samp{"f"} as its
-operand constraint, saying that a floating point register is required.
+operand constraint, saying that a floating-point register is required.
 The @samp{=} in @samp{=f} indicates that the operand is an output; all
 output operands' constraints must use @samp{=}.  The constraints use the
 same language used in the machine description (@pxref{Constraints}).
@@ -6116,7 +6116,7 @@ instruction.)  Note that even a volatile @code{asm} instruction
 can be moved relative to other code, including across jump
 instructions.  For example, on many targets there is a system
 register that can be set to control the rounding mode of
-floating point operations.  You might try
+floating-point operations.  You might try
 setting it with a volatile @code{asm}, like this PowerPC example:
 
 @smallexample
@@ -6270,7 +6270,7 @@ space in the object file than is needed for a single instruction.
 If this happens then the assembler produces a diagnostic saying that
 a label is unreachable.
 
-@subsection i386 floating point asm operands
+@subsection i386 floating-point asm operands
 
 There are several rules on the usage of stack-like regs in
 asm_operands insns.  These rules apply only to the operands that are
@@ -8054,7 +8054,7 @@ are all recognized as built-in functions unless
 is specified for an individual function).  All of these functions have
 corresponding versions prefixed with @code{__builtin_}.
 
-GCC provides built-in versions of the ISO C99 floating point comparison
+GCC provides built-in versions of the ISO C99 floating-point comparison
 macros that avoid raising exceptions for unordered operands.  They have
 the same names as the standard macros ( @code{isgreater},
 @code{isgreaterequal}, @code{isless}, @code{islessequal},
@@ -8332,15 +8332,15 @@ if it is non-zero means misalignment offset.  For example:
 void *x = __builtin_assume_aligned (arg, 16);
 @end smallexample
 
-means that the compiler can assume x, set to arg, is at least
-16 byte aligned, while:
+means that the compiler can assume @code{x}, set to @code{arg}, is at least
+16-byte aligned, while:
 
 @smallexample
 void *x = __builtin_assume_aligned (arg, 32, 8);
 @end smallexample
 
-means that the compiler can assume for x, set to arg, that
-(char *) x - 8 is 32 byte aligned.
+means that the compiler can assume for @code{x}, set to @code{arg}, that
+@code{(char *) x - 8} is 32-byte aligned.
 @end deftypefn
 
 @deftypefn {Built-in Function} int __builtin_LINE ()
@@ -8434,7 +8434,7 @@ five int arguments should be the target library's notion of the
 possible FP classes and are used for return values.  They must be
 constant values and they must appear in this order: @code{FP_NAN},
 @code{FP_INFINITE}, @code{FP_NORMAL}, @code{FP_SUBNORMAL} and
-@code{FP_ZERO}.  The ellipsis is for exactly one floating point value
+@code{FP_ZERO}.  The ellipsis is for exactly one floating-point value
 to classify.  GCC treats the last argument as type-generic, which
 means it does not do default promotion from float to double.
 @end deftypefn
@@ -8469,7 +8469,7 @@ type is @code{long double}.
 @deftypefn {Built-in Function} int __builtin_isinf_sign (...)
 Similar to @code{isinf}, except the return value is negative for
 an argument of @code{-Inf}.  Note while the parameter list is an
-ellipsis, this function only accepts exactly one floating point
+ellipsis, this function only accepts exactly one floating-point
 argument.  GCC treats this parameter as type-generic, which means it
 does not do default promotion from float to double.
 @end deftypefn
@@ -8638,12 +8638,12 @@ exactly 8 bits.
 
 @deftypefn {Built-in Function} uint32_t __builtin_bswap32 (uint32_t x)
 Similar to @code{__builtin_bswap16}, except the argument and return types
-are 32-bit.
+are 32 bit.
 @end deftypefn
 
 @deftypefn {Built-in Function} uint64_t __builtin_bswap64 (uint64_t x)
 Similar to @code{__builtin_bswap32}, except the argument and return types
-are 64-bit.
+are 64 bit.
 @end deftypefn
 
 @node Target Builtins
@@ -9009,8 +9009,8 @@ __builtin_avr_insert_bits (0x32107654, bits, 0)
 @end smallexample
 
 @smallexample
-// high-nibble of result is the high-nibble of val
-// low-nibble of result is the low-nibble of bits
+// high nibble of result is the high nibble of val
+// low nibble of result is the low nibble of bits
 __builtin_avr_insert_bits (0xffff3210, bits, val)
 @end smallexample
 
@@ -9480,19 +9480,19 @@ vector of eight 8-bit integers.  Some of the built-in functions operate on
 MMX registers as a whole 64-bit entity, these use @code{V1DI} as their mode.
 
 If 3DNow!@: extensions are enabled, @code{V2SF} is used as a mode for a vector
-of two 32-bit floating point values.
+of two 32-bit floating-point values.
 
 If SSE extensions are enabled, @code{V4SF} is used for a vector of four 32-bit
-floating point values.  Some instructions use a vector of four 32-bit
+floating-point values.  Some instructions use a vector of four 32-bit
 integers, these use @code{V4SI}.  Finally, some instructions operate on an
 entire vector register, interpreting it as a 128-bit integer, these use mode
 @code{TI}.
 
 In 64-bit mode, the x86-64 family of processors uses additional built-in
 functions for efficient use of @code{TF} (@code{__float128}) 128-bit
-floating point and @code{TC} 128-bit complex floating point values.
+floating point and @code{TC} 128-bit complex floating-point values.
 
-The following floating point built-in functions are available in 64-bit
+The following floating-point built-in functions are available in 64-bit
 mode.  All of them implement the function that is part of the name.
 
 @smallexample
@@ -9508,7 +9508,7 @@ Generates the @code{pause} machine instruction with a compiler memory
 barrier.
 @end table
 
-The following floating point built-in functions are made available in the
+The following floating-point built-in functions are made available in the
 64-bit mode.
 
 @table @code
@@ -11370,7 +11370,7 @@ In each case, @var{cond} can be any of the 16 floating-point conditions:
 @table @code
 @item v2sf __builtin_mips_movt_c_@var{cond}_ps (v2sf @var{a}, v2sf @var{b}, v2sf @var{c}, v2sf @var{d})
 @itemx v2sf __builtin_mips_movf_c_@var{cond}_ps (v2sf @var{a}, v2sf @var{b}, v2sf @var{c}, v2sf @var{d})
-Conditional move based on floating point comparison (@code{c.@var{cond}.ps},
+Conditional move based on floating-point comparison (@code{c.@var{cond}.ps},
 @code{movt.ps}/@code{movf.ps}).
 
 The @code{movt} functions return the value @var{x} computed by:
@@ -11434,23 +11434,23 @@ Convert paired word to paired single (@code{cvt.ps.pw}).
 @item float __builtin_mips_recip1_s (float)
 @itemx double __builtin_mips_recip1_d (double)
 @itemx v2sf __builtin_mips_recip1_ps (v2sf)
-Reduced precision reciprocal (sequence step 1) (@code{recip1.@var{fmt}}).
+Reduced-precision reciprocal (sequence step 1) (@code{recip1.@var{fmt}}).
 
 @item float __builtin_mips_recip2_s (float, float)
 @itemx double __builtin_mips_recip2_d (double, double)
 @itemx v2sf __builtin_mips_recip2_ps (v2sf, v2sf)
-Reduced precision reciprocal (sequence step 2) (@code{recip2.@var{fmt}}).
+Reduced-precision reciprocal (sequence step 2) (@code{recip2.@var{fmt}}).
 
 @item float __builtin_mips_rsqrt1_s (float)
 @itemx double __builtin_mips_rsqrt1_d (double)
 @itemx v2sf __builtin_mips_rsqrt1_ps (v2sf)
-Reduced precision reciprocal square root (sequence step 1)
+Reduced-precision reciprocal square root (sequence step 1)
 (@code{rsqrt1.@var{fmt}}).
 
 @item float __builtin_mips_rsqrt2_s (float, float)
 @itemx double __builtin_mips_rsqrt2_d (double, double)
 @itemx v2sf __builtin_mips_rsqrt2_ps (v2sf, v2sf)
-Reduced precision reciprocal square root (sequence step 2)
+Reduced-precision reciprocal square root (sequence step 2)
 (@code{rsqrt2.@var{fmt}}).
 @end table
 
@@ -11578,7 +11578,7 @@ picoChip instruction set.
 @table @code
 @item int __builtin_sbc (int @var{value})
 Sign bit count.  Return the number of consecutive bits in @var{value}
-that have the same value as the sign-bit.  The result is the number of
+that have the same value as the sign bit.  The result is the number of
 leading sign bits minus one, giving the number of redundant sign bits in
 @var{value}.
 
@@ -13763,36 +13763,36 @@ with the specified value.
 
 @deftypefn {Built-in Function}  void __builtin_rx_machi (int, int)
 Generates the @code{machi} machine instruction to add the result of
-multiplying the top 16-bits of the two arguments into the
+multiplying the top 16 bits of the two arguments into the
 accumulator.
 @end deftypefn
 
 @deftypefn {Built-in Function}  void __builtin_rx_maclo (int, int)
 Generates the @code{maclo} machine instruction to add the result of
-multiplying the bottom 16-bits of the two arguments into the
+multiplying the bottom 16 bits of the two arguments into the
 accumulator.
 @end deftypefn
 
 @deftypefn {Built-in Function}  void __builtin_rx_mulhi (int, int)
 Generates the @code{mulhi} machine instruction to place the result of
-multiplying the top 16-bits of the two arguments into the
+multiplying the top 16 bits of the two arguments into the
 accumulator.
 @end deftypefn
 
 @deftypefn {Built-in Function}  void __builtin_rx_mullo (int, int)
 Generates the @code{mullo} machine instruction to place the result of
-multiplying the bottom 16-bits of the two arguments into the
+multiplying the bottom 16 bits of the two arguments into the
 accumulator.
 @end deftypefn
 
 @deftypefn {Built-in Function}  int  __builtin_rx_mvfachi (void)
 Generates the @code{mvfachi} machine instruction to read the top
-32-bits of the accumulator.
+32 bits of the accumulator.
 @end deftypefn
 
 @deftypefn {Built-in Function}  int  __builtin_rx_mvfacmi (void)
 Generates the @code{mvfacmi} machine instruction to read the middle
-32-bits of the accumulator.
+32 bits of the accumulator.
 @end deftypefn
 
 @deftypefn {Built-in Function}  int __builtin_rx_mvfc (int)
@@ -13802,12 +13802,12 @@ register specified in its argument and returns its value.
 
 @deftypefn {Built-in Function}  void __builtin_rx_mvtachi (int)
 Generates the @code{mvtachi} machine instruction to set the top
-32-bits of the accumulator.
+32 bits of the accumulator.
 @end deftypefn
 
 @deftypefn {Built-in Function}  void __builtin_rx_mvtaclo (int)
 Generates the @code{mvtaclo} machine instruction to set the bottom
-32-bits of the accumulator.
+32 bits of the accumulator.
 @end deftypefn
 
 @deftypefn {Built-in Function}  void __builtin_rx_mvtc (int reg, int val)
@@ -13838,8 +13838,8 @@ repeated multiply and accumulate sequence.
 
 @deftypefn {Built-in Function}  void __builtin_rx_round (float)
 Generates the @code{round} machine instruction which returns the
-floating point argument rounded according to the current rounding mode
-set in the floating point status word register.
+floating-point argument rounded according to the current rounding mode
+set in the floating-point status word register.
 @end deftypefn
 
 @deftypefn {Built-in Function}  int __builtin_rx_sat (int)
@@ -15089,7 +15089,7 @@ Non-@code{static} members shall not be @code{__thread}.
 Integer constants can be written as binary constants, consisting of a
 sequence of @samp{0} and @samp{1} digits, prefixed by @samp{0b} or
 @samp{0B}.  This is particularly useful in environments that operate a
-lot on the bit-level (like microcontrollers).
+lot on the bit level (like microcontrollers).
 
 The following statements are identical: