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riscv-gcc-1
Commit 6f2dde9c by Uros Bizjak Committed by Uros Bizjak
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i386.md (<sincos>xf2): Rename from *<sincos>xf2_i387. 

	* config/i386/i386.md (<sincos>xf2): Rename from *<sincos>xf2_i387.
	(*<sincos>_extend<mode>xf2_i387): Remove insn pattern.
	(<sincos>mode2): New expander.
	(sincos_extend<mode>xf3_i387): Remove insn pattern.
	(sincos -> sin, cos splitters): Remove splitter patterns.
	(sincos<mode>3): Change operand 2 predicate to general_operand.
	Extend operand 2 to XFmode and generate sincosxf3 insn.
	(fptanxf4_i387): Change mode of operands 0 and 3 to SFmode.
	Change operand 3 predicate to const1_operand.
	(fptan_extend<mode>xf4_i387): Remove insn pattern.
	(tanxf2): Update operands in the call to fptanxf4_i387.
	(tan<mode>2): Change operand 1 predicate to general_operand.
	Extend operand 1 to XFmode and generate tanxf3 insn.
	(atan2xf3): Rename from *fpatanxf3_i387.
	(fpatan_extend<mode>xf3_i387): Remove insn pattern.
	(atan2xf3): Remove expander.
	(atan2<mode<3):  Change operand 1 and 2 predicates to general_operand.
	Extend operands 1 and 2 to XFmode and generate atan2xf3 insn.
	(atan<mode>2): Change operand 1 predicate to general_operand.
	Extend operand 1 to XFmode and generate atanxf3 insn.

From-SVN: r264195
parent dfc74155
Showing with 66 additions and 149 deletions
gcc/ChangeLog
2018-09-10 Uros Bizjak <ubizjak@gmail.com> 2018-09-10 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (<sincos>xf2): Rename from *<sincos>xf2_i387.
(*<sincos>_extend<mode>xf2_i387): Remove insn pattern.
(<sincos>mode2): New expander.
(sincos_extend<mode>xf3_i387): Remove insn pattern.
(sincos -> sin, cos splitters): Remove splitter patterns.
(sincos<mode>3): Change operand 2 predicate to general_operand.
Extend operand 2 to XFmode and generate sincosxf3 insn.
(fptanxf4_i387): Change mode of operands 0 and 3 to SFmode.
Change operand 3 predicate to const1_operand.
(fptan_extend<mode>xf4_i387): Remove insn pattern.
(tanxf2): Update operands in the call to fptanxf4_i387.
(tan<mode>2): Change operand 1 predicate to general_operand.
Extend operand 1 to XFmode and generate tanxf3 insn.
(atan2xf3): Rename from *fpatanxf3_i387.
(fpatan_extend<mode>xf3_i387): Remove insn pattern.
(atan2xf3): Remove expander.
(atan2<mode<3): Change operand 1 and 2 predicates to general_operand.
Extend operands 1 and 2 to XFmode and generate atan2xf3 insn.
(atan<mode>2): Change operand 1 predicate to general_operand.
Extend operand 1 to XFmode and generate atanxf3 insn.
2018-09-10 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (x87/SSE constant load splitter): Use * config/i386/i386.md (x87/SSE constant load splitter): Use
memory_operand instead of nonimmediate_operand for input operand memory_operand instead of nonimmediate_operand for input operand
predicate. predicate.
......
gcc/config/i386/i386.md
...@@ -15375,7 +15375,7 @@ ...@@ -15375,7 +15375,7 @@
[(UNSPEC_SIN "sin") [(UNSPEC_SIN "sin")
(UNSPEC_COS "cos")]) (UNSPEC_COS "cos")])
(define_insn "*<sincos>xf2_i387" (define_insn "<sincos>xf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
SINCOS))] SINCOS))]
...@@ -15386,25 +15386,23 @@ ...@@ -15386,25 +15386,23 @@
(set_attr "znver1_decode" "vector") (set_attr "znver1_decode" "vector")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
(define_insn "*<sincos>_extend<mode>xf2_i387" (define_expand "<sincos><mode>2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:MODEF 0 "register_operand")
(unspec:XF [(float_extend:XF (unspec:MODEF [(match_operand:MODEF 1 "general_operand")]
(match_operand:MODEF 1 "register_operand" "0"))] SINCOS))]
SINCOS))]
"TARGET_USE_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"f<sincos>" {
[(set_attr "type" "fpspc") rtx op0 = gen_reg_rtx (XFmode);
(set_attr "znver1_decode" "vector") rtx op1 = gen_reg_rtx (XFmode);
(set_attr "mode" "XF")])
;; When sincos pattern is defined, sin and cos builtin functions will be emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
;; expanded to sincos pattern with one of its outputs left unused. emit_insn (gen_<sincos>xf2 (op0, op1));
;; CSE pass will figure out if two sincos patterns can be combined, emit_insn (gen_truncxf<mode>2 (operands[0], op0));
;; otherwise sincos pattern will be split back to sin or cos pattern, DONE;
;; depending on the unused output. })
(define_insn "sincosxf3" (define_insn "sincosxf3"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
...@@ -15419,70 +15417,10 @@ ...@@ -15419,70 +15417,10 @@
(set_attr "znver1_decode" "vector") (set_attr "znver1_decode" "vector")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
(define_split
[(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_operand:XF 2 "register_operand")]
UNSPEC_SINCOS_COS))
(set (match_operand:XF 1 "register_operand")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
&& can_create_pseudo_p ()"
[(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))])
(define_split
[(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_operand:XF 2 "register_operand")]
UNSPEC_SINCOS_COS))
(set (match_operand:XF 1 "register_operand")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
&& can_create_pseudo_p ()"
[(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))])
(define_insn "sincos_extend<mode>xf3_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(float_extend:XF
(match_operand:MODEF 2 "register_operand" "0"))]
UNSPEC_SINCOS_COS))
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
(set_attr "mode" "XF")])
(define_split
[(set (match_operand:XF 0 "register_operand")
(unspec:XF [(float_extend:XF
(match_operand:MODEF 2 "register_operand"))]
UNSPEC_SINCOS_COS))
(set (match_operand:XF 1 "register_operand")
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
&& can_create_pseudo_p ()"
[(set (match_dup 1)
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))])
(define_split
[(set (match_operand:XF 0 "register_operand")
(unspec:XF [(float_extend:XF
(match_operand:MODEF 2 "register_operand"))]
UNSPEC_SINCOS_COS))
(set (match_operand:XF 1 "register_operand")
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
&& can_create_pseudo_p ()"
[(set (match_dup 0)
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))])
(define_expand "sincos<mode>3" (define_expand "sincos<mode>3"
[(use (match_operand:MODEF 0 "register_operand")) [(use (match_operand:MODEF 0 "register_operand"))
(use (match_operand:MODEF 1 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))
(use (match_operand:MODEF 2 "register_operand"))] (use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387) || TARGET_MIX_SSE_I387)
...@@ -15490,39 +15428,23 @@ ...@@ -15490,39 +15428,23 @@
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode); rtx op1 = gen_reg_rtx (XFmode);
rtx op2 = gen_reg_rtx (XFmode);
emit_insn (gen_sincos_extend<mode>xf3_i387 (op0, op1, operands[2])); emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
emit_insn (gen_sincosxf3 (op0, op1, op2));
emit_insn (gen_truncxf<mode>2 (operands[0], op0)); emit_insn (gen_truncxf<mode>2 (operands[0], op0));
emit_insn (gen_truncxf<mode>2 (operands[1], op1)); emit_insn (gen_truncxf<mode>2 (operands[1], op1));
DONE; DONE;
}) })
(define_insn "fptanxf4_i387" (define_insn "fptanxf4_i387"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(match_operand:XF 3 "const_double_operand" "F")) (match_operand:SF 3 "const1_operand"))
(set (match_operand:XF 1 "register_operand" "=u") (set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")] (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
UNSPEC_TAN))] UNSPEC_TAN))]
"TARGET_USE_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations && flag_unsafe_math_optimizations"
&& standard_80387_constant_p (operands[3]) == 2"
"fptan"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
(set_attr "mode" "XF")])
(define_insn "fptan_extend<mode>xf4_i387"
[(set (match_operand:MODEF 0 "register_operand" "=f")
(match_operand:MODEF 3 "const_double_operand" "F"))
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(float_extend:XF
(match_operand:MODEF 2 "register_operand" "0"))]
UNSPEC_TAN))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations
&& standard_80387_constant_p (operands[3]) == 2"
"fptan" "fptan"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector") (set_attr "znver1_decode" "vector")
...@@ -15534,33 +15456,30 @@ ...@@ -15534,33 +15456,30 @@
"TARGET_USE_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx one = gen_reg_rtx (XFmode); rtx one = gen_reg_rtx (SFmode);
rtx op2 = CONST1_RTX (XFmode); /* fld1 */ emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1],
CONST1_RTX (SFmode)));
emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1], op2));
DONE; DONE;
}) })
(define_expand "tan<mode>2" (define_expand "tan<mode>2"
[(use (match_operand:MODEF 0 "register_operand")) [(use (match_operand:MODEF 0 "register_operand"))
(use (match_operand:MODEF 1 "register_operand"))] (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
rtx one = gen_reg_rtx (<MODE>mode); emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
rtx op2 = CONST1_RTX (<MODE>mode); /* fld1 */ emit_insn (gen_tanxf2 (op0, op1));
emit_insn (gen_fptan_extend<mode>xf4_i387 (one, op0,
operands[1], op2));
emit_insn (gen_truncxf<mode>2 (operands[0], op0)); emit_insn (gen_truncxf<mode>2 (operands[0], op0));
DONE; DONE;
}) })
(define_insn "*fpatanxf3_i387" (define_insn "atan2xf3"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0") (unspec:XF [(match_operand:XF 1 "register_operand" "0")
(match_operand:XF 2 "register_operand" "u")] (match_operand:XF 2 "register_operand" "u")]
...@@ -15573,44 +15492,23 @@ ...@@ -15573,44 +15492,23 @@
(set_attr "znver1_decode" "vector") (set_attr "znver1_decode" "vector")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
(define_insn "fpatan_extend<mode>xf3_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(float_extend:XF
(match_operand:MODEF 1 "register_operand" "0"))
(float_extend:XF
(match_operand:MODEF 2 "register_operand" "u"))]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 "=2"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "atan2xf3"
[(parallel [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_operand:XF 2 "register_operand")
(match_operand:XF 1 "register_operand")]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations")
(define_expand "atan2<mode>3" (define_expand "atan2<mode>3"
[(use (match_operand:MODEF 0 "register_operand")) [(use (match_operand:MODEF 0 "register_operand"))
(use (match_operand:MODEF 1 "register_operand")) (use (match_operand:MODEF 1 "general_operand"))
(use (match_operand:MODEF 2 "register_operand"))] (use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
rtx op2 = gen_reg_rtx (XFmode);
emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, operands[2], operands[1])); emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_atan2xf3 (op0, op2, op1));
emit_insn (gen_truncxf<mode>2 (operands[0], op0)); emit_insn (gen_truncxf<mode>2 (operands[0], op0));
DONE; DONE;
}) })
...@@ -15623,25 +15521,21 @@ ...@@ -15623,25 +15521,21 @@
(clobber (match_scratch:XF 3))])] (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ "operands[2] = force_reg (XFmode, CONST1_RTX (XFmode));")
operands[2] = gen_reg_rtx (XFmode);
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
})
(define_expand "atan<mode>2" (define_expand "atan<mode>2"
[(use (match_operand:MODEF 0 "register_operand")) [(use (match_operand:MODEF 0 "register_operand"))
(use (match_operand:MODEF 1 "register_operand"))] (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387 "TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx op0 = gen_reg_rtx (XFmode); rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
rtx op2 = gen_reg_rtx (<MODE>mode); emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_move_insn (op2, CONST1_RTX (<MODE>mode)); /* fld1 */ emit_insn (gen_atanxf2 (op0, op1));
emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, op2, operands[1]));
emit_insn (gen_truncxf<mode>2 (operands[0], op0)); emit_insn (gen_truncxf<mode>2 (operands[0], op0));
DONE; DONE;
}) })
...@@ -15664,7 +15558,7 @@ ...@@ -15664,7 +15558,7 @@
for (i = 2; i < 6; i++) for (i = 2; i < 6; i++)
operands[i] = gen_reg_rtx (XFmode); operands[i] = gen_reg_rtx (XFmode);
emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ operands[3] = force_reg (XFmode, CONST1_RTX (XFmode));
}) })
(define_expand "asin<mode>2" (define_expand "asin<mode>2"
...@@ -15702,7 +15596,7 @@ ...@@ -15702,7 +15596,7 @@
for (i = 2; i < 6; i++) for (i = 2; i < 6; i++)
operands[i] = gen_reg_rtx (XFmode); operands[i] = gen_reg_rtx (XFmode);
emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ operands[3] = force_reg (XFmode, CONST1_RTX (XFmode));
}) })
(define_expand "acos<mode>2" (define_expand "acos<mode>2"
......
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