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riscv-gcc-1
Commit 6df4618c by Srinath Parvathaneni Committed by Kyrylo Tkachov
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[ARM][GCC][3/1x]: MVE intrinsics with unary operand. 

This patch supports following MVE ACLE intrinsics with unary operand.

vdupq_n_s8, vdupq_n_s16, vdupq_n_s32, vabsq_s8, vabsq_s16, vabsq_s32, vclsq_s8, vclsq_s16, vclsq_s32, vclzq_s8, vclzq_s16, vclzq_s32, vnegq_s8, vnegq_s16, vnegq_s32, vaddlvq_s32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vmovlbq_s8, vmovlbq_s16, vmovltq_s8, vmovltq_s16, vmvnq_s8, vmvnq_s16, vmvnq_s32, vrev16q_s8, vrev32q_s8, vrev32q_s16, vqabsq_s8, vqabsq_s16, vqabsq_s32, vqnegq_s8, vqnegq_s16, vqnegq_s32, vcvtaq_s16_f16, vcvtaq_s32_f32, vcvtnq_s16_f16, vcvtnq_s32_f32, vcvtpq_s16_f16, vcvtpq_s32_f32, vcvtmq_s16_f16, vcvtmq_s32_f32, vmvnq_u8, vmvnq_u16, vmvnq_u32, vdupq_n_u8, vdupq_n_u16, vdupq_n_u32, vclzq_u8, vclzq_u16, vclzq_u32, vaddvq_u8, vaddvq_u16, vaddvq_u32, vrev32q_u8, vrev32q_u16, vmovltq_u8, vmovltq_u16, vmovlbq_u8, vmovlbq_u16, vrev16q_u8, vaddlvq_u32, vcvtpq_u16_f16, vcvtpq_u32_f32, vcvtnq_u16_f16, vcvtmq_u16_f16, vcvtmq_u32_f32, vcvtaq_u16_f16, vcvtaq_u32_f32, vdupq_n, vabsq, vclsq, vclzq, vnegq, vaddlvq, vaddvq, vmovlbq, vmovltq, vmvnq, vrev16q, vrev32q, vqabsq, vqnegq.

A new register class "EVEN_REGS" which allows only even registers is added in this patch.

The new constraint "e" allows only reigsters of EVEN_REGS class.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
	* config/arm/arm_mve.h (vdupq_n_s8): Define macro.
	(vdupq_n_s16): Likewise.
	(vdupq_n_s32): Likewise.
	(vabsq_s8): Likewise.
	(vabsq_s16): Likewise.
	(vabsq_s32): Likewise.
	(vclsq_s8): Likewise.
	(vclsq_s16): Likewise.
	(vclsq_s32): Likewise.
	(vclzq_s8): Likewise.
	(vclzq_s16): Likewise.
	(vclzq_s32): Likewise.
	(vnegq_s8): Likewise.
	(vnegq_s16): Likewise.
	(vnegq_s32): Likewise.
	(vaddlvq_s32): Likewise.
	(vaddvq_s8): Likewise.
	(vaddvq_s16): Likewise.
	(vaddvq_s32): Likewise.
	(vmovlbq_s8): Likewise.
	(vmovlbq_s16): Likewise.
	(vmovltq_s8): Likewise.
	(vmovltq_s16): Likewise.
	(vmvnq_s8): Likewise.
	(vmvnq_s16): Likewise.
	(vmvnq_s32): Likewise.
	(vrev16q_s8): Likewise.
	(vrev32q_s8): Likewise.
	(vrev32q_s16): Likewise.
	(vqabsq_s8): Likewise.
	(vqabsq_s16): Likewise.
	(vqabsq_s32): Likewise.
	(vqnegq_s8): Likewise.
	(vqnegq_s16): Likewise.
	(vqnegq_s32): Likewise.
	(vcvtaq_s16_f16): Likewise.
	(vcvtaq_s32_f32): Likewise.
	(vcvtnq_s16_f16): Likewise.
	(vcvtnq_s32_f32): Likewise.
	(vcvtpq_s16_f16): Likewise.
	(vcvtpq_s32_f32): Likewise.
	(vcvtmq_s16_f16): Likewise.
	(vcvtmq_s32_f32): Likewise.
	(vmvnq_u8): Likewise.
	(vmvnq_u16): Likewise.
	(vmvnq_u32): Likewise.
	(vdupq_n_u8): Likewise.
	(vdupq_n_u16): Likewise.
	(vdupq_n_u32): Likewise.
	(vclzq_u8): Likewise.
	(vclzq_u16): Likewise.
	(vclzq_u32): Likewise.
	(vaddvq_u8): Likewise.
	(vaddvq_u16): Likewise.
	(vaddvq_u32): Likewise.
	(vrev32q_u8): Likewise.
	(vrev32q_u16): Likewise.
	(vmovltq_u8): Likewise.
	(vmovltq_u16): Likewise.
	(vmovlbq_u8): Likewise.
	(vmovlbq_u16): Likewise.
	(vrev16q_u8): Likewise.
	(vaddlvq_u32): Likewise.
	(vcvtpq_u16_f16): Likewise.
	(vcvtpq_u32_f32): Likewise.
	(vcvtnq_u16_f16): Likewise.
	(vcvtmq_u16_f16): Likewise.
	(vcvtmq_u32_f32): Likewise.
	(vcvtaq_u16_f16): Likewise.
	(vcvtaq_u32_f32): Likewise.
	(__arm_vdupq_n_s8): Define intrinsic.
	(__arm_vdupq_n_s16): Likewise.
	(__arm_vdupq_n_s32): Likewise.
	(__arm_vabsq_s8): Likewise.
	(__arm_vabsq_s16): Likewise.
	(__arm_vabsq_s32): Likewise.
	(__arm_vclsq_s8): Likewise.
	(__arm_vclsq_s16): Likewise.
	(__arm_vclsq_s32): Likewise.
	(__arm_vclzq_s8): Likewise.
	(__arm_vclzq_s16): Likewise.
	(__arm_vclzq_s32): Likewise.
	(__arm_vnegq_s8): Likewise.
	(__arm_vnegq_s16): Likewise.
	(__arm_vnegq_s32): Likewise.
	(__arm_vaddlvq_s32): Likewise.
	(__arm_vaddvq_s8): Likewise.
	(__arm_vaddvq_s16): Likewise.
	(__arm_vaddvq_s32): Likewise.
	(__arm_vmovlbq_s8): Likewise.
	(__arm_vmovlbq_s16): Likewise.
	(__arm_vmovltq_s8): Likewise.
	(__arm_vmovltq_s16): Likewise.
	(__arm_vmvnq_s8): Likewise.
	(__arm_vmvnq_s16): Likewise.
	(__arm_vmvnq_s32): Likewise.
	(__arm_vrev16q_s8): Likewise.
	(__arm_vrev32q_s8): Likewise.
	(__arm_vrev32q_s16): Likewise.
	(__arm_vqabsq_s8): Likewise.
	(__arm_vqabsq_s16): Likewise.
	(__arm_vqabsq_s32): Likewise.
	(__arm_vqnegq_s8): Likewise.
	(__arm_vqnegq_s16): Likewise.
	(__arm_vqnegq_s32): Likewise.
	(__arm_vmvnq_u8): Likewise.
	(__arm_vmvnq_u16): Likewise.
	(__arm_vmvnq_u32): Likewise.
	(__arm_vdupq_n_u8): Likewise.
	(__arm_vdupq_n_u16): Likewise.
	(__arm_vdupq_n_u32): Likewise.
	(__arm_vclzq_u8): Likewise.
	(__arm_vclzq_u16): Likewise.
	(__arm_vclzq_u32): Likewise.
	(__arm_vaddvq_u8): Likewise.
	(__arm_vaddvq_u16): Likewise.
	(__arm_vaddvq_u32): Likewise.
	(__arm_vrev32q_u8): Likewise.
	(__arm_vrev32q_u16): Likewise.
	(__arm_vmovltq_u8): Likewise.
	(__arm_vmovltq_u16): Likewise.
	(__arm_vmovlbq_u8): Likewise.
	(__arm_vmovlbq_u16): Likewise.
	(__arm_vrev16q_u8): Likewise.
	(__arm_vaddlvq_u32): Likewise.
	(__arm_vcvtpq_u16_f16): Likewise.
	(__arm_vcvtpq_u32_f32): Likewise.
	(__arm_vcvtnq_u16_f16): Likewise.
	(__arm_vcvtmq_u16_f16): Likewise.
	(__arm_vcvtmq_u32_f32): Likewise.
	(__arm_vcvtaq_u16_f16): Likewise.
	(__arm_vcvtaq_u32_f32): Likewise.
	(__arm_vcvtaq_s16_f16): Likewise.
	(__arm_vcvtaq_s32_f32): Likewise.
	(__arm_vcvtnq_s16_f16): Likewise.
	(__arm_vcvtnq_s32_f32): Likewise.
	(__arm_vcvtpq_s16_f16): Likewise.
	(__arm_vcvtpq_s32_f32): Likewise.
	(__arm_vcvtmq_s16_f16): Likewise.
	(__arm_vcvtmq_s32_f32): Likewise.
	(vdupq_n): Define polymorphic variant.
	(vabsq): Likewise.
	(vclsq): Likewise.
	(vclzq): Likewise.
	(vnegq): Likewise.
	(vaddlvq): Likewise.
	(vaddvq): Likewise.
	(vmovlbq): Likewise.
	(vmovltq): Likewise.
	(vmvnq): Likewise.
	(vrev16q): Likewise.
	(vrev32q): Likewise.
	(vqabsq): Likewise.
	(vqnegq): Likewise.
	* config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
	(UNOP_SNONE_NONE): Likewise.
	(UNOP_UNONE_UNONE): Likewise.
	(UNOP_UNONE_NONE): Likewise.
	* config/arm/constraints.md (e): Define new constriant to allow only
	even registers.
	* config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
	(mve_vnegq_s<mode>): Likewise.
	(mve_vmvnq_<supf><mode>): Likewise.
	(mve_vdupq_n_<supf><mode>): Likewise.
	(mve_vclzq_<supf><mode>): Likewise.
	(mve_vclsq_s<mode>): Likewise.
	(mve_vaddvq_<supf><mode>): Likewise.
	(mve_vabsq_s<mode>): Likewise.
	(mve_vrev32q_<supf><mode>): Likewise.
	(mve_vmovltq_<supf><mode>): Likewise.
	(mve_vmovlbq_<supf><mode>): Likewise.
	(mve_vcvtpq_<supf><mode>): Likewise.
	(mve_vcvtnq_<supf><mode>): Likewise.
	(mve_vcvtmq_<supf><mode>): Likewise.
	(mve_vcvtaq_<supf><mode>): Likewise.
	(mve_vrev16q_<supf>v16qi): Likewise.
	(mve_vaddlvq_<supf>v4si): Likewise.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabsq_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise.
parent 700d4cb0
Showing with 1955 additions and 8 deletions
gcc/ChangeLog
2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
* config/arm/arm_mve.h (vdupq_n_s8): Define macro.
(vdupq_n_s16): Likewise.
(vdupq_n_s32): Likewise.
(vabsq_s8): Likewise.
(vabsq_s16): Likewise.
(vabsq_s32): Likewise.
(vclsq_s8): Likewise.
(vclsq_s16): Likewise.
(vclsq_s32): Likewise.
(vclzq_s8): Likewise.
(vclzq_s16): Likewise.
(vclzq_s32): Likewise.
(vnegq_s8): Likewise.
(vnegq_s16): Likewise.
(vnegq_s32): Likewise.
(vaddlvq_s32): Likewise.
(vaddvq_s8): Likewise.
(vaddvq_s16): Likewise.
(vaddvq_s32): Likewise.
(vmovlbq_s8): Likewise.
(vmovlbq_s16): Likewise.
(vmovltq_s8): Likewise.
(vmovltq_s16): Likewise.
(vmvnq_s8): Likewise.
(vmvnq_s16): Likewise.
(vmvnq_s32): Likewise.
(vrev16q_s8): Likewise.
(vrev32q_s8): Likewise.
(vrev32q_s16): Likewise.
(vqabsq_s8): Likewise.
(vqabsq_s16): Likewise.
(vqabsq_s32): Likewise.
(vqnegq_s8): Likewise.
(vqnegq_s16): Likewise.
(vqnegq_s32): Likewise.
(vcvtaq_s16_f16): Likewise.
(vcvtaq_s32_f32): Likewise.
(vcvtnq_s16_f16): Likewise.
(vcvtnq_s32_f32): Likewise.
(vcvtpq_s16_f16): Likewise.
(vcvtpq_s32_f32): Likewise.
(vcvtmq_s16_f16): Likewise.
(vcvtmq_s32_f32): Likewise.
(vmvnq_u8): Likewise.
(vmvnq_u16): Likewise.
(vmvnq_u32): Likewise.
(vdupq_n_u8): Likewise.
(vdupq_n_u16): Likewise.
(vdupq_n_u32): Likewise.
(vclzq_u8): Likewise.
(vclzq_u16): Likewise.
(vclzq_u32): Likewise.
(vaddvq_u8): Likewise.
(vaddvq_u16): Likewise.
(vaddvq_u32): Likewise.
(vrev32q_u8): Likewise.
(vrev32q_u16): Likewise.
(vmovltq_u8): Likewise.
(vmovltq_u16): Likewise.
(vmovlbq_u8): Likewise.
(vmovlbq_u16): Likewise.
(vrev16q_u8): Likewise.
(vaddlvq_u32): Likewise.
(vcvtpq_u16_f16): Likewise.
(vcvtpq_u32_f32): Likewise.
(vcvtnq_u16_f16): Likewise.
(vcvtmq_u16_f16): Likewise.
(vcvtmq_u32_f32): Likewise.
(vcvtaq_u16_f16): Likewise.
(vcvtaq_u32_f32): Likewise.
(__arm_vdupq_n_s8): Define intrinsic.
(__arm_vdupq_n_s16): Likewise.
(__arm_vdupq_n_s32): Likewise.
(__arm_vabsq_s8): Likewise.
(__arm_vabsq_s16): Likewise.
(__arm_vabsq_s32): Likewise.
(__arm_vclsq_s8): Likewise.
(__arm_vclsq_s16): Likewise.
(__arm_vclsq_s32): Likewise.
(__arm_vclzq_s8): Likewise.
(__arm_vclzq_s16): Likewise.
(__arm_vclzq_s32): Likewise.
(__arm_vnegq_s8): Likewise.
(__arm_vnegq_s16): Likewise.
(__arm_vnegq_s32): Likewise.
(__arm_vaddlvq_s32): Likewise.
(__arm_vaddvq_s8): Likewise.
(__arm_vaddvq_s16): Likewise.
(__arm_vaddvq_s32): Likewise.
(__arm_vmovlbq_s8): Likewise.
(__arm_vmovlbq_s16): Likewise.
(__arm_vmovltq_s8): Likewise.
(__arm_vmovltq_s16): Likewise.
(__arm_vmvnq_s8): Likewise.
(__arm_vmvnq_s16): Likewise.
(__arm_vmvnq_s32): Likewise.
(__arm_vrev16q_s8): Likewise.
(__arm_vrev32q_s8): Likewise.
(__arm_vrev32q_s16): Likewise.
(__arm_vqabsq_s8): Likewise.
(__arm_vqabsq_s16): Likewise.
(__arm_vqabsq_s32): Likewise.
(__arm_vqnegq_s8): Likewise.
(__arm_vqnegq_s16): Likewise.
(__arm_vqnegq_s32): Likewise.
(__arm_vmvnq_u8): Likewise.
(__arm_vmvnq_u16): Likewise.
(__arm_vmvnq_u32): Likewise.
(__arm_vdupq_n_u8): Likewise.
(__arm_vdupq_n_u16): Likewise.
(__arm_vdupq_n_u32): Likewise.
(__arm_vclzq_u8): Likewise.
(__arm_vclzq_u16): Likewise.
(__arm_vclzq_u32): Likewise.
(__arm_vaddvq_u8): Likewise.
(__arm_vaddvq_u16): Likewise.
(__arm_vaddvq_u32): Likewise.
(__arm_vrev32q_u8): Likewise.
(__arm_vrev32q_u16): Likewise.
(__arm_vmovltq_u8): Likewise.
(__arm_vmovltq_u16): Likewise.
(__arm_vmovlbq_u8): Likewise.
(__arm_vmovlbq_u16): Likewise.
(__arm_vrev16q_u8): Likewise.
(__arm_vaddlvq_u32): Likewise.
(__arm_vcvtpq_u16_f16): Likewise.
(__arm_vcvtpq_u32_f32): Likewise.
(__arm_vcvtnq_u16_f16): Likewise.
(__arm_vcvtmq_u16_f16): Likewise.
(__arm_vcvtmq_u32_f32): Likewise.
(__arm_vcvtaq_u16_f16): Likewise.
(__arm_vcvtaq_u32_f32): Likewise.
(__arm_vcvtaq_s16_f16): Likewise.
(__arm_vcvtaq_s32_f32): Likewise.
(__arm_vcvtnq_s16_f16): Likewise.
(__arm_vcvtnq_s32_f32): Likewise.
(__arm_vcvtpq_s16_f16): Likewise.
(__arm_vcvtpq_s32_f32): Likewise.
(__arm_vcvtmq_s16_f16): Likewise.
(__arm_vcvtmq_s32_f32): Likewise.
(vdupq_n): Define polymorphic variant.
(vabsq): Likewise.
(vclsq): Likewise.
(vclzq): Likewise.
(vnegq): Likewise.
(vaddlvq): Likewise.
(vaddvq): Likewise.
(vmovlbq): Likewise.
(vmovltq): Likewise.
(vmvnq): Likewise.
(vrev16q): Likewise.
(vrev32q): Likewise.
(vqabsq): Likewise.
(vqnegq): Likewise.
* config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
(UNOP_SNONE_NONE): Likewise.
(UNOP_UNONE_UNONE): Likewise.
(UNOP_UNONE_NONE): Likewise.
* config/arm/constraints.md (e): Define new constriant to allow only
even registers.
* config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
(mve_vnegq_s<mode>): Likewise.
(mve_vmvnq_<supf><mode>): Likewise.
(mve_vdupq_n_<supf><mode>): Likewise.
(mve_vclzq_<supf><mode>): Likewise.
(mve_vclsq_s<mode>): Likewise.
(mve_vaddvq_<supf><mode>): Likewise.
(mve_vabsq_s<mode>): Likewise.
(mve_vrev32q_<supf><mode>): Likewise.
(mve_vmovltq_<supf><mode>): Likewise.
(mve_vmovlbq_<supf><mode>): Likewise.
(mve_vcvtpq_<supf><mode>): Likewise.
(mve_vcvtnq_<supf><mode>): Likewise.
(mve_vcvtmq_<supf><mode>): Likewise.
(mve_vcvtaq_<supf><mode>): Likewise.
(mve_vrev16q_<supf>v16qi): Likewise.
(mve_vaddlvq_<supf>v4si): Likewise.
2020-03-17 Jakub Jelinek <jakub@redhat.com>
* lra-spills.c (remove_pseudos): Fix up duplicated word issue in
......
gcc/config/arm/arm.h
......@@ -1167,6 +1167,7 @@ enum reg_class
BASE_REGS,
HI_REGS,
CALLER_SAVE_REGS,
EVEN_REG,
GENERAL_REGS,
CORE_REGS,
VFP_D0_D7_REGS,
......@@ -1195,6 +1196,7 @@ enum reg_class
"BASE_REGS", \
"HI_REGS", \
"CALLER_SAVE_REGS", \
"EVEN_REG", \
"GENERAL_REGS", \
"CORE_REGS", \
"VFP_D0_D7_REGS", \
......@@ -1222,6 +1224,7 @@ enum reg_class
{ 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
{ 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
{ 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
{ 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \
{ 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
{ 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
{ 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
......
gcc/config/arm/arm_mve_builtins.def
......@@ -35,8 +35,39 @@ VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf)
VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf)
VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf)
VAR3 (UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vqnegq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vqabsq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vnegq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vmvnq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vdupq_n_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vclzq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vclsq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vaddvq_s, v16qi, v8hi, v4si)
VAR3 (UNOP_SNONE_SNONE, vabsq_s, v16qi, v8hi, v4si)
VAR2 (UNOP_SNONE_SNONE, vrev32q_s, v16qi, v8hi)
VAR2 (UNOP_SNONE_SNONE, vmovltq_s, v16qi, v8hi)
VAR2 (UNOP_SNONE_SNONE, vmovlbq_s, v16qi, v8hi)
VAR2 (UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si)
VAR2 (UNOP_SNONE_NONE, vcvtpq_s, v8hi, v4si)
VAR2 (UNOP_SNONE_NONE, vcvtnq_s, v8hi, v4si)
VAR2 (UNOP_SNONE_NONE, vcvtmq_s, v8hi, v4si)
VAR2 (UNOP_SNONE_NONE, vcvtaq_s, v8hi, v4si)
VAR2 (UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si)
VAR1 (UNOP_SNONE_SNONE, vrev16q_s, v16qi)
VAR1 (UNOP_SNONE_SNONE, vaddlvq_s, v4si)
VAR3 (UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si)
VAR3 (UNOP_UNONE_UNONE, vmvnq_u, v16qi, v8hi, v4si)
VAR3 (UNOP_UNONE_UNONE, vdupq_n_u, v16qi, v8hi, v4si)
VAR3 (UNOP_UNONE_UNONE, vclzq_u, v16qi, v8hi, v4si)
VAR3 (UNOP_UNONE_UNONE, vaddvq_u, v16qi, v8hi, v4si)
VAR2 (UNOP_UNONE_UNONE, vrev32q_u, v16qi, v8hi)
VAR2 (UNOP_UNONE_UNONE, vmovltq_u, v16qi, v8hi)
VAR2 (UNOP_UNONE_UNONE, vmovlbq_u, v16qi, v8hi)
VAR2 (UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si)
VAR2 (UNOP_UNONE_NONE, vcvtpq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_NONE, vcvtnq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_NONE, vcvtmq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si)
VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi)
VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si)
gcc/config/arm/constraints.md
......@@ -49,6 +49,10 @@
(define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS"
"MVE FPCCR register")
(define_register_constraint "e" "TARGET_HAVE_MVE ? EVEN_REG : NO_REGS"
"MVE EVEN registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8},
@code{r10}, @code{r12}, @code{r14}")
(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
"The VFP registers @code{s0}-@code{s31}.")
......
gcc/config/arm/mve.md
......@@ -22,26 +22,55 @@
(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
(define_mode_iterator MVE_0 [V8HF V4SF])
(define_mode_iterator MVE_3 [V16QI V8HI])
(define_mode_iterator MVE_2 [V16QI V8HI V4SI])
(define_mode_iterator MVE_5 [V8HI V4SI])
(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S
VCVTQ_TO_F_U VMVNQ_N_S VMVNQ_N_U VREV64Q_S VREV64Q_U
VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S
VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S
VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U
VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S
VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S
VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
VADDLVQ_U])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
(V8HF "V8HI") (V4SF "V4SI")])
(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VMVNQ_N_S "s")
(VMVNQ_N_U "u") (VREV64Q_U "u") (VREV64Q_S "s")
(VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")])
(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
(VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
(VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
(VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
(VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
(VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
(VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
(VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
(VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
(VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
(VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
(VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")])
(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
(define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
(define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
......@@ -362,6 +391,228 @@
"vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;; [vqnegq_s])
;;
(define_insn "mve_vqnegq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VQNEGQ_S))
]
"TARGET_HAVE_MVE"
"vqneg.s%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vqabsq_s])
;;
(define_insn "mve_vqabsq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VQABSQ_S))
]
"TARGET_HAVE_MVE"
"vqabs.s%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vnegq_s])
;;
(define_insn "mve_vnegq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VNEGQ_S))
]
"TARGET_HAVE_MVE"
"vneg.s%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vmvnq_u, vmvnq_s])
;;
(define_insn "mve_vmvnq_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VMVNQ))
]
"TARGET_HAVE_MVE"
"vmvn %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vdupq_n_u, vdupq_n_s])
;;
(define_insn "mve_vdupq_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
VDUPQ_N))
]
"TARGET_HAVE_MVE"
"vdup.%#<V_sz_elem> %q0, %1"
[(set_attr "type" "mve_move")
])
;;
;; [vclzq_u, vclzq_s])
;;
(define_insn "mve_vclzq_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VCLZQ))
]
"TARGET_HAVE_MVE"
"vclz.i%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vclsq_s])
;;
(define_insn "mve_vclsq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VCLSQ_S))
]
"TARGET_HAVE_MVE"
"vcls.s%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vaddvq_s, vaddvq_u])
;;
(define_insn "mve_vaddvq_<supf><mode>"
[
(set (match_operand:SI 0 "s_register_operand" "=e")
(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
VADDVQ))
]
"TARGET_HAVE_MVE"
"vaddv.<supf>%#<V_sz_elem>\t%0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vabsq_s])
;;
(define_insn "mve_vabsq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VABSQ_S))
]
"TARGET_HAVE_MVE"
"vabs.s%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrev32q_u, vrev32q_s])
;;
(define_insn "mve_vrev32q_<supf><mode>"
[
(set (match_operand:MVE_3 0 "s_register_operand" "=w")
(unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
VREV32Q))
]
"TARGET_HAVE_MVE"
"vrev32.%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vmovltq_u, vmovltq_s])
;;
(define_insn "mve_vmovltq_<supf><mode>"
[
(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
(unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
VMOVLTQ))
]
"TARGET_HAVE_MVE"
"vmovlt.<supf>%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vmovlbq_s, vmovlbq_u])
;;
(define_insn "mve_vmovlbq_<supf><mode>"
[
(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
(unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
VMOVLBQ))
]
"TARGET_HAVE_MVE"
"vmovlb.<supf>%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtpq_s, vcvtpq_u])
;;
(define_insn "mve_vcvtpq_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
VCVTPQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtnq_s, vcvtnq_u])
;;
(define_insn "mve_vcvtnq_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
VCVTNQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtmq_s, vcvtmq_u])
;;
(define_insn "mve_vcvtmq_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
VCVTMQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtaq_u, vcvtaq_s])
;;
(define_insn "mve_vcvtaq_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
VCVTAQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vmvnq_n_u, vmvnq_n_s])
......@@ -376,3 +627,31 @@
"vmvn.i%#<V_sz_elem> %q0, %1"
[(set_attr "type" "mve_move")
])
;;
;; [vrev16q_u, vrev16q_s])
;;
(define_insn "mve_vrev16q_<supf>v16qi"
[
(set (match_operand:V16QI 0 "s_register_operand" "=w")
(unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
VREV16Q))
]
"TARGET_HAVE_MVE"
"vrev16.8 %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vaddlvq_s vaddlvq_u])
;;
(define_insn "mve_vaddlvq_<supf>v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
VADDLVQ))
]
"TARGET_HAVE_MVE"
"vaddlv.<supf>32 %Q0, %R0, %q1"
[(set_attr "type" "mve_move")
])
gcc/testsuite/ChangeLog
2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabsq_s16.c: New test.
* gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise.
2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
* gcc.target/arm/multilib.exp: Add new v8.1-M entry.
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a)
{
return vabsq_s16 (a);
}
/* { dg-final { scan-assembler "vabs.s16" } } */
int16x8_t
foo1 (int16x8_t a)
{
return vabsq (a);
}
/* { dg-final { scan-assembler "vabs.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a)
{
return vabsq_s32 (a);
}
/* { dg-final { scan-assembler "vabs.s32" } } */
int32x4_t
foo1 (int32x4_t a)
{
return vabsq (a);
}
/* { dg-final { scan-assembler "vabs.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a)
{
return vabsq_s8 (a);
}
/* { dg-final { scan-assembler "vabs.s8" } } */
int8x16_t
foo1 (int8x16_t a)
{
return vabsq (a);
}
/* { dg-final { scan-assembler "vabs.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int32x4_t a)
{
return vaddlvq_s32 (a);
}
/* { dg-final { scan-assembler "vaddlv.s32" } } */
int64_t
foo1 (int32x4_t a)
{
return vaddlvq_s32 (a);
}
/* { dg-final { scan-assembler "vaddlv.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint64_t
foo (uint32x4_t a)
{
return vaddlvq_u32 (a);
}
/* { dg-final { scan-assembler "vaddlv.u32" } } */
uint64_t
foo1 (uint32x4_t a)
{
return vaddlvq (a);
}
/* { dg-final { scan-assembler "vaddlv.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32_t
foo (int16x8_t a)
{
return vaddvq_s16 (a);
}
/* { dg-final { scan-assembler "vaddv.s16" } } */
int32_t
foo1 (int16x8_t a)
{
return vaddvq_s16 (a);
}
/* { dg-final { scan-assembler "vaddv.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32_t
foo (int32x4_t a)
{
return vaddvq_s32 (a);
}
/* { dg-final { scan-assembler "vaddv.s32" } } */
int32_t
foo1 (int32x4_t a)
{
return vaddvq_s32 (a);
}
/* { dg-final { scan-assembler "vaddv.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32_t
foo (int8x16_t a)
{
return vaddvq_s8 (a);
}
/* { dg-final { scan-assembler "vaddv.s8" } } */
int32_t
foo1 (int8x16_t a)
{
return vaddvq (a);
}
/* { dg-final { scan-assembler "vaddv.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint16x8_t a)
{
return vaddvq_u16 (a);
}
/* { dg-final { scan-assembler "vaddv.u16" } } */
uint32_t
foo1 (uint16x8_t a)
{
return vaddvq (a);
}
/* { dg-final { scan-assembler "vaddv.u16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32x4_t a)
{
return vaddvq_u32 (a);
}
/* { dg-final { scan-assembler "vaddv.u32" } } */
uint32_t
foo1 (uint32x4_t a)
{
return vaddvq (a);
}
/* { dg-final { scan-assembler "vaddv.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint8x16_t a)
{
return vaddvq_u8 (a);
}
/* { dg-final { scan-assembler "vaddv.u8" } } */
uint32_t
foo1 (uint8x16_t a)
{
return vaddvq (a);
}
/* { dg-final { scan-assembler "vaddv.u8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a)
{
return vclsq_s16 (a);
}
/* { dg-final { scan-assembler "vcls.s16" } } */
int16x8_t
foo1 (int16x8_t a)
{
return vclsq (a);
}
/* { dg-final { scan-assembler "vcls.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a)
{
return vclsq_s32 (a);
}
/* { dg-final { scan-assembler "vcls.s32" } } */
int32x4_t
foo1 (int32x4_t a)
{
return vclsq (a);
}
/* { dg-final { scan-assembler "vcls.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a)
{
return vclsq_s8 (a);
}
/* { dg-final { scan-assembler "vcls.s8" } } */
int8x16_t
foo1 (int8x16_t a)
{
return vclsq (a);
}
/* { dg-final { scan-assembler "vcls.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a)
{
return vclzq_s16 (a);
}
/* { dg-final { scan-assembler "vclz.i16" } } */
int16x8_t
foo1 (int16x8_t a)
{
return vclzq (a);
}
/* { dg-final { scan-assembler "vclz.i16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a)
{
return vclzq_s32 (a);
}
/* { dg-final { scan-assembler "vclz.i32" } } */
int32x4_t
foo1 (int32x4_t a)
{
return vclzq (a);
}
/* { dg-final { scan-assembler "vclz.i32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a)
{
return vclzq_s8 (a);
}
/* { dg-final { scan-assembler "vclz.i8" } } */
int8x16_t
foo1 (int8x16_t a)
{
return vclzq (a);
}
/* { dg-final { scan-assembler "vclz.i8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t a)
{
return vclzq_u16 (a);
}
/* { dg-final { scan-assembler "vclz.i16" } } */
uint16x8_t
foo1 (uint16x8_t a)
{
return vclzq (a);
}
/* { dg-final { scan-assembler "vclz.i16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t a)
{
return vclzq_u32 (a);
}
/* { dg-final { scan-assembler "vclz.i32" } } */
uint32x4_t
foo1 (uint32x4_t a)
{
return vclzq (a);
}
/* { dg-final { scan-assembler "vclz.i32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t a)
{
return vclzq_u8 (a);
}
/* { dg-final { scan-assembler "vclz.i8" } } */
uint8x16_t
foo1 (uint8x16_t a)
{
return vclzq (a);
}
/* { dg-final { scan-assembler "vclz.i8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (float16x8_t a)
{
return vcvtaq_s16_f16 (a);
}
/* { dg-final { scan-assembler "vcvta.s16.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (float32x4_t a)
{
return vcvtaq_s32_f32 (a);
}
/* { dg-final { scan-assembler "vcvta.s32.f32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (float16x8_t a)
{
return vcvtaq_u16_f16 (a);
}
/* { dg-final { scan-assembler "vcvta.u16.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (float32x4_t a)
{
return vcvtaq_u32_f32 (a);
}
/* { dg-final { scan-assembler "vcvta.u32.f32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (float16x8_t a)
{
return vcvtmq_s16_f16 (a);
}
/* { dg-final { scan-assembler "vcvtm.s16.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (float32x4_t a)
{
return vcvtmq_s32_f32 (a);
}
/* { dg-final { scan-assembler "vcvtm.s32.f32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (float16x8_t a)
{
return vcvtmq_u16_f16 (a);
}
/* { dg-final { scan-assembler "vcvtm.u16.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (float32x4_t a)
{
return vcvtmq_u32_f32 (a);
}
/* { dg-final { scan-assembler "vcvtm.u32.f32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (float16x8_t a)
{
return vcvtnq_s16_f16 (a);
}
/* { dg-final { scan-assembler "vcvtn.s16.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (float32x4_t a)
{
return vcvtnq_s32_f32 (a);
}
/* { dg-final { scan-assembler "vcvtn.s32.f32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (float16x8_t a)
{
return vcvtnq_u16_f16 (a);
}
/* { dg-final { scan-assembler "vcvtn.u16.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (float16x8_t a)
{
return vcvtpq_s16_f16 (a);
}
/* { dg-final { scan-assembler "vcvtp.s16.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (float32x4_t a)
{
return vcvtpq_s32_f32 (a);
}
/* { dg-final { scan-assembler "vcvtp.s32.f32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (float16x8_t a)
{
return vcvtpq_u16_f16 (a);
}
/* { dg-final { scan-assembler "vcvtp.u16.f16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (float32x4_t a)
{
return vcvtpq_u32_f32 (a);
}
/* { dg-final { scan-assembler "vcvtp.u32.f32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16_t a)
{
return vdupq_n_s16 (a);
}
/* { dg-final { scan-assembler "vdup.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32_t a)
{
return vdupq_n_s32 (a);
}
/* { dg-final { scan-assembler "vdup.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8_t a)
{
return vdupq_n_s8 (a);
}
/* { dg-final { scan-assembler "vdup.8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16_t a)
{
return vdupq_n_u16 (a);
}
/* { dg-final { scan-assembler "vdup.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32_t a)
{
return vdupq_n_u32 (a);
}
/* { dg-final { scan-assembler "vdup.32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8_t a)
{
return vdupq_n_u8 (a);
}
/* { dg-final { scan-assembler "vdup.8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int16x8_t a)
{
return vmovlbq_s16 (a);
}
/* { dg-final { scan-assembler "vmovlb.s16" } } */
int32x4_t
foo1 (int16x8_t a)
{
return vmovlbq (a);
}
/* { dg-final { scan-assembler "vmovlb.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int8x16_t a)
{
return vmovlbq_s8 (a);
}
/* { dg-final { scan-assembler "vmovlb.s8" } } */
int16x8_t
foo1 (int8x16_t a)
{
return vmovlbq (a);
}
/* { dg-final { scan-assembler "vmovlb.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint16x8_t a)
{
return vmovlbq_u16 (a);
}
/* { dg-final { scan-assembler "vmovlb.u16" } } */
uint32x4_t
foo1 (uint16x8_t a)
{
return vmovlbq (a);
}
/* { dg-final { scan-assembler "vmovlb.u16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint8x16_t a)
{
return vmovlbq_u8 (a);
}
/* { dg-final { scan-assembler "vmovlb.u8" } } */
uint16x8_t
foo1 (uint8x16_t a)
{
return vmovlbq (a);
}
/* { dg-final { scan-assembler "vmovlb.u8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int16x8_t a)
{
return vmovltq_s16 (a);
}
/* { dg-final { scan-assembler "vmovlt.s16" } } */
int32x4_t
foo1 (int16x8_t a)
{
return vmovltq (a);
}
/* { dg-final { scan-assembler "vmovlt.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int8x16_t a)
{
return vmovltq_s8 (a);
}
/* { dg-final { scan-assembler "vmovlt.s8" } } */
int16x8_t
foo1 (int8x16_t a)
{
return vmovltq (a);
}
/* { dg-final { scan-assembler "vmovlt.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint16x8_t a)
{
return vmovltq_u16 (a);
}
/* { dg-final { scan-assembler "vmovlt.u16" } } */
uint32x4_t
foo1 (uint16x8_t a)
{
return vmovltq (a);
}
/* { dg-final { scan-assembler "vmovlt.u16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint8x16_t a)
{
return vmovltq_u8 (a);
}
/* { dg-final { scan-assembler "vmovlt.u8" } } */
uint16x8_t
foo1 (uint8x16_t a)
{
return vmovltq (a);
}
/* { dg-final { scan-assembler "vmovlt.u8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a)
{
return vmvnq_s16 (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
int16x8_t
foo1 (int16x8_t a)
{
return vmvnq (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a)
{
return vmvnq_s32 (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
int32x4_t
foo1 (int32x4_t a)
{
return vmvnq (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a)
{
return vmvnq_s8 (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
int8x16_t
foo1 (int8x16_t a)
{
return vmvnq (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t a)
{
return vmvnq_u16 (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
uint16x8_t
foo1 (uint16x8_t a)
{
return vmvnq (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t a)
{
return vmvnq_u32 (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
uint32x4_t
foo1 (uint32x4_t a)
{
return vmvnq (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t a)
{
return vmvnq_u8 (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
uint8x16_t
foo1 (uint8x16_t a)
{
return vmvnq (a);
}
/* { dg-final { scan-assembler "vmvn" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a)
{
return vnegq_s16 (a);
}
/* { dg-final { scan-assembler "vneg.s16" } } */
int16x8_t
foo1 (int16x8_t a)
{
return vnegq (a);
}
/* { dg-final { scan-assembler "vneg.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a)
{
return vnegq_s32 (a);
}
/* { dg-final { scan-assembler "vneg.s32" } } */
int32x4_t
foo1 (int32x4_t a)
{
return vnegq (a);
}
/* { dg-final { scan-assembler "vneg.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a)
{
return vnegq_s8 (a);
}
/* { dg-final { scan-assembler "vneg.s8" } } */
int8x16_t
foo1 (int8x16_t a)
{
return vnegq (a);
}
/* { dg-final { scan-assembler "vneg.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a)
{
return vqabsq_s16 (a);
}
/* { dg-final { scan-assembler "vqabs.s16" } } */
int16x8_t
foo1 (int16x8_t a)
{
return vqabsq (a);
}
/* { dg-final { scan-assembler "vqabs.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a)
{
return vqabsq_s32 (a);
}
/* { dg-final { scan-assembler "vqabs.s32" } } */
int32x4_t
foo1 (int32x4_t a)
{
return vqabsq (a);
}
/* { dg-final { scan-assembler "vqabs.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a)
{
return vqabsq_s8 (a);
}
/* { dg-final { scan-assembler "vqabs.s8" } } */
int8x16_t
foo1 (int8x16_t a)
{
return vqabsq (a);
}
/* { dg-final { scan-assembler "vqabs.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a)
{
return vqnegq_s16 (a);
}
/* { dg-final { scan-assembler "vqneg.s16" } } */
int16x8_t
foo1 (int16x8_t a)
{
return vqnegq (a);
}
/* { dg-final { scan-assembler "vqneg.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a)
{
return vqnegq_s32 (a);
}
/* { dg-final { scan-assembler "vqneg.s32" } } */
int32x4_t
foo1 (int32x4_t a)
{
return vqnegq (a);
}
/* { dg-final { scan-assembler "vqneg.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a)
{
return vqnegq_s8 (a);
}
/* { dg-final { scan-assembler "vqneg.s8" } } */
int8x16_t
foo1 (int8x16_t a)
{
return vqnegq (a);
}
/* { dg-final { scan-assembler "vqneg.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a)
{
return vrev16q_s8 (a);
}
/* { dg-final { scan-assembler "vrev16.8" } } */
int8x16_t
foo1 (int8x16_t a)
{
return vrev16q (a);
}
/* { dg-final { scan-assembler "vrev16.8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t a)
{
return vrev16q_u8 (a);
}
/* { dg-final { scan-assembler "vrev16.8" } } */
uint8x16_t
foo1 (uint8x16_t a)
{
return vrev16q (a);
}
/* { dg-final { scan-assembler "vrev16.8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a)
{
return vrev32q_s16 (a);
}
/* { dg-final { scan-assembler "vrev32.16" } } */
int16x8_t
foo1 (int16x8_t a)
{
return vrev32q (a);
}
/* { dg-final { scan-assembler "vrev32.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a)
{
return vrev32q_s8 (a);
}
/* { dg-final { scan-assembler "vrev32.8" } } */
int8x16_t
foo1 (int8x16_t a)
{
return vrev32q (a);
}
/* { dg-final { scan-assembler "vrev32.8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t a)
{
return vrev32q_u16 (a);
}
/* { dg-final { scan-assembler "vrev32.16" } } */
uint16x8_t
foo1 (uint16x8_t a)
{
return vrev32q (a);
}
/* { dg-final { scan-assembler "vrev32.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t a)
{
return vrev32q_u8 (a);
}
/* { dg-final { scan-assembler "vrev32.8" } } */
uint8x16_t
foo1 (uint8x16_t a)
{
return vrev32q (a);
}
/* { dg-final { scan-assembler "vrev32.8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
......@@ -16,7 +16,7 @@ foo (int16x8_t a)
int16x8_t
foo1 (int16x8_t a)
{
return vrev64q_s16 (a);
return vrev64q (a);
}
/* { dg-final { scan-assembler "vrev64.16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
......@@ -16,7 +16,7 @@ foo (int32x4_t a)
int32x4_t
foo1 (int32x4_t a)
{
return vrev64q_s32 (a);
return vrev64q (a);
}
/* { dg-final { scan-assembler "vrev64.32" } } */
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