Commit 6dac2e8e by Uros Bizjak

alpha.md (smaxsf3): Disable for IEEE mode.

	* config/alpha/alpha.md (smaxsf3): Disable for IEEE mode.
	(sminsf3): Ditto.

From-SVN: r151709
parent 07471115
2009-09-15 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/alpha.md (smaxsf3): Disable for IEEE mode.
(sminsf3): Ditto.
2009-09-14 DJ Delorie <dj@redhat.com> 2009-09-14 DJ Delorie <dj@redhat.com>
* config/mep/mep.h (JUMP_TABLES_IN_TEXT_SECTION): Define. * config/mep/mep.h (JUMP_TABLES_IN_TEXT_SECTION): Define.
* config/mep/mep.c (mep_emit_cbranch): Don't use BEQZ/BNEI in
* config/mep/mep.c (mep_emit_cbranch): Don't use BEQZ/BNEI in VLIW VLIW mode.
mode.
2009-09-14 Richard Henderson <rth@redhat.com> 2009-09-14 Richard Henderson <rth@redhat.com>
Jakub Jelinek <jakub@redhat.com> Jakub Jelinek <jakub@redhat.com>
...@@ -550,6 +554,7 @@ ...@@ -550,6 +554,7 @@
* config/bfin/bfin.c (bfin_expand_builtin, * config/bfin/bfin.c (bfin_expand_builtin,
case BFIN_BUILTIN_MULT_1X32X32): Force constants to registers for the case BFIN_BUILTIN_MULT_1X32X32): Force constants to registers for the
operands. operands.
From Jie Zhang <jie.zhang@analog.com>: From Jie Zhang <jie.zhang@analog.com>:
* config/bfin/bfin.c (bfin_expand_builtin): Initialize icodes * config/bfin/bfin.c (bfin_expand_builtin): Initialize icodes
before use in two places. before use in two places.
......
...@@ -3863,7 +3863,7 @@ ...@@ -3863,7 +3863,7 @@
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(if_then_else:SF (eq (match_dup 3) (match_dup 4)) (if_then_else:SF (eq (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"TARGET_FP" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
{ {
operands[3] = gen_reg_rtx (DFmode); operands[3] = gen_reg_rtx (DFmode);
operands[4] = CONST0_RTX (DFmode); operands[4] = CONST0_RTX (DFmode);
...@@ -3876,7 +3876,7 @@ ...@@ -3876,7 +3876,7 @@
(set (match_operand:SF 0 "register_operand" "") (set (match_operand:SF 0 "register_operand" "")
(if_then_else:SF (ne (match_dup 3) (match_dup 4)) (if_then_else:SF (ne (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))] (match_dup 1) (match_dup 2)))]
"TARGET_FP" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
{ {
operands[3] = gen_reg_rtx (DFmode); operands[3] = gen_reg_rtx (DFmode);
operands[4] = CONST0_RTX (DFmode); operands[4] = CONST0_RTX (DFmode);
......
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