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lvzhengyang
riscv-gcc-1
Commits
6d5363fa
Commit
6d5363fa
authored
May 13, 1993
by
Richard Stallman
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(combined mult/arithmetic recognizers): Switch on.
Add special pattern for reload. From-SVN: r4442
parent
0d4d8174
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37 additions
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18 deletions
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-18
gcc/config/arm/arm.md
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gcc/config/arm/arm.md
View file @
6d5363fa
...
@@ -686,7 +686,7 @@
...
@@ -686,7 +686,7 @@
;; storehi is not allowed.
;; storehi is not allowed.
(define_expand "restorehi"
(define_expand "restorehi"
[
(set (mem:QI (match_operand 1 "" ""))
[
(set (mem:QI (match_operand
:SI
1 "" ""))
(match_dup 2))
(match_dup 2))
(set (reg:SI 10)
(set (reg:SI 10)
(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
...
@@ -705,12 +705,12 @@
...
@@ -705,12 +705,12 @@
(define_expand "storehi"
(define_expand "storehi"
[
;; store the low byte
[
;; store the low byte
(set (mem:QI (match_operand 1 "" "")) (match_dup 3))
(set (mem:QI (match_operand
:SI
1 "" "")) (match_dup 3))
;; extract the high byte
;; extract the high byte
(set (match_dup 2)
(set (match_dup 2)
(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
;; store the high byte
;; store the high byte
(set (mem:QI (plus (match_dup 1) (const_int 1)))
(set (mem:QI (plus
:SI
(match_dup 1) (const_int 1)))
(subreg:QI (match_dup 2) 0))] ;explicit subreg safe
(subreg:QI (match_dup 2) 0))] ;explicit subreg safe
""
""
"
"
...
@@ -724,9 +724,9 @@
...
@@ -724,9 +724,9 @@
(define_expand "storeinthi"
(define_expand "storeinthi"
[
;; store the low byte
[
;; store the low byte
(set (mem:QI (match_operand 1 "" "")) (match_operand 0 "" ""))
(set (mem:QI (match_operand
:SI
1 "" "")) (match_operand 0 "" ""))
;; store the high byte
;; store the high byte
(set (mem:QI (plus (match_dup 1) (const_int 1)))
(set (mem:QI (plus
:SI
(match_dup 1) (const_int 1)))
(match_dup 2))]
(match_dup 2))]
""
""
"
"
...
@@ -1248,7 +1248,7 @@
...
@@ -1248,7 +1248,7 @@
; return (output_arithmetic_with_shift (operands, TRUE, FALSE));
; return (output_arithmetic_with_shift (operands, TRUE, FALSE));
;")
;")
;; Patterns to allow combination of arithmetic and
multiplication
;; Patterns to allow combination of arithmetic and
left shift
;(define_insn ""
;(define_insn ""
;
[
(set (match_operand:SI 0 "register_operand" "=r")
;
[
(set (match_operand:SI 0 "register_operand" "=r")
...
@@ -1262,18 +1262,37 @@
...
@@ -1262,18 +1262,37 @@
; return (output_arithmetic_with_immediate_multiply (operands, FALSE));
; return (output_arithmetic_with_immediate_multiply (operands, FALSE));
;")
;")
; Uncomment this to show combiner problem (see ../COMBINER-PROBLEM).
(define_insn ""
;(define_insn ""
[
(set (match_operand:SI 0 "register_operand" "=r")
;
[
(set (match_operand:SI 0 "register_operand" "=r")
(match_operator:SI 1 "shiftable_operator"
; (match_operator:SI 1 "shiftable_operator"
[
(mult:SI
;
[
(mult:SI
(match_operand:SI 3 "register_operand" "r")
; (match_operand:SI 3 "register_operand" "r")
(match_operand:SI 4 "power_of_two_operand" "n"))
; (match_operand:SI 4 "power_of_two_operand" "n"))
(match_operand:SI 2 "register_operand" "r")]))]
; (match_operand:SI 2 "register_operand" "r")]))]
""
; ""
"
*
; "
*
return (output_arithmetic_with_immediate_multiply (operands, TRUE));
; return (output_arithmetic_with_immediate_multiply (operands, TRUE));
")
;")
;; This variant of the above insn can occur if the first operand is the
;; frame pointer and we eliminate that. This is a kludge, but there doesn't
;; seem to be a way around it.
(define_insn ""
[
(set (match_operand:SI 0 "register_operand" "=&r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 3 "register_operand" "r")
(match_operand:SI 4 "power_of_two_operand" "n"))
(match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 1 "const_int_operand" "n")))]
"reload_in_progress"
"
*
{
int shift = int_log2 (INTVAL (operands
[
4
]
));
operands
[
4
]
= GEN_INT (shift);
arm_output_asm_insn (
\"
add
\\
t%0, %2, %3, asl#%4
\"
, operands);
operands
[
2
]
= operands
[
0
]
;
return output_add_immediate (operands);
}")
;; Peephole optimizations.
;; Peephole optimizations.
...
...
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