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riscv-gcc-1
Commit 6adcf89d by Uros Bizjak Committed by Uros Bizjak
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i386.md (*fyl2x_sfxf3, [...]): Remove insn definition. 

        * config/i386/i386.md (*fyl2x_sfxf3, *fyl2x_dfxf3): Remove insn
        definition.
        (log?f2, log10?f2, log2?f2): Reimplement expanders with
        float_truncate insn.
        (*fxtractsf3, *fxtractdf3): Remove insn definition.
        (logb?f2): Reimplement expanders with float_truncate insn.

From-SVN: r81432
parent 834eb1f0
Showing with 110 additions and 98 deletions
gcc/ChangeLog
2004-05-03 Uros Bizjak <uros@kss-loka.si>
* config/i386/i386.md (*fyl2x_sfxf3, *fyl2x_dfxf3): Remove insn
definition.
(log?f2, log10?f2, log2?f2): Reimplement expanders with
float_truncate insn.
(*fxtractsf3, *fxtractdf3): Remove insn definition.
(logb?f2): Reimplement expanders with float_truncate insn.
2004-05-03 Graham Stott <graham.stott@btinternet.com> 2004-05-03 Graham Stott <graham.stott@btinternet.com>
PR 14718 PR 14718
......
gcc/config/i386/i386.md
...@@ -15458,30 +15458,6 @@ ...@@ -15458,30 +15458,6 @@
emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
}) })
(define_insn "*fyl2x_sfxf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 2 "register_operand" "0")
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2X))
(clobber (match_scratch:SF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
(define_insn "*fyl2x_dfxf3"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 2 "register_operand" "0")
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2X))
(clobber (match_scratch:DF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")])
(define_insn "*fyl2x_xf3" (define_insn "*fyl2x_xf3"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0") (unspec:XF [(match_operand:XF 2 "register_operand" "0")
...@@ -15495,33 +15471,47 @@ ...@@ -15495,33 +15471,47 @@
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
(define_expand "logsf2" (define_expand "logsf2"
[(parallel [(set (match_operand:SF 0 "register_operand" "") [(set (match_dup 2)
(unspec:SF [(match_operand:SF 1 "register_operand" "") (float_extend:XF (match_operand:SF 1 "register_operand" "")))
(match_dup 2)] UNSPEC_FYL2X)) (parallel [(set (match_dup 4)
(clobber (match_scratch:SF 3 ""))])] (unspec:XF [(match_dup 2)
(match_dup 3)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (4); /* fldln2 */ temp = standard_80387_constant_rtx (4); /* fldln2 */
emit_move_insn (operands[2], temp); emit_move_insn (operands[3], temp);
}) })
(define_expand "logdf2" (define_expand "logdf2"
[(parallel [(set (match_operand:DF 0 "register_operand" "") [(set (match_dup 2)
(unspec:DF [(match_operand:DF 1 "register_operand" "") (float_extend:XF (match_operand:DF 1 "register_operand" "")))
(match_dup 2)] UNSPEC_FYL2X)) (parallel [(set (match_dup 4)
(clobber (match_scratch:DF 3 ""))])] (unspec:XF [(match_dup 2)
(match_dup 3)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (4); /* fldln2 */ temp = standard_80387_constant_rtx (4); /* fldln2 */
emit_move_insn (operands[2], temp); emit_move_insn (operands[3], temp);
}) })
(define_expand "logxf2" (define_expand "logxf2"
...@@ -15540,33 +15530,47 @@ ...@@ -15540,33 +15530,47 @@
}) })
(define_expand "log10sf2" (define_expand "log10sf2"
[(parallel [(set (match_operand:SF 0 "register_operand" "") [(set (match_dup 2)
(unspec:SF [(match_operand:SF 1 "register_operand" "") (float_extend:XF (match_operand:SF 1 "register_operand" "")))
(match_dup 2)] UNSPEC_FYL2X)) (parallel [(set (match_dup 4)
(clobber (match_scratch:SF 3 ""))])] (unspec:XF [(match_dup 2)
(match_dup 3)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (3); /* fldlg2 */ temp = standard_80387_constant_rtx (3); /* fldlg2 */
emit_move_insn (operands[2], temp); emit_move_insn (operands[3], temp);
}) })
(define_expand "log10df2" (define_expand "log10df2"
[(parallel [(set (match_operand:DF 0 "register_operand" "") [(set (match_dup 2)
(unspec:DF [(match_operand:DF 1 "register_operand" "") (float_extend:XF (match_operand:DF 1 "register_operand" "")))
(match_dup 2)] UNSPEC_FYL2X)) (parallel [(set (match_dup 4)
(clobber (match_scratch:DF 3 ""))])] (unspec:XF [(match_dup 2)
(match_dup 3)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (3); /* fldlg2 */ temp = standard_80387_constant_rtx (3); /* fldlg2 */
emit_move_insn (operands[2], temp); emit_move_insn (operands[3], temp);
}) })
(define_expand "log10xf2" (define_expand "log10xf2"
...@@ -15585,28 +15589,41 @@ ...@@ -15585,28 +15589,41 @@
}) })
(define_expand "log2sf2" (define_expand "log2sf2"
[(parallel [(set (match_operand:SF 0 "register_operand" "") [(set (match_dup 2)
(unspec:SF [(match_operand:SF 1 "register_operand" "") (float_extend:XF (match_operand:SF 1 "register_operand" "")))
(match_dup 2)] UNSPEC_FYL2X)) (parallel [(set (match_dup 4)
(clobber (match_scratch:SF 3 ""))])] (unspec:XF [(match_dup 2)
(match_dup 3)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
}) })
(define_expand "log2df2" (define_expand "log2df2"
[(parallel [(set (match_operand:DF 0 "register_operand" "") [(set (match_dup 2)
(unspec:DF [(match_operand:DF 1 "register_operand" "") (float_extend:XF (match_operand:DF 1 "register_operand" "")))
(match_dup 2)] UNSPEC_FYL2X)) (parallel [(set (match_dup 4)
(clobber (match_scratch:DF 3 ""))])] (unspec:XF [(match_dup 2)
(match_dup 3)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
}) })
(define_expand "log2xf2" (define_expand "log2xf2"
...@@ -15621,66 +15638,52 @@ ...@@ -15621,66 +15638,52 @@
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
}) })
(define_insn "*fxtractdf3" (define_insn "*fxtractxf3"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 2 "register_operand" "0")] (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
UNSPEC_XTRACT_FRACT)) UNSPEC_XTRACT_FRACT))
(set (match_operand:DF 1 "register_operand" "=u") (set (match_operand:XF 1 "register_operand" "=u")
(unspec:DF [(match_dup 2)] UNSPEC_XTRACT_EXP))] (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fxtract" "fxtract"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "DF")]) (set_attr "mode" "XF")])
(define_expand "logbdf2" (define_expand "logbsf2"
[(parallel [(set (match_dup 2) [(set (match_dup 2)
(unspec:DF [(match_operand:DF 1 "register_operand" "")] (float_extend:XF (match_operand:SF 1 "register_operand" "")))
UNSPEC_XTRACT_FRACT)) (parallel [(set (match_dup 3)
(set (match_operand:DF 0 "register_operand" "") (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
(unspec:DF [(match_dup 1)] UNSPEC_XTRACT_EXP))])] (set (match_dup 4)
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (DFmode); operands[2] = gen_reg_rtx (XFmode);
operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
}) })
(define_insn "*fxtractsf3" (define_expand "logbdf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_dup 2)
(unspec:SF [(match_operand:SF 2 "register_operand" "0")] (float_extend:XF (match_operand:DF 1 "register_operand" "")))
UNSPEC_XTRACT_FRACT)) (parallel [(set (match_dup 3)
(set (match_operand:SF 1 "register_operand" "=u") (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
(unspec:SF [(match_dup 2)] UNSPEC_XTRACT_EXP))] (set (match_dup 4)
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
&& flag_unsafe_math_optimizations" (set (match_operand:DF 0 "register_operand" "")
"fxtract" (float_truncate:DF (match_dup 4)))]
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
(define_expand "logbsf2"
[(parallel [(set (match_dup 2)
(unspec:SF [(match_operand:SF 1 "register_operand" "")]
UNSPEC_XTRACT_FRACT))
(set (match_operand:SF 0 "register_operand" "")
(unspec:SF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (SFmode); operands[2] = gen_reg_rtx (XFmode);
operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
}) })
(define_insn "*fxtractxf3"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")]
UNSPEC_XTRACT_FRACT))
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fxtract"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(define_expand "logbxf2" (define_expand "logbxf2"
[(parallel [(set (match_dup 2) [(parallel [(set (match_dup 2)
(unspec:XF [(match_operand:XF 1 "register_operand" "")] (unspec:XF [(match_operand:XF 1 "register_operand" "")]
......
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