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riscv-gcc-1
Commit 6a4bb1fa by Doug Evans
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Cosmetic changes only. Just reordered code a little. 

From-SVN: r5292
parent 25b5c537
Showing with 257 additions and 254 deletions
gcc/config/sparc/sparc.c
......@@ -62,6 +62,7 @@ char leaf_reg_remap[] =
48, 49, 50, 51, 52, 53, 54, 55,
56, 57, 58, 59, 60, 61, 62, 63};
#if 0 /* not used anymore */
char leaf_reg_backmap[] =
{ 0, 1, 2, 3, 4, 5, 6, 7,
24, 25, 26, 27, 28, 29, 14, 31,
......@@ -73,12 +74,13 @@ char leaf_reg_backmap[] =
48, 49, 50, 51, 52, 53, 54, 55,
56, 57, 58, 59, 60, 61, 62, 63};
#endif
#endif
/* Global variables set by FUNCTION_PROLOGUE. */
/* Size of frame. Need to know this to emit return insns from
leaf procedures. */
int apparent_fsize;
int actual_fsize;
static int apparent_fsize;
static int actual_fsize;
/* Name of where we pretend to think the frame pointer points.
Normally, this is "%fp", but if we are in a leaf procedure,
......@@ -271,46 +273,6 @@ move_pic_label (op, mode)
return 1;
return 0;
}
/* The rtx for the global offset table which is a special form
that *is* a position independent symbolic constant. */
rtx pic_pc_rtx;
/* Ensure that we are not using patterns that are not OK with PIC. */
int
check_pic (i)
int i;
{
switch (flag_pic)
{
case 1:
if (GET_CODE (recog_operand[i]) == SYMBOL_REF
|| (GET_CODE (recog_operand[i]) == CONST
&& ! rtx_equal_p (pic_pc_rtx, recog_operand[i])))
abort ();
case 2:
default:
return 1;
}
}
/* Return true if X is an address which needs a temporary register when
reloaded while generating PIC code. */
int
pic_address_needs_scratch (x)
rtx x;
{
/* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
&& ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
return 1;
return 0;
}
int
memop (op, mode)
......@@ -621,6 +583,46 @@ reg_unused_after (reg, insn)
return 1;
}
/* The rtx for the global offset table which is a special form
that *is* a position independent symbolic constant. */
static rtx pic_pc_rtx;
/* Ensure that we are not using patterns that are not OK with PIC. */
int
check_pic (i)
int i;
{
switch (flag_pic)
{
case 1:
if (GET_CODE (recog_operand[i]) == SYMBOL_REF
|| (GET_CODE (recog_operand[i]) == CONST
&& ! rtx_equal_p (pic_pc_rtx, recog_operand[i])))
abort ();
case 2:
default:
return 1;
}
}
/* Return true if X is an address which needs a temporary register when
reloaded while generating PIC code. */
int
pic_address_needs_scratch (x)
rtx x;
{
/* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
&& ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
return 1;
return 0;
}
/* Legitimize PIC addresses. If the address is already position-independent,
we return ORIG. Newly generated position-independent addresses go into a
reg. This is REG if non zero, otherwise we allocate register(s) as
......@@ -1526,6 +1528,8 @@ find_addr_reg (addr)
abort ();
}
#if 0 /* not currently used */
void
output_sized_memop (opname, mode, signedp)
char *opname;
......@@ -1560,6 +1564,7 @@ output_move_with_extension (operands)
else
abort ();
}
#endif /* not currently used */
#if 0
/* ??? These are only used by the movstrsi pattern, but we get better code
......
gcc/config/sparc/sparc.h
......@@ -519,7 +519,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
normally.
We put %f0/%f1 last among the float registers, so as to make it more
likely that a pseduo-register which dies in the float return register
likely that a pseudo-register which dies in the float return register
will get allocated to the float return register, thus saving a move
instruction at the end of the function. */
#define REG_ALLOC_ORDER \
......@@ -886,10 +886,6 @@ do { \
ASM_OUTPUT_LABEL (FILE, NAME); \
} while (0)
/* Two views of the size of the current frame. */
extern int actual_fsize;
extern int apparent_fsize;
/* This macro generates the assembly code for function entry.
FILE is a stdio stream to output the code to.
SIZE is an int: how many units of temporary storage to allocate.
......@@ -978,7 +974,7 @@ extern union tree_node *current_function_decl;
#define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
(TARGET_FRW ? sparc_frw_eligible_for_epilogue_delay (trial, slots_filled) \
: eligible_for_epilogue_delay (trial, slots_filled))
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts. */
......@@ -1040,7 +1036,7 @@ extern union tree_node *current_function_decl;
emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
}
/* Generate necessary RTL for __builtin_saveregs().
ARGLIST is the argument list; see expr.c. */
extern struct rtx_def *sparc_builtin_saveregs ();
......
gcc/config/sparc/sparc.md
......@@ -772,6 +772,88 @@
;; Move instructions
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" ""))]
""
"
{
if (emit_move_sequence (operands, QImode))
DONE;
}")
(define_insn ""
[(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q")
(match_operand:QI 1 "move_operand" "rI,K,Q,rJ"))]
"register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode)
|| operands[1] == const0_rtx"
"@
mov %1,%0
sethi %%hi(%a1),%0
ldub %1,%0
stb %r1,%0"
[(set_attr "type" "move,move,load,store")
(set_attr "length" "*,1,*,1")])
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r")
(subreg:QI (lo_sum:SI (match_operand:QI 1 "register_operand" "r")
(match_operand 2 "immediate_operand" "in")) 0))]
""
"or %1,%%lo(%a2),%0"
[(set_attr "length" "1")])
(define_insn ""
[(set (mem:QI (match_operand:SI 0 "symbolic_operand" ""))
(match_operand:QI 1 "reg_or_0_operand" "rJ"))
(clobber (match_scratch:SI 2 "=&r"))]
""
"sethi %%hi(%a0),%2\;stb %r1,[%2+%%lo(%a0)]"
[(set_attr "type" "store")
(set_attr "length" "2")])
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))]
""
"
{
if (emit_move_sequence (operands, HImode))
DONE;
}")
(define_insn ""
[(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q")
(match_operand:HI 1 "move_operand" "rI,K,Q,rJ"))]
"register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode)
|| operands[1] == const0_rtx"
"@
mov %1,%0
sethi %%hi(%a1),%0
lduh %1,%0
sth %r1,%0"
[(set_attr "type" "move,move,load,store")
(set_attr "length" "*,1,*,1")])
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(lo_sum:HI (match_operand:HI 1 "register_operand" "r")
(match_operand 2 "immediate_operand" "in")))]
""
"or %1,%%lo(%a2),%0"
[(set_attr "length" "1")])
(define_insn ""
[(set (mem:HI (match_operand:SI 0 "symbolic_operand" ""))
(match_operand:HI 1 "reg_or_0_operand" "rJ"))
(clobber (match_scratch:SI 2 "=&r"))]
""
"sethi %%hi(%a0),%2\;sth %r1,[%2+%%lo(%a0)]"
[(set_attr "type" "store")
(set_attr "length" "2")])
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" ""))]
......@@ -883,23 +965,6 @@
[(set_attr "type" "move")
(set_attr "length" "1")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "immediate_operand" "in")))]
""
"*
{
/* Don't output a 64 bit constant, since we can't trust the assembler to
handle it correctly. */
if (GET_CODE (operands[2]) == CONST_DOUBLE)
operands[2] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[2]));
return \"or %R1,%%lo(%a2),%R0\";
}"
;; Need to set length for this arith insn because operand2
;; is not an "arith_operand".
[(set_attr "length" "1")])
;; For PIC, symbol_refs are put inside unspec so that the optimizer won't
;; confuse them with real addresses.
(define_insn ""
......@@ -912,6 +977,8 @@
;; is not an "arith_operand".
[(set_attr "length" "1")])
;; ??? Can the next two be moved above the PIC stuff?
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
......@@ -931,87 +998,51 @@
[(set_attr "type" "store")
(set_attr "length" "2")])
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))]
(define_expand "movdi"
[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
(match_operand:DI 1 "general_operand" ""))]
""
"
{
if (emit_move_sequence (operands, HImode))
if (emit_move_sequence (operands, DImode))
DONE;
}")
(define_insn ""
[(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q")
(match_operand:HI 1 "move_operand" "rI,K,Q,rJ"))]
"register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode)
[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "=r,Q,r,r,?f,?f,?Q")
(match_operand:DI 1 "general_operand" "r,r,Q,i,f,Q,f"))]
"register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode)
|| operands[1] == const0_rtx"
"@
mov %1,%0
sethi %%hi(%a1),%0
lduh %1,%0
sth %r1,%0"
[(set_attr "type" "move,move,load,store")
(set_attr "length" "*,1,*,1")])
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(lo_sum:HI (match_operand:HI 1 "register_operand" "r")
(match_operand 2 "immediate_operand" "in")))]
""
"or %1,%%lo(%a2),%0"
[(set_attr "length" "1")])
(define_insn ""
[(set (mem:HI (match_operand:SI 0 "symbolic_operand" ""))
(match_operand:HI 1 "reg_or_0_operand" "rJ"))
(clobber (match_scratch:SI 2 "=&r"))]
""
"sethi %%hi(%a0),%2\;sth %r1,[%2+%%lo(%a0)]"
[(set_attr "type" "store")
(set_attr "length" "2")])
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" ""))]
""
"
"*
{
if (emit_move_sequence (operands, QImode))
DONE;
}")
(define_insn ""
[(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q")
(match_operand:QI 1 "move_operand" "rI,K,Q,rJ"))]
"register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode)
|| operands[1] == const0_rtx"
"@
mov %1,%0
sethi %%hi(%a1),%0
ldub %1,%0
stb %r1,%0"
[(set_attr "type" "move,move,load,store")
(set_attr "length" "*,1,*,1")])
if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
return output_fp_move_double (operands);
return output_move_double (operands);
}"
[(set_attr "type" "move,store,load,multi,fp,fpload,fpstore")
(set_attr "length" "2,3,3,3,2,3,3")])
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r")
(subreg:QI (lo_sum:SI (match_operand:QI 1 "register_operand" "r")
(match_operand 2 "immediate_operand" "in")) 0))]
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "immediate_operand" "in")))]
""
"or %1,%%lo(%a2),%0"
"*
{
/* Don't output a 64 bit constant, since we can't trust the assembler to
handle it correctly. */
if (GET_CODE (operands[2]) == CONST_DOUBLE)
operands[2] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[2]));
return \"or %R1,%%lo(%a2),%R0\";
}"
;; Need to set length for this arith insn because operand2
;; is not an "arith_operand".
[(set_attr "length" "1")])
(define_insn ""
[(set (mem:QI (match_operand:SI 0 "symbolic_operand" ""))
(match_operand:QI 1 "reg_or_0_operand" "rJ"))
(clobber (match_scratch:SI 2 "=&r"))]
""
"sethi %%hi(%a0),%2\;stb %r1,[%2+%%lo(%a0)]"
[(set_attr "type" "store")
(set_attr "length" "2")])
;; ??? There's no symbolic (set (mem:DI ...) ...).
;; Block move insns.
;; ??? We get better code without it. See output_block_move in sparc.c.
......@@ -1062,91 +1093,78 @@
;; Floating point move insns
;; This pattern forces (set (reg:TF ...) (const_double ...))
;; This pattern forces (set (reg:SF ...) (const_double ...))
;; to be reloaded by putting the constant into memory.
;; It must come before the more general movtf pattern.
;; It must come before the more general movsf pattern.
(define_insn ""
[(set (match_operand:TF 0 "general_operand" "=?r,f,o")
(match_operand:TF 1 "" "?E,m,G"))]
[(set (match_operand:SF 0 "general_operand" "=?r,f,m")
(match_operand:SF 1 "" "?E,m,G"))]
"TARGET_FPU && GET_CODE (operands[1]) == CONST_DOUBLE"
"*
{
switch (which_alternative)
{
case 0:
return output_move_quad (operands);
return singlemove_string (operands);
case 1:
return output_fp_move_quad (operands);
return \"ld %1,%0\";
case 2:
operands[1] = adj_offsettable_operand (operands[0], 4);
operands[2] = adj_offsettable_operand (operands[0], 8);
operands[3] = adj_offsettable_operand (operands[0], 12);
return \"st %%g0,%0\;st %%g0,%1\;st %%g0,%2\;st %%g0,%3\";
return \"st %%g0,%0\";
}
}"
[(set_attr "type" "load,fpload,store")
(set_attr "length" "5,5,5")])
(set_attr "length" "2,1,1")])
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")
(match_operand:TF 1 "general_operand" ""))]
(define_expand "movsf"
[(set (match_operand:SF 0 "general_operand" "")
(match_operand:SF 1 "general_operand" ""))]
""
"
{
if (emit_move_sequence (operands, TFmode))
if (emit_move_sequence (operands, SFmode))
DONE;
}")
(define_insn ""
[(set (match_operand:TF 0 "reg_or_nonsymb_mem_operand" "=f,r,Q,Q,f,&r")
(match_operand:TF 1 "reg_or_nonsymb_mem_operand" "f,r,f,r,Q,Q"))]
[(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" "=f,r,f,r,Q,Q")
(match_operand:SF 1 "reg_or_nonsymb_mem_operand" "f,r,Q,Q,f,r"))]
"TARGET_FPU
&& (register_operand (operands[0], TFmode)
|| register_operand (operands[1], TFmode))"
"*
{
if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
return output_fp_move_quad (operands);
return output_move_quad (operands);
}"
[(set_attr "type" "fp,move,fpstore,store,fpload,load")
(set_attr "length" "4,4,5,5,5,5")])
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))"
"@
fmovs %1,%0
mov %1,%0
ld %1,%0
ld %1,%0
st %r1,%0
st %r1,%0"
[(set_attr "type" "fp,move,fpload,load,fpstore,store")])
;; Exactly the same as above, except that all `f' cases are deleted.
;; This is necessary to prevent reload from ever trying to use a `f' reg
;; when -mno-fpu.
(define_insn ""
[(set (match_operand:TF 0 "reg_or_nonsymb_mem_operand" "=r,Q,&r")
(match_operand:TF 1 "reg_or_nonsymb_mem_operand" "r,r,Q"))]
[(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" "=r,r,Q")
(match_operand:SF 1 "reg_or_nonsymb_mem_operand" "r,Q,r"))]
"! TARGET_FPU
&& (register_operand (operands[0], TFmode)
|| register_operand (operands[1], TFmode))"
"*
{
if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
return output_fp_move_quad (operands);
return output_move_quad (operands);
}"
[(set_attr "type" "move,store,load")
(set_attr "length" "4,5,5")])
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))"
"@
mov %1,%0
ld %1,%0
st %r1,%0"
[(set_attr "type" "move,load,store")])
(define_insn ""
[(set (mem:TF (match_operand:SI 0 "symbolic_operand" "i,i"))
(match_operand:TF 1 "reg_or_0_operand" "rf,G"))
(clobber (match_scratch:SI 2 "=&r,&r"))]
[(set (mem:SF (match_operand:SI 0 "symbolic_operand" "i"))
(match_operand:SF 1 "reg_or_0_operand" "rfG"))
(clobber (match_scratch:SI 2 "=&r"))]
""
"*
{
output_asm_insn (\"sethi %%hi(%a0),%2\", operands);
if (which_alternative == 0)
return \"std %1,[%2+%%lo(%a0)]\;std %S1,[%2+%%lo(%a0+8)]\";
else
return \"st %%g0,[%2+%%lo(%a0)]\;st %%g0,[%2+%%lo(%a0+4)]\; st %%g0,[%2+%%lo(%a0+8)]\;st %%g0,[%2+%%lo(%a0+12)]\";
}"
"sethi %%hi(%a0),%2\;st %r1,[%2+%%lo(%a0)]"
[(set_attr "type" "store")
(set_attr "length" "5")])
(set_attr "length" "2")])
;; This pattern forces (set (reg:DF ...) (const_double ...))
;; to be reloaded by putting the constant into memory.
;; It must come before the more general movdf pattern.
......@@ -1237,107 +1255,91 @@
}"
[(set_attr "type" "store")
(set_attr "length" "3")])
;; Double-word move insns.
(define_expand "movdi"
[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
(match_operand:DI 1 "general_operand" ""))]
""
"
{
if (emit_move_sequence (operands, DImode))
DONE;
}")
(define_insn ""
[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "=r,Q,r,r,?f,?f,?Q")
(match_operand:DI 1 "general_operand" "r,r,Q,i,f,Q,f"))]
"register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode)
|| operands[1] == const0_rtx"
"*
{
if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
return output_fp_move_double (operands);
return output_move_double (operands);
}"
[(set_attr "type" "move,store,load,multi,fp,fpload,fpstore")
(set_attr "length" "2,3,3,3,2,3,3")])
;; Floating-point move insns.
;; This pattern forces (set (reg:SF ...) (const_double ...))
;; This pattern forces (set (reg:TF ...) (const_double ...))
;; to be reloaded by putting the constant into memory.
;; It must come before the more general movsf pattern.
;; It must come before the more general movtf pattern.
(define_insn ""
[(set (match_operand:SF 0 "general_operand" "=?r,f,m")
(match_operand:SF 1 "" "?E,m,G"))]
[(set (match_operand:TF 0 "general_operand" "=?r,f,o")
(match_operand:TF 1 "" "?E,m,G"))]
"TARGET_FPU && GET_CODE (operands[1]) == CONST_DOUBLE"
"*
{
switch (which_alternative)
{
case 0:
return singlemove_string (operands);
return output_move_quad (operands);
case 1:
return \"ld %1,%0\";
return output_fp_move_quad (operands);
case 2:
return \"st %%g0,%0\";
operands[1] = adj_offsettable_operand (operands[0], 4);
operands[2] = adj_offsettable_operand (operands[0], 8);
operands[3] = adj_offsettable_operand (operands[0], 12);
return \"st %%g0,%0\;st %%g0,%1\;st %%g0,%2\;st %%g0,%3\";
}
}"
[(set_attr "type" "load,fpload,store")
(set_attr "length" "2,1,1")])
(set_attr "length" "5,5,5")])
(define_expand "movsf"
[(set (match_operand:SF 0 "general_operand" "")
(match_operand:SF 1 "general_operand" ""))]
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")
(match_operand:TF 1 "general_operand" ""))]
""
"
{
if (emit_move_sequence (operands, SFmode))
if (emit_move_sequence (operands, TFmode))
DONE;
}")
(define_insn ""
[(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" "=f,r,f,r,Q,Q")
(match_operand:SF 1 "reg_or_nonsymb_mem_operand" "f,r,Q,Q,f,r"))]
[(set (match_operand:TF 0 "reg_or_nonsymb_mem_operand" "=f,r,Q,Q,f,&r")
(match_operand:TF 1 "reg_or_nonsymb_mem_operand" "f,r,f,r,Q,Q"))]
"TARGET_FPU
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))"
"@
fmovs %1,%0
mov %1,%0
ld %1,%0
ld %1,%0
st %r1,%0
st %r1,%0"
[(set_attr "type" "fp,move,fpload,load,fpstore,store")])
&& (register_operand (operands[0], TFmode)
|| register_operand (operands[1], TFmode))"
"*
{
if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
return output_fp_move_quad (operands);
return output_move_quad (operands);
}"
[(set_attr "type" "fp,move,fpstore,store,fpload,load")
(set_attr "length" "4,4,5,5,5,5")])
;; Exactly the same as above, except that all `f' cases are deleted.
;; This is necessary to prevent reload from ever trying to use a `f' reg
;; when -mno-fpu.
(define_insn ""
[(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" "=r,r,Q")
(match_operand:SF 1 "reg_or_nonsymb_mem_operand" "r,Q,r"))]
[(set (match_operand:TF 0 "reg_or_nonsymb_mem_operand" "=r,Q,&r")
(match_operand:TF 1 "reg_or_nonsymb_mem_operand" "r,r,Q"))]
"! TARGET_FPU
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))"
"@
mov %1,%0
ld %1,%0
st %r1,%0"
[(set_attr "type" "move,load,store")])
&& (register_operand (operands[0], TFmode)
|| register_operand (operands[1], TFmode))"
"*
{
if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
return output_fp_move_quad (operands);
return output_move_quad (operands);
}"
[(set_attr "type" "move,store,load")
(set_attr "length" "4,5,5")])
(define_insn ""
[(set (mem:SF (match_operand:SI 0 "symbolic_operand" "i"))
(match_operand:SF 1 "reg_or_0_operand" "rfG"))
(clobber (match_scratch:SI 2 "=&r"))]
[(set (mem:TF (match_operand:SI 0 "symbolic_operand" "i,i"))
(match_operand:TF 1 "reg_or_0_operand" "rf,G"))
(clobber (match_scratch:SI 2 "=&r,&r"))]
""
"sethi %%hi(%a0),%2\;st %r1,[%2+%%lo(%a0)]"
"*
{
output_asm_insn (\"sethi %%hi(%a0),%2\", operands);
if (which_alternative == 0)
return \"std %1,[%2+%%lo(%a0)]\;std %S1,[%2+%%lo(%a0+8)]\";
else
return \"st %%g0,[%2+%%lo(%a0)]\;st %%g0,[%2+%%lo(%a0+4)]\; st %%g0,[%2+%%lo(%a0+8)]\;st %%g0,[%2+%%lo(%a0+12)]\";
}"
[(set_attr "type" "store")
(set_attr "length" "2")])
(set_attr "length" "5")])
;;- zero extension instructions
......@@ -1913,8 +1915,8 @@
"TARGET_V8"
"wr %%g0,%%g0,%%y\;nop\;nop\;nop\;udivcc %1,%2,%0"
[(set_attr "length" "5")])
;;- and instructions
;;- Boolean instructions
;; We define DImode `and` so with DImode `not` we can get
;; DImode `andn`. Other combinations are possible.
......
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