Skip to content

R
riscv-gcc-1
Commit 683bdff7 by Fariborz Jahanian
Options

Separate TARGET_POWERPC64 patterns for TARGET_64BIT or TARGET_32BIT. 

Approved by David Edelsohn.

From-SVN: r72650
parent ad7e39ca
Showing with 265 additions and 188 deletions
gcc/config/rs6000/rs6000.md
......@@ -123,7 +123,7 @@
(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 2 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rldicl. %2,%1,0,56
#"
......@@ -149,7 +149,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(zero_extend:DI (match_dup 1)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rldicl. %0,%1,0,56
#"
......@@ -181,7 +181,7 @@
(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 2 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
extsb. %2,%1
#"
......@@ -207,7 +207,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(sign_extend:DI (match_dup 1)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
extsb. %0,%1
#"
......@@ -248,7 +248,7 @@
(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 2 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rldicl. %2,%1,0,48
#"
......@@ -274,7 +274,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(zero_extend:DI (match_dup 1)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rldicl. %0,%1,0,48
#"
......@@ -315,7 +315,7 @@
(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 2 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
extsh. %2,%1
#"
......@@ -341,7 +341,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(sign_extend:DI (match_dup 1)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
extsh. %0,%1
#"
......@@ -382,7 +382,7 @@
(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 2 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rldicl. %2,%1,0,32
#"
......@@ -408,7 +408,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(zero_extend:DI (match_dup 1)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rldicl. %0,%1,0,32
#"
......@@ -449,7 +449,7 @@
(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 2 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
extsw. %2,%1
#"
......@@ -475,7 +475,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(sign_extend:DI (match_dup 1)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
extsw. %0,%1
#"
......@@ -2245,7 +2245,7 @@
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
#
{andil.|andi.} %3,%1,%b2
......@@ -2326,7 +2326,7 @@
(and:SI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
#
{andil.|andi.} %0,%1,%b2
......@@ -3223,7 +3223,7 @@
(match_operand:SI 3 "const_int_operand" "i"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"*
{
int start = INTVAL (operands[3]) & 63;
......@@ -3245,7 +3245,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"*
{
int start = INTVAL (operands[3]) & 63;
......@@ -5242,7 +5242,7 @@
(define_expand "floatdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
if (!flag_unsafe_math_optimizations)
......@@ -5293,7 +5293,7 @@
(pc)))
(set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
(set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
operands[2] = gen_reg_rtx (DImode);
......@@ -5633,11 +5633,26 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "M,i")))]
"TARGET_32BIT && !TARGET_POWER"
"TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER"
"@
{srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
{sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
[(set_attr "length" "8,12")])
(define_insn "*ashrdisi3_noppc64"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(const_int 32)) 4))]
"TARGET_32BIT && !TARGET_POWERPC64"
"*
{
if (REGNO (operands[0]) == REGNO (operands[1]))
return \"\";
else
return \"mr %0,%1\";
}"
[(set_attr "length" "4")])
;; PowerPC64 DImode operations.
......@@ -5696,7 +5711,7 @@
(match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r,r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
add. %3,%1,%2
addic. %3,%1,%2
......@@ -5726,7 +5741,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
(plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
add. %0,%1,%2
addic. %0,%1,%2
......@@ -5792,7 +5807,7 @@
(compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 2 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
nor. %2,%1,%1
#"
......@@ -5818,7 +5833,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(not:DI (match_dup 1)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
nor. %0,%1,%1
#"
......@@ -5854,7 +5869,7 @@
(match_operand:DI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
subf. %3,%2,%1
#"
......@@ -5882,7 +5897,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(minus:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
subf. %0,%2,%1
#"
......@@ -5960,7 +5975,7 @@
(compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 2 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
neg. %2,%1
#"
......@@ -5986,7 +6001,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(neg:DI (match_dup 1)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
neg. %0,%1
#"
......@@ -6187,7 +6202,7 @@
(match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
sradi %3,%1,%p2\;addze. %3,%3
#"
......@@ -6215,7 +6230,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(div:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
sradi %0,%1,%p2\;addze. %0,%0
#"
......@@ -6266,7 +6281,7 @@
(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2cl. %3,%1,%H2,0
#"
......@@ -6294,7 +6309,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(rotate:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2cl. %0,%1,%H2,0
#"
......@@ -6332,7 +6347,7 @@
(match_operand:DI 3 "mask64_operand" "n,n"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2c%B3. %4,%1,%H2,%S3
#"
......@@ -6366,7 +6381,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2c%B3. %0,%1,%H2,%S3
#"
......@@ -6407,7 +6422,7 @@
(match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2cl. %3,%1,%H2,56
#"
......@@ -6441,7 +6456,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2cl. %0,%1,%H2,56
#"
......@@ -6482,7 +6497,7 @@
(match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2cl. %3,%1,%H2,48
#"
......@@ -6516,7 +6531,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2cl. %0,%1,%H2,48
#"
......@@ -6557,7 +6572,7 @@
(match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2cl. %3,%1,%H2,32
#"
......@@ -6591,7 +6606,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
rld%I2cl. %0,%1,%H2,32
#"
......@@ -6647,7 +6662,7 @@
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
sld%I2. %3,%1,%H2
#"
......@@ -6675,7 +6690,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(ashift:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
sld%I2. %0,%1,%H2
#"
......@@ -6713,7 +6728,7 @@
(match_operand:DI 3 "const_int_operand" "n,n"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=r,r"))]
"TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
"TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
"@
rldic. %4,%1,%H2,%W3
#"
......@@ -6747,7 +6762,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
"TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
"@
rldic. %0,%1,%H2,%W3
#"
......@@ -6789,7 +6804,7 @@
(match_operand:DI 3 "mask64_operand" "n,n"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=r,r"))]
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
"TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
"@
rldicr. %4,%1,%H2,%S3
#"
......@@ -6823,7 +6838,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
"TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
"@
rldicr. %0,%1,%H2,%S3
#"
......@@ -6880,7 +6895,7 @@
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT "
"@
srd%I2. %3,%1,%H2
#"
......@@ -6908,7 +6923,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(lshiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
srd%I2. %0,%1,%H2
#"
......@@ -6966,7 +6981,7 @@
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
srad%I2. %3,%1,%H2
#"
......@@ -6994,7 +7009,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
srad%I2. %0,%1,%H2
#"
......@@ -7058,7 +7073,7 @@
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
and. %3,%1,%2
rldic%B2. %3,%1,0,%S2
......@@ -7123,7 +7138,7 @@
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
(and:DI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
and. %0,%1,%2
rldic%B2. %0,%1,0,%S2
......@@ -7268,7 +7283,7 @@
(match_operand:DI 2 "gpc_reg_operand" "r,r")])
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
%q4. %3,%1,%2
#"
......@@ -7297,7 +7312,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(match_dup 4))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
%q4. %0,%1,%2
#"
......@@ -7368,7 +7383,7 @@
(match_operand:DI 2 "gpc_reg_operand" "r,r")])
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
%q4. %3,%2,%1
#"
......@@ -7397,7 +7412,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(match_dup 4))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
%q4. %0,%2,%1
#"
......@@ -7434,7 +7449,7 @@
(not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
%q4. %3,%1,%2
#"
......@@ -7463,7 +7478,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(match_dup 4))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
%q4. %0,%1,%2
#"
......@@ -7619,17 +7634,23 @@
operands2[0] = operands[0];
operands2[1] = operands[1];
operands2[2] = operands[2];
operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
#if TARGET_MACHO
if (MACHO_DYNAMIC_NO_PIC_P)
output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
if (TARGET_POWERPC64 && TARGET_32BIT)
/* Note, old assemblers didn't support relocation here. */
return \"ld %0,lo16(%2)(%1)\";
else
/* We cannot rely on ha16(low half)==ha16(high half), alas,
although in practice it almost always is. */
output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
{
operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
#if TARGET_MACHO
if (MACHO_DYNAMIC_NO_PIC_P)
output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
else
/* We cannot rely on ha16(low half)==ha16(high half), alas,
although in practice it almost always is. */
output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
#endif
return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
}
}
default:
abort();
......@@ -8644,7 +8665,7 @@
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
cmpdi %2,%0,0
mr. %0,%1
......@@ -8684,7 +8705,7 @@
[(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
(match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
(clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
"TARGET_POWER && ! TARGET_POWERPC64
"TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
{
......@@ -11538,7 +11559,7 @@
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
......@@ -11552,7 +11573,7 @@
(eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
(clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
subfic %3,%1,0\;adde %0,%3,%1
......@@ -11570,7 +11591,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
(eq:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
{sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
......@@ -11594,7 +11615,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "")
(eq:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 3 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(parallel [(set (match_dup 0)
(eq:SI (match_dup 1) (match_dup 2)))
(clobber (match_dup 3))])
......@@ -11612,7 +11633,7 @@
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
(eq:DI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
subfic %3,%1,0\;adde. %0,%3,%1
......@@ -11636,7 +11657,7 @@
(set (match_operand:DI 0 "gpc_reg_operand" "")
(eq:DI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(parallel [(set (match_dup 0)
(eq:DI (match_dup 1) (match_dup 2)))
(clobber (match_dup 3))])
......@@ -11665,7 +11686,7 @@
(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
{sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
......@@ -11683,7 +11704,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
{sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
......@@ -11707,7 +11728,7 @@
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 4)
(plus:SI (eq:SI (match_dup 1)
(match_dup 2))
......@@ -11727,7 +11748,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
{sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
......@@ -11752,7 +11773,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
......@@ -11764,7 +11785,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
......@@ -11780,7 +11801,7 @@
(lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
(const_int 31)))
(clobber (match_scratch:SI 2 "=&r"))]
"! TARGET_POWER && ! TARGET_POWERPC64 && !TARGET_ISEL"
"! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
"{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
[(set_attr "length" "8")])
......@@ -11789,7 +11810,7 @@
(lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
(const_int 63)))
(clobber (match_scratch:DI 2 "=&r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"addic %2,%1,-1\;subfe %0,%2,%1"
[(set_attr "length" "8")])
......@@ -11801,7 +11822,7 @@
(const_int 31))
(match_operand:SI 2 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 3 "=&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
[(set_attr "length" "8")])
......@@ -11812,7 +11833,7 @@
(const_int 63))
(match_operand:DI 2 "gpc_reg_operand" "r")))
(clobber (match_scratch:DI 3 "=&r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"addic %3,%1,-1\;addze %0,%2"
[(set_attr "length" "8")])
......@@ -11826,7 +11847,7 @@
(const_int 0)))
(clobber (match_scratch:SI 3 "=&r,&r"))
(clobber (match_scratch:SI 4 "=X,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
#"
......@@ -11843,7 +11864,7 @@
(const_int 0)))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:SI 4 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(parallel [(set (match_dup 3)
(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
(const_int 31))
......@@ -11863,7 +11884,7 @@
(match_operand:DI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=&r,&r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
addic %3,%1,-1\;addze. %3,%2
#"
......@@ -11879,7 +11900,7 @@
(match_operand:DI 2 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(set (match_dup 3)
(plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
(const_int 63))
......@@ -11901,7 +11922,7 @@
(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
(match_dup 2)))
(clobber (match_scratch:SI 3 "=&r,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
#"
......@@ -11920,7 +11941,7 @@
(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
(match_dup 2)))
(clobber (match_scratch:SI 3 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(parallel [(set (match_dup 0)
(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
(match_dup 2)))
......@@ -11942,7 +11963,7 @@
(plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
(match_dup 2)))
(clobber (match_scratch:DI 3 "=&r,&r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
addic %3,%1,-1\;addze. %0,%2
#"
......@@ -11961,7 +11982,7 @@
(plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
(match_dup 2)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(parallel [(set (match_dup 0)
(plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
(match_dup 2)))
......@@ -12120,7 +12141,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
[(set_attr "length" "12")])
......@@ -12132,7 +12153,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(leu:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
#"
......@@ -12147,7 +12168,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(leu:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(leu:DI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
......@@ -12163,7 +12184,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(leu:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
#"
......@@ -12178,7 +12199,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(leu:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(leu:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
......@@ -12194,7 +12215,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(leu:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
#"
......@@ -12206,7 +12227,7 @@
(plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
[(set_attr "length" "8")])
......@@ -12218,7 +12239,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
#"
......@@ -12233,7 +12254,7 @@
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 4)
(plus:SI (leu:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
......@@ -12251,7 +12272,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
#"
......@@ -12267,7 +12288,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
......@@ -12279,7 +12300,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
[(set_attr "length" "12")])
......@@ -12289,7 +12310,7 @@
(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
[(set_attr "length" "12")])
......@@ -12302,7 +12323,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
#"
......@@ -12318,7 +12339,7 @@
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 4)
(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
(match_dup 3)))
......@@ -12337,7 +12358,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
#"
......@@ -12354,7 +12375,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
(match_dup 3)))
......@@ -12488,7 +12509,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
......@@ -12502,7 +12523,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(ltu:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
......@@ -12519,7 +12540,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(ltu:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(ltu:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
......@@ -12532,7 +12553,7 @@
(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
(match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
......@@ -12546,7 +12567,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
......@@ -12563,7 +12584,7 @@
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 4)
(plus:SI (ltu:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
......@@ -12581,7 +12602,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
......@@ -12599,7 +12620,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
......@@ -12611,7 +12632,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
......@@ -12746,7 +12767,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
......@@ -12756,7 +12777,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
......@@ -12770,7 +12791,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(geu:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
......@@ -12787,7 +12808,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(geu:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(geu:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
......@@ -12803,7 +12824,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
(geu:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
......@@ -12820,7 +12841,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(geu:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(geu:DI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
......@@ -12833,7 +12854,7 @@
(plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
(match_operand:SI 3 "gpc_reg_operand" "r,r")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
{ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
......@@ -12847,7 +12868,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
{ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
......@@ -12864,7 +12885,7 @@
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 4)
(plus:SI (geu:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
......@@ -12882,7 +12903,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
{ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
......@@ -12900,7 +12921,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
......@@ -12912,7 +12933,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
{sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
......@@ -12924,7 +12945,7 @@
(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
(match_operand:SI 3 "gpc_reg_operand" "r,r")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
......@@ -12939,7 +12960,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
......@@ -12957,7 +12978,7 @@
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 4)
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
(match_dup 3)))
......@@ -12976,7 +12997,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
......@@ -12995,7 +13016,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
(set (match_dup 4)
......@@ -13007,7 +13028,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
[(set_attr "length" "12")])
......@@ -13015,7 +13036,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(const_int 0)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
[(set_attr "length" "12")])
......@@ -13027,7 +13048,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(gt:SI (match_dup 1) (const_int 0)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
#"
......@@ -13042,7 +13063,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(gt:SI (match_dup 1) (const_int 0)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(gt:SI (match_dup 1) (const_int 0)))
(set (match_dup 2)
......@@ -13058,7 +13079,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(gt:DI (match_dup 1) (const_int 0)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
#"
......@@ -13073,7 +13094,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(gt:DI (match_dup 1) (const_int 0)))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(gt:DI (match_dup 1) (const_int 0)))
(set (match_dup 2)
......@@ -13125,7 +13146,7 @@
(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))
(match_operand:SI 2 "gpc_reg_operand" "r")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
[(set_attr "length" "12")])
......@@ -13134,7 +13155,7 @@
(plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(const_int 0))
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
[(set_attr "length" "12")])
......@@ -13146,7 +13167,7 @@
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=&r,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
#"
......@@ -13161,7 +13182,7 @@
(match_operand:SI 2 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 3)
(plus:SI (gt:SI (match_dup 1) (const_int 0))
(match_dup 2)))
......@@ -13178,7 +13199,7 @@
(match_operand:DI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=&r,&r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
#"
......@@ -13193,7 +13214,7 @@
(match_operand:DI 2 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(set (match_dup 3)
(plus:DI (gt:DI (match_dup 1) (const_int 0))
(match_dup 2)))
......@@ -13211,7 +13232,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
#"
......@@ -13227,7 +13248,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
(set (match_dup 3)
......@@ -13244,7 +13265,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
#"
......@@ -13260,7 +13281,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
(set (match_dup 3)
......@@ -13345,7 +13366,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
......@@ -13353,7 +13374,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(const_int 0))))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
[(set_attr "length" "12")])
......@@ -13369,7 +13390,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
[(set_attr "length" "12")])
......@@ -13377,7 +13398,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
[(set_attr "length" "12")])
......@@ -13389,7 +13410,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(gtu:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
#"
......@@ -13404,7 +13425,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(gtu:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(gtu:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
......@@ -13420,7 +13441,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(gtu:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
#"
......@@ -13435,7 +13456,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(gtu:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(gtu:DI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
......@@ -13448,7 +13469,7 @@
(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "I,rI"))
(match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
......@@ -13459,7 +13480,7 @@
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_short_operand" "I,rI"))
(match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
addic %0,%1,%k2\;addze %0,%3
subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
......@@ -13473,7 +13494,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
......@@ -13490,7 +13511,7 @@
(match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 4)
(plus:SI (gtu:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
......@@ -13507,7 +13528,7 @@
(match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
addic %4,%1,%k2\;addze. %4,%3
subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
......@@ -13524,7 +13545,7 @@
(match_operand:DI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 4 ""))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(set (match_dup 4)
(plus:DI (gtu:DI (match_dup 1) (match_dup 2))
(match_dup 3)))
......@@ -13542,7 +13563,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"@
{ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
......@@ -13560,7 +13581,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"! TARGET_POWERPC64 && reload_completed"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
......@@ -13577,7 +13598,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"@
addic %0,%1,%k2\;addze. %0,%3
subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
......@@ -13595,7 +13616,7 @@
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
......@@ -13607,7 +13628,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "8")])
......@@ -13615,7 +13636,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI"))))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;subfe %0,%0,%0"
[(set_attr "length" "8")])
......@@ -13923,7 +13944,7 @@
/* Only use this on innermost loops. */
if (INTVAL (operands[3]) > 1)
FAIL;
if (TARGET_POWERPC64)
if (TARGET_64BIT)
{
if (GET_MODE (operands[0]) != DImode)
FAIL;
......@@ -13949,7 +13970,7 @@
(const_int -1)))
(clobber (match_scratch:CC 2 ""))
(clobber (match_scratch:SI 3 ""))])]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"")
(define_expand "ctrdi"
......@@ -13963,7 +13984,7 @@
(const_int -1)))
(clobber (match_scratch:CC 2 ""))
(clobber (match_scratch:DI 3 ""))])]
"TARGET_POWERPC64"
"TARGET_64BIT"
"")
;; We need to be able to do this for any operand, including MEM, or we
......@@ -13983,7 +14004,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"*
{
if (which_alternative != 0)
......@@ -14007,7 +14028,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"*
{
if (which_alternative != 0)
......@@ -14031,7 +14052,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"*
{
if (which_alternative != 0)
......@@ -14055,7 +14076,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"*
{
if (which_alternative != 0)
......@@ -14081,7 +14102,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
if (which_alternative != 0)
......@@ -14105,7 +14126,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
if (which_alternative != 0)
......@@ -14129,7 +14150,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
if (which_alternative != 0)
......@@ -14153,7 +14174,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
if (which_alternative != 0)
......@@ -14179,7 +14200,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"*
{
if (which_alternative != 0)
......@@ -14203,7 +14224,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64"
"TARGET_32BIT"
"*
{
if (which_alternative != 0)
......@@ -14227,7 +14248,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"*
{
if (which_alternative != 0)
......@@ -14251,7 +14272,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64"
"TARGET_64BIT"
"*
{
if (which_alternative != 0)
......@@ -14333,7 +14354,7 @@
(const_int -1)))
(clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:DI 4 ""))]
"TARGET_POWERPC64 && reload_completed"
"TARGET_64BIT && reload_completed"
[(parallel [(set (match_dup 3)
(compare:CC (plus:DI (match_dup 1)
(const_int -1))
......@@ -14359,7 +14380,7 @@
(plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:DI 4 ""))]
"TARGET_POWERPC64 && reload_completed
"TARGET_64BIT && reload_completed
&& ! gpc_reg_operand (operands[0], DImode)"
[(parallel [(set (match_dup 3)
(compare:CC (plus:DI (match_dup 1)
......@@ -14377,6 +14398,62 @@
{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx); }")
; These two are for 64-bit hardware running 32-bit mode.
; We don't use the add. instruction in this mode.
(define_split
[(set (pc)
(if_then_else (match_operator 2 "comparison_operator"
[(match_operand:SI 1 "gpc_reg_operand" "")
(const_int 1)])
(match_operand 5 "" "")
(match_operand 6 "" "")))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:SI 4 ""))]
"TARGET_POWERPC64 && TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(plus:SI (match_dup 1)
(const_int -1)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))
(set (pc) (if_then_else (match_dup 7)
(match_dup 5)
(match_dup 6)))]
"
{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx); }")
(define_split
[(set (pc)
(if_then_else (match_operator 2 "comparison_operator"
[(match_operand:SI 1 "gpc_reg_operand" "")
(const_int 1)])
(match_operand 5 "" "")
(match_operand 6 "" "")))
(set (match_operand:SI 0 "nonimmediate_operand" "")
(plus:SI (match_dup 1) (const_int -1)))
(clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:SI 4 ""))]
"TARGET_POWERPC64 && TARGET_32BIT && reload_completed
&& ! gpc_reg_operand (operands[0], SImode)"
[(set (match_dup 4)
(plus:SI (match_dup 1)
(const_int -1)))
(set (match_dup 3)
(compare:CC (match_dup 4)
(const_int 0)))
(set (match_dup 0)
(match_dup 4))
(set (pc) (if_then_else (match_dup 7)
(match_dup 5)
(match_dup 6)))]
"
{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx); }")
(define_insn "trap"
[(trap_if (const_int 1) (const_int 0))]
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment