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Commit 680dd104 by Jan Hubicka Committed by Jan Hubicka
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i386.md: FIx typo. 


	* i386.md: FIx typo.
	(sse2_cvtsi2sd, sse2_pslrdq): Fix template.
	(sse2_umulv2siv2di3): Fix predicate.
	(sse2_psadbw, ashrv8hi3, ashrv4si3, lshrv8hi3 lshrv4si3,
	lshrv2di3, ashlv8hi3, ashlv4si3, ashlv2di3): Likewise.
	* xmmintrin.h (_mm_mul_epu16): Rename to...
	(_mm_mul_epu32): This one.
	(_mm_cvtsi32_si128, _mm_cvtsi128_si32): New.

	(contains_128bit_aligned_vector_p): Undo accidental checkin.

From-SVN: r58421
parent 3aabf9a5
Showing with 44 additions and 18 deletions
gcc/ChangeLog
Tue Oct 22 23:51:34 CEST 2002 Jan Hubicka <jh@suse.cz>
* i386.md: FIx typo.
(sse2_cvtsi2sd, sse2_pslrdq): Fix template.
(sse2_umulv2siv2di3): Fix predicate.
(sse2_psadbw, ashrv8hi3, ashrv4si3, lshrv8hi3 lshrv4si3,
lshrv2di3, ashlv8hi3, ashlv4si3, ashlv2di3): Likewise.
* xmmintrin.h (_mm_mul_epu16): Rename to...
(_mm_mul_epu32): This one.
(_mm_cvtsi32_si128, _mm_cvtsi128_si32): New.
(contains_128bit_aligned_vector_p): Undo accidental checkin.
2002-10-22 Eric Christopher <echristo@redhat.com> 2002-10-22 Eric Christopher <echristo@redhat.com>
* config/sparc/sparc.h: Add #error. * config/sparc/sparc.h: Add #error.
......
gcc/config/i386/i386.c
...@@ -797,7 +797,6 @@ const struct attribute_spec ix86_attribute_table[]; ...@@ -797,7 +797,6 @@ const struct attribute_spec ix86_attribute_table[];
static tree ix86_handle_cdecl_attribute PARAMS ((tree *, tree, tree, int, bool *)); static tree ix86_handle_cdecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
static tree ix86_handle_regparm_attribute PARAMS ((tree *, tree, tree, int, bool *)); static tree ix86_handle_regparm_attribute PARAMS ((tree *, tree, tree, int, bool *));
static int ix86_value_regno PARAMS ((enum machine_mode)); static int ix86_value_regno PARAMS ((enum machine_mode));
static bool contains_128bit_aligned_vector_p PARAMS ((tree));
#if defined (DO_GLOBAL_CTORS_BODY) && defined (HAS_INIT_SECTION) #if defined (DO_GLOBAL_CTORS_BODY) && defined (HAS_INIT_SECTION)
static void ix86_svr3_asm_out_constructor PARAMS ((rtx, int)); static void ix86_svr3_asm_out_constructor PARAMS ((rtx, int));
......
gcc/config/i386/i386.md
...@@ -16862,7 +16862,7 @@ ...@@ -16862,7 +16862,7 @@
&& ix86_match_ccmode (insn, CCNOmode) && ix86_match_ccmode (insn, CCNOmode)
&& (GET_MODE (operands[0]) == HImode && (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode || (GET_MODE (operands[0]) == QImode
/* Ensure that the operand will remain sign extended immedaite. */ /* Ensure that the operand will remain sign extended immediate. */
&& INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) >= 0
&& (TARGET_PROMOTE_QImode || optimize_size)))" && (TARGET_PROMOTE_QImode || optimize_size)))"
[(parallel [(set (reg:CCNO 17) [(parallel [(set (reg:CCNO 17)
...@@ -20685,7 +20685,7 @@ ...@@ -20685,7 +20685,7 @@
(match_operand:SI 2 "nonimmediate_operand" "rm"))) (match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 2)))] (const_int 2)))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtsd2si\t{%2, %0|%0, %2}" "cvtsi2sd\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
...@@ -20935,14 +20935,14 @@ ...@@ -20935,14 +20935,14 @@
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_insn "sse2_umulv2siv2di3" (define_insn "sse2_umulv2siv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=y") [(set (match_operand:V2DI 0 "register_operand" "=x")
(mult:V2DI (zero_extend:V2DI (mult:V2DI (zero_extend:V2DI
(vec_select:V2SI (vec_select:V2SI
(match_operand:V4SI 1 "register_operand" "0") (match_operand:V4SI 1 "register_operand" "0")
(parallel [(const_int 0) (const_int 2)]))) (parallel [(const_int 0) (const_int 2)])))
(zero_extend:V2DI (zero_extend:V2DI
(vec_select:V2SI (vec_select:V2SI
(match_operand:V4SI 2 "nonimmediate_operand" "ym") (match_operand:V4SI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (const_int 2)])))))] (parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE2" "TARGET_SSE2"
"pmuludq\t{%2, %0|%0, %2}" "pmuludq\t{%2, %0|%0, %2}"
...@@ -20996,7 +20996,7 @@ ...@@ -20996,7 +20996,7 @@
(ashiftrt:V16QI (ashiftrt:V16QI
(plus:V16QI (plus:V16QI (plus:V16QI (plus:V16QI
(match_operand:V16QI 1 "register_operand" "0") (match_operand:V16QI 1 "register_operand" "0")
(match_operand:V16QI 2 "nonimmediate_operand" "ym")) (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
(const_vector:V16QI [(const_int 1) (const_int 1) (const_vector:V16QI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1) (const_int 1) (const_int 1)
(const_int 1) (const_int 1) (const_int 1) (const_int 1)
...@@ -21016,7 +21016,7 @@ ...@@ -21016,7 +21016,7 @@
(ashiftrt:V8HI (ashiftrt:V8HI
(plus:V8HI (plus:V8HI (plus:V8HI (plus:V8HI
(match_operand:V8HI 1 "register_operand" "0") (match_operand:V8HI 1 "register_operand" "0")
(match_operand:V8HI 2 "nonimmediate_operand" "ym")) (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
(const_vector:V8HI [(const_int 1) (const_int 1) (const_vector:V8HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1) (const_int 1) (const_int 1)
(const_int 1) (const_int 1) (const_int 1) (const_int 1)
...@@ -21031,7 +21031,7 @@ ...@@ -21031,7 +21031,7 @@
(define_insn "sse2_psadbw" (define_insn "sse2_psadbw"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0") (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
(match_operand:V16QI 2 "nonimmediate_operand" "ym")] (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
UNSPEC_PSADBW))] UNSPEC_PSADBW))]
"TARGET_SSE2" "TARGET_SSE2"
"psadbw\t{%2, %0|%0, %2}" "psadbw\t{%2, %0|%0, %2}"
...@@ -21194,7 +21194,7 @@ ...@@ -21194,7 +21194,7 @@
(define_insn "ashrv8hi3" (define_insn "ashrv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=x")
(ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "ri")))] (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2" "TARGET_SSE2"
"psraw\t{%2, %0|%0, %2}" "psraw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -21203,7 +21203,7 @@ ...@@ -21203,7 +21203,7 @@
(define_insn "ashrv4si3" (define_insn "ashrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "ri")))] (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2" "TARGET_SSE2"
"psrad\t{%2, %0|%0, %2}" "psrad\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -21212,7 +21212,7 @@ ...@@ -21212,7 +21212,7 @@
(define_insn "lshrv8hi3" (define_insn "lshrv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=x")
(lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "ri")))] (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2" "TARGET_SSE2"
"psrlw\t{%2, %0|%0, %2}" "psrlw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -21221,7 +21221,7 @@ ...@@ -21221,7 +21221,7 @@
(define_insn "lshrv4si3" (define_insn "lshrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "ri")))] (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2" "TARGET_SSE2"
"psrld\t{%2, %0|%0, %2}" "psrld\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -21230,7 +21230,7 @@ ...@@ -21230,7 +21230,7 @@
(define_insn "lshrv2di3" (define_insn "lshrv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0") (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "ri")))] (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2" "TARGET_SSE2"
"psrlq\t{%2, %0|%0, %2}" "psrlq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -21239,7 +21239,7 @@ ...@@ -21239,7 +21239,7 @@
(define_insn "ashlv8hi3" (define_insn "ashlv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=x")
(ashift:V8HI (match_operand:V8HI 1 "register_operand" "0") (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "ri")))] (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2" "TARGET_SSE2"
"psllw\t{%2, %0|%0, %2}" "psllw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -21248,7 +21248,7 @@ ...@@ -21248,7 +21248,7 @@
(define_insn "ashlv4si3" (define_insn "ashlv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "=x")
(ashift:V4SI (match_operand:V4SI 1 "register_operand" "0") (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "ri")))] (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2" "TARGET_SSE2"
"pslld\t{%2, %0|%0, %2}" "pslld\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -21257,7 +21257,7 @@ ...@@ -21257,7 +21257,7 @@
(define_insn "ashlv2di3" (define_insn "ashlv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "=x")
(ashift:V2DI (match_operand:V2DI 1 "register_operand" "0") (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "ri")))] (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2" "TARGET_SSE2"
"psllq\t{%2, %0|%0, %2}" "psllq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
...@@ -21357,7 +21357,7 @@ ...@@ -21357,7 +21357,7 @@
(mult:SI (match_operand:SI 2 "immediate_operand" "i") (mult:SI (match_operand:SI 2 "immediate_operand" "i")
(const_int 8)))] UNSPEC_NOP))] (const_int 8)))] UNSPEC_NOP))]
"TARGET_SSE2" "TARGET_SSE2"
"pslrdq\t{%2, %0|%0, %2}" "psrldq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft") [(set_attr "type" "sseishft")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
......
gcc/config/i386/xmmintrin.h
...@@ -2148,7 +2148,7 @@ _mm_mul_pu16 (__m64 __A, __m64 __B) ...@@ -2148,7 +2148,7 @@ _mm_mul_pu16 (__m64 __A, __m64 __B)
} }
static __inline __m128i static __inline __m128i
_mm_mul_epu16 (__m128i __A, __m128i __B) _mm_mul_epu32 (__m128i __A, __m128i __B)
{ {
return (__m128i)__builtin_ia32_pmuludq128 ((__v4si)__A, (__v4si)__B); return (__m128i)__builtin_ia32_pmuludq128 ((__v4si)__A, (__v4si)__B);
} }
...@@ -2435,6 +2435,20 @@ _mm_mfence (void) ...@@ -2435,6 +2435,20 @@ _mm_mfence (void)
__builtin_ia32_mfence (); __builtin_ia32_mfence ();
} }
static __inline __m128i
_mm_cvtsi32_si128 (int __A)
{
return (__m128i) __builtin_ia32_loadd (&__A);
}
static __inline int
_mm_cvtsi128_si32 (__m128i __A)
{
int __tmp;
__builtin_ia32_stored (&__tmp, (__v4si)__A);
return __tmp;
}
#endif /* __SSE2__ */ #endif /* __SSE2__ */
#endif /* __SSE__ */ #endif /* __SSE__ */
......
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