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Commit 66adb8eb by James Greenhalgh Committed by James Greenhalgh
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[AArch64] Fixup the vget_lane RTL patterns and intrinsics 

gcc/
	* config/aarch64/aarch64-simd-builtins.def (get_lane_signed): Remove.
	(get_lane_unsigned): Likewise.
	(dup_lane_scalar): Likewise.
	(get_lane): enable for VALL.
	* config/aarch64/aarch64-simd.md
	(aarch64_dup_lane_scalar<mode>): Remove.
	(aarch64_get_lane_signed<mode>): Likewise.
	(aarch64_get_lane_unsigned<mode>): Likewise.
	(aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): New.
	(aarch64_get_lane_zero_extendsi<mode>): Likewise.
	(aarch64_get_lane<mode>): Enable for all vector modes.
	(aarch64_get_lanedi): Remove misleading constraints.
	* config/aarch64/arm_neon.h
	(__aarch64_vget_lane_any): Define.
	(__aarch64_vget<q>_lane_<fpsu><8,16,32,64>): Likewise.
	(vget<q>_lane_<fpsu><8,16,32,64>): Use __aarch64_vget_lane macros.
	(vdup<bhsd>_lane_<su><8,16,32,64>): Likewise.
	* config/aarch64/iterators.md (VDQQH): New.
	(VDQQHS): Likewise.
	(vwcore): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/scalar_intrinsics.c: Update expected
	output of vdup intrinsics.

From-SVN: r201624
parent 23a6cb78
Showing with 74 additions and 42 deletions
gcc/ChangeLog
2013-08-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd-builtins.def (get_lane_signed): Remove.
(get_lane_unsigned): Likewise.
(dup_lane_scalar): Likewise.
(get_lane): enable for VALL.
* config/aarch64/aarch64-simd.md
(aarch64_dup_lane_scalar<mode>): Remove.
(aarch64_get_lane_signed<mode>): Likewise.
(aarch64_get_lane_unsigned<mode>): Likewise.
(aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): New.
(aarch64_get_lane_zero_extendsi<mode>): Likewise.
(aarch64_get_lane<mode>): Enable for all vector modes.
(aarch64_get_lanedi): Remove misleading constraints.
* config/aarch64/arm_neon.h
(__aarch64_vget_lane_any): Define.
(__aarch64_vget<q>_lane_<fpsu><8,16,32,64>): Likewise.
(vget<q>_lane_<fpsu><8,16,32,64>): Use __aarch64_vget_lane macros.
(vdup<bhsd>_lane_<su><8,16,32,64>): Likewise.
* config/aarch64/iterators.md (VDQQH): New.
(VDQQHS): Likewise.
(vwcore): Likewise.
2013-08-09 Eric Botcazou <ebotcazou@adacore.com> 2013-08-09 Eric Botcazou <ebotcazou@adacore.com>
* configure.ac: Add GAS check for LEON instructions on SPARC. * configure.ac: Add GAS check for LEON instructions on SPARC.
......
gcc/config/aarch64/aarch64-simd-builtins.def
...@@ -40,10 +40,6 @@ ...@@ -40,10 +40,6 @@
10 - CODE_FOR_<name><mode>. */ 10 - CODE_FOR_<name><mode>. */
BUILTIN_VD_RE (CREATE, create, 0) BUILTIN_VD_RE (CREATE, create, 0)
BUILTIN_VQ_S (GETLANE, get_lane_signed, 0)
BUILTIN_VDQ (GETLANE, get_lane_unsigned, 0)
BUILTIN_VDQF (GETLANE, get_lane, 0)
VAR1 (GETLANE, get_lane, 0, di)
BUILTIN_VDC (COMBINE, combine, 0) BUILTIN_VDC (COMBINE, combine, 0)
BUILTIN_VB (BINOP, pmul, 0) BUILTIN_VB (BINOP, pmul, 0)
BUILTIN_VDQF (UNOP, sqrt, 2) BUILTIN_VDQF (UNOP, sqrt, 2)
...@@ -51,6 +47,9 @@ ...@@ -51,6 +47,9 @@
VAR1 (UNOP, addp, 0, di) VAR1 (UNOP, addp, 0, di)
VAR1 (UNOP, clz, 2, v4si) VAR1 (UNOP, clz, 2, v4si)
BUILTIN_VALL (GETLANE, get_lane, 0)
VAR1 (GETLANE, get_lane, 0, di)
BUILTIN_VD_RE (REINTERP, reinterpretdi, 0) BUILTIN_VD_RE (REINTERP, reinterpretdi, 0)
BUILTIN_VDC (REINTERP, reinterpretv8qi, 0) BUILTIN_VDC (REINTERP, reinterpretv8qi, 0)
BUILTIN_VDC (REINTERP, reinterpretv4hi, 0) BUILTIN_VDC (REINTERP, reinterpretv4hi, 0)
...@@ -64,7 +63,6 @@ ...@@ -64,7 +63,6 @@
BUILTIN_VQ (REINTERP, reinterpretv2df, 0) BUILTIN_VQ (REINTERP, reinterpretv2df, 0)
BUILTIN_VDQ_I (BINOP, dup_lane, 0) BUILTIN_VDQ_I (BINOP, dup_lane, 0)
BUILTIN_VDQ_I (BINOP, dup_lane_scalar, 0)
/* Implemented by aarch64_<sur>q<r>shl<mode>. */ /* Implemented by aarch64_<sur>q<r>shl<mode>. */
BUILTIN_VSDQ_I (BINOP, sqshl, 0) BUILTIN_VSDQ_I (BINOP, sqshl, 0)
BUILTIN_VSDQ_I (BINOP, uqshl, 0) BUILTIN_VSDQ_I (BINOP, uqshl, 0)
......
gcc/config/aarch64/aarch64-simd.md
...@@ -357,20 +357,6 @@ ...@@ -357,20 +357,6 @@
(set_attr "simd_mode" "<MODE>")] (set_attr "simd_mode" "<MODE>")]
) )
(define_insn "aarch64_dup_lane_scalar<mode>"
[(set (match_operand:<VEL> 0 "register_operand" "=w, r")
(vec_select:<VEL>
(match_operand:VDQ 1 "register_operand" "w, w")
(parallel [(match_operand:SI 2 "immediate_operand" "i, i")])
))]
"TARGET_SIMD"
"@
dup\\t%<Vetype>0, %1.<Vetype>[%2]
umov\\t%<vw>0, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_dup, simd_movgp")
(set_attr "simd_mode" "<MODE>")]
)
(define_insn "aarch64_simd_dup<mode>" (define_insn "aarch64_simd_dup<mode>"
[(set (match_operand:VDQF 0 "register_operand" "=w") [(set (match_operand:VDQF 0 "register_operand" "=w")
(vec_duplicate:VDQF (match_operand:<VEL> 1 "register_operand" "w")))] (vec_duplicate:VDQF (match_operand:<VEL> 1 "register_operand" "w")))]
...@@ -2147,45 +2133,50 @@ ...@@ -2147,45 +2133,50 @@
DONE; DONE;
}) })
(define_insn "aarch64_get_lane_signed<mode>" ;; Lane extraction with sign extension to general purpose register.
[(set (match_operand:<VEL> 0 "register_operand" "=r") (define_insn "*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>"
(sign_extend:<VEL> [(set (match_operand:GPI 0 "register_operand" "=r")
(sign_extend:GPI
(vec_select:<VEL> (vec_select:<VEL>
(match_operand:VQ_S 1 "register_operand" "w") (match_operand:VDQQH 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD" "TARGET_SIMD"
"smov\\t%0, %1.<Vetype>[%2]" "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]"
[(set_attr "simd_type" "simd_movgp") [(set_attr "simd_type" "simd_movgp")
(set_attr "simd_mode" "<MODE>")] (set_attr "simd_mode" "<VDQQH:MODE>")]
) )
(define_insn "aarch64_get_lane_unsigned<mode>" (define_insn "*aarch64_get_lane_zero_extendsi<mode>"
[(set (match_operand:<VEL> 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:<VEL> (zero_extend:SI
(vec_select:<VEL> (vec_select:<VEL>
(match_operand:VDQ 1 "register_operand" "w") (match_operand:VDQQH 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD" "TARGET_SIMD"
"umov\\t%<vw>0, %1.<Vetype>[%2]" "umov\\t%w0, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_movgp") [(set_attr "simd_type" "simd_movgp")
(set_attr "simd_mode" "<MODE>")] (set_attr "simd_mode" "<MODE>")]
) )
;; Lane extraction of a value, neither sign nor zero extension
;; is guaranteed so upper bits should be considered undefined.
(define_insn "aarch64_get_lane<mode>" (define_insn "aarch64_get_lane<mode>"
[(set (match_operand:<VEL> 0 "register_operand" "=w") [(set (match_operand:<VEL> 0 "register_operand" "=r, w")
(vec_select:<VEL> (vec_select:<VEL>
(match_operand:VDQF 1 "register_operand" "w") (match_operand:VALL 1 "register_operand" "w, w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")])))] (parallel [(match_operand:SI 2 "immediate_operand" "i, i")])))]
"TARGET_SIMD" "TARGET_SIMD"
"mov\\t%0.<Vetype>[0], %1.<Vetype>[%2]" "@
[(set_attr "simd_type" "simd_ins") umov\\t%<vwcore>0, %1.<Vetype>[%2]
dup\\t%<Vetype>0, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_movgp, simd_dup")
(set_attr "simd_mode" "<MODE>")] (set_attr "simd_mode" "<MODE>")]
) )
(define_expand "aarch64_get_lanedi" (define_expand "aarch64_get_lanedi"
[(match_operand:DI 0 "register_operand" "=r") [(match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand" "w") (match_operand:DI 1 "register_operand")
(match_operand:SI 2 "immediate_operand" "i")] (match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD" "TARGET_SIMD"
{ {
aarch64_simd_lane_bounds (operands[2], 0, 1); aarch64_simd_lane_bounds (operands[2], 0, 1);
......
gcc/config/aarch64/iterators.md
...@@ -134,9 +134,15 @@ ...@@ -134,9 +134,15 @@
;; Vector modes except double int. ;; Vector modes except double int.
(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
;; Vector modes for Q and H types.
(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
;; Vector modes for H and S types. ;; Vector modes for H and S types.
(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
;; Vector modes for Q, H and S types.
(define_mode_iterator VDQQHS [V8QI V16QI V4HI V8HI V2SI V4SI])
;; Vector and scalar integer modes for H and S ;; Vector and scalar integer modes for H and S
(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
...@@ -453,6 +459,15 @@ ...@@ -453,6 +459,15 @@
(V2SF "s") (V4SF "s") (V2SF "s") (V4SF "s")
(V2DF "d")]) (V2DF "d")])
;; Corresponding core element mode for each vector mode. This is a
;; variation on <vw> mapping FP modes to GP regs.
(define_mode_attr vwcore [(V8QI "w") (V16QI "w")
(V4HI "w") (V8HI "w")
(V2SI "w") (V4SI "w")
(DI "x") (V2DI "x")
(V2SF "w") (V4SF "w")
(V2DF "x")])
;; Double vector types for ALLX. ;; Double vector types for ALLX.
(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
......
gcc/testsuite/ChangeLog
2013-08-09 James Greenhalgh <james.greenhalgh@arm.com>
* gcc.target/aarch64/scalar_intrinsics.c: Update expected
output of vdup intrinsics.
2013-08-09 Zhenqiang Chen <zhenqiang.chen@linaro.org> 2013-08-09 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* gcc.target/arm/lp1189445.c: New testcase. * gcc.target/arm/lp1189445.c: New testcase.
......
gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
...@@ -193,7 +193,7 @@ test_vcltzd_s64 (int64x1_t a) ...@@ -193,7 +193,7 @@ test_vcltzd_s64 (int64x1_t a)
return res; return res;
} }
/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv16qi" 2 } } */ /* { dg-final { scan-assembler-times "aarch64_get_lanev16qi" 2 } } */
int8x1_t int8x1_t
test_vdupb_lane_s8 (int8x16_t a) test_vdupb_lane_s8 (int8x16_t a)
...@@ -207,7 +207,7 @@ test_vdupb_lane_u8 (uint8x16_t a) ...@@ -207,7 +207,7 @@ test_vdupb_lane_u8 (uint8x16_t a)
return vdupb_lane_u8 (a, 2); return vdupb_lane_u8 (a, 2);
} }
/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv8hi" 2 } } */ /* { dg-final { scan-assembler-times "aarch64_get_lanev8hi" 2 } } */
int16x1_t int16x1_t
test_vduph_lane_s16 (int16x8_t a) test_vduph_lane_s16 (int16x8_t a)
...@@ -221,7 +221,7 @@ test_vduph_lane_u16 (uint16x8_t a) ...@@ -221,7 +221,7 @@ test_vduph_lane_u16 (uint16x8_t a)
return vduph_lane_u16 (a, 2); return vduph_lane_u16 (a, 2);
} }
/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv4si" 2 } } */ /* { dg-final { scan-assembler-times "aarch64_get_lanev4si" 2 } } */
int32x1_t int32x1_t
test_vdups_lane_s32 (int32x4_t a) test_vdups_lane_s32 (int32x4_t a)
...@@ -235,7 +235,7 @@ test_vdups_lane_u32 (uint32x4_t a) ...@@ -235,7 +235,7 @@ test_vdups_lane_u32 (uint32x4_t a)
return vdups_lane_u32 (a, 2); return vdups_lane_u32 (a, 2);
} }
/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv2di" 2 } } */ /* { dg-final { scan-assembler-times "aarch64_get_lanev2di" 2 } } */
int64x1_t int64x1_t
test_vdupd_lane_s64 (int64x2_t a) test_vdupd_lane_s64 (int64x2_t a)
......
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