pa.c (pa_emit_move_sequence): Handle floating point reloads for other unsupported memory operands.

	* config/pa/pa.c (pa_emit_move_sequence): Handle floating point
	reloads for other unsupported memory operands.

From-SVN: r232253

gcc/ChangeLog

+2016-01-11  John David Anglin  <danglin@gcc.gnu.org>
+
+	* config/pa/pa.c (pa_emit_move_sequence): Handle floating point
+	reloads for other unsupported memory operands.
+
 2016-01-12  Kugan Vivekanandarajah  <kuganv@linaro.org>
 	    Jim Wilson  <jim.wilson@linaro.org>
 

gcc/config/pa/pa.c

@@ -1681,7 +1681,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 
   /* Handle secondary reloads for loads/stores of FP registers from
      REG+D addresses where D does not fit in 5 or 14 bits, including
-     (subreg (mem (addr))) cases.  */
+     (subreg (mem (addr))) cases, and reloads for other unsupported
+     memory operands.  */
   if (scratch_reg
       && FP_REG_P (operand0)
       && (MEM_P (operand1)
@@ -1693,8 +1694,9 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
       if (GET_CODE (op1) == SUBREG)
 	op1 = XEXP (op1, 0);
 
-      if (reg_plus_base_memory_operand (op1, GET_MODE (op1))
-	  && !(TARGET_PA_20
+      if (reg_plus_base_memory_operand (op1, GET_MODE (op1)))
+	{
+	  if (!(TARGET_PA_20
 		&& !TARGET_ELF32
 		&& INT_14_BITS (XEXP (XEXP (op1, 0), 1)))
 	      && !INT_5_BITS (XEXP (XEXP (op1, 0), 1)))
@@ -1704,8 +1706,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 		 originally given to us.  */
 	      scratch_reg = force_mode (word_mode, scratch_reg);
 
-	  /* D might not fit in 14 bits either; for such cases load D into
-	     scratch reg.  */
+	      /* D might not fit in 14 bits either; for such cases load D
+		 into scratch reg.  */
 	      if (!INT_14_BITS (XEXP (XEXP (op1, 0), 1)))
 		{
 		  emit_move_insn (scratch_reg, XEXP (XEXP (op1, 0), 1));
@@ -1722,6 +1724,18 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	      return 1;
 	    }
 	}
+      else if ((!INT14_OK_STRICT && symbolic_memory_operand (op1, VOIDmode))
+	       || IS_LO_SUM_DLT_ADDR_P (XEXP (op1, 0))
+	       || IS_INDEX_ADDR_P (XEXP (op1, 0)))
+	{
+	  /* Load memory address into SCRATCH_REG.  */
+	  scratch_reg = force_mode (word_mode, scratch_reg);
+	  emit_move_insn (scratch_reg, XEXP (op1, 0));
+	  emit_insn (gen_rtx_SET (operand0,
+				  replace_equiv_address (op1, scratch_reg)));
+	  return 1;
+	}
+    }
   else if (scratch_reg
 	   && FP_REG_P (operand1)
 	   && (MEM_P (operand0)
@@ -1733,8 +1747,9 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
       if (GET_CODE (op0) == SUBREG)
 	op0 = XEXP (op0, 0);
 
-      if (reg_plus_base_memory_operand (op0, GET_MODE (op0))
-	  && !(TARGET_PA_20
+      if (reg_plus_base_memory_operand (op0, GET_MODE (op0)))
+	{
+	  if (!(TARGET_PA_20
 		&& !TARGET_ELF32
 		&& INT_14_BITS (XEXP (XEXP (op0, 0), 1)))
 	      && !INT_5_BITS (XEXP (XEXP (op0, 0), 1)))
@@ -1744,8 +1759,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 		 originally given to us.  */
 	      scratch_reg = force_mode (word_mode, scratch_reg);
 
-	  /* D might not fit in 14 bits either; for such cases load D into
-	     scratch reg.  */
+	      /* D might not fit in 14 bits either; for such cases load D
+		 into scratch reg.  */
 	      if (!INT_14_BITS (XEXP (XEXP (op0, 0), 1)))
 		{
 		  emit_move_insn (scratch_reg, XEXP (XEXP (op0, 0), 1));
@@ -1762,6 +1777,18 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	      return 1;
 	    }
 	}
+      else if ((!INT14_OK_STRICT && symbolic_memory_operand (op0, VOIDmode))
+	       || IS_LO_SUM_DLT_ADDR_P (XEXP (op0, 0))
+	       || IS_INDEX_ADDR_P (XEXP (op0, 0)))
+	{
+	  /* Load memory address into SCRATCH_REG.  */
+	  scratch_reg = force_mode (word_mode, scratch_reg);
+	  emit_move_insn (scratch_reg, XEXP (op0, 0));
+	  emit_insn (gen_rtx_SET (replace_equiv_address (op0, scratch_reg),
+				  operand1));
+	  return 1;
+	}
+    }
   /* Handle secondary reloads for loads of FP registers from constant
      expressions by forcing the constant into memory.  For the most part,
      this is only necessary for SImode and DImode.