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Commit 65b1d8ea by Andreas Krebbel Committed by Andreas Krebbel
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s390.c (z196_cost): New. 

2010-10-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
            Christian Borntraeger  <Christian.Borntraeger@de.ibm.com>

	* gcc/config/s390/s390.c (z196_cost): New.
	(s390_handle_arch_option): Add -march=z196.
	(s390_option_override): Use the new cost function and use the z10
	defaults also for z196.
	(legitimate_reload_constant_p): Adjust comment.
	(legitimate_reload_fp_constant_p): New function.
	(s390_preferred_reload_class): Distingiush between FP and Int constants.
	(preferred_la_operand_p): Avoid la with index on z196.
	(s390_adjust_priority): Trigger also for z196.
	(s390_issue_rate): Issue rate for z196 is 3.
	(s390_z10_fix_long_loop_prediction): Rename to ...
	(s390_fix_long_loop_prediction): ... this.
	(s390_reorg): Apply the z10 adjustments also for z196.
	(s390_loop_unroll_adjust): Do this also for z196.
	* gcc/config/s390/s390.h (enum processor_type): Add PROCESSOR_2817_Z196.
	(enum processor_flags): Add PF_Z196.
	(TARGET_AVOID_CMP_AND_BRANCH): New macro.
	(TARGET_CPU_Z196, TARGET_Z196): New macros.
	* gcc/config.gcc: Enable z196 for --with-arch.
	* gcc/config/s390/2817.md: New file.
	* gcc/config/s390/2084.md: New type for multiply and add.
	* gcc/config/s390/2097.md: Likewise.
	* gcc/config/s390/s390.md (UNSPEC_POPCNT, UNSPEC_COPYSIGN)
	(UNSPECV_ATOMIC_OP): New constants.
	(fmadddf, fmaddsf): New values for type attribute.
	(z196prop): New insn attribute.
	(cpu, cpu_facility): Add z196.
	(ATOMIC_Z196): New code iterator.
	(noxa): New code attribute.
	(gk): New mode attribute.
	(*mov<mode>_64, *mov<mode>_31, *mov<mode>_64dfp, mov<mode>):
	Support load zero for fp constants.
	(fixuns_truncdddi2, fixuns_trunctddi2)
	(fixuns_trunc<BFP:mode><GPR:mode>2): Use the standard rtx pattern
	for z196.
	(fixuns_trunc<mode>si2, mov<mode>cc, popcountdi2, popcountsi2)
	(popcounthi2, popcountqi2): New expander.
	(*fixuns_trunc<FP:mode><GPR:mode>2_z196, floatsi<mode>2)
	(floatuns<GPR:mode><FP:mode>2, *mov<mode>cc, sync_<atomic><mode>)
	(sync_old_<atomic><mode>, *popcount<mode>, copysign<mode>3): New
	insn definition.
	(add<mode>3, *add<mode>3_carry1_cc, *add<mode>3_carry1_cconly)
	(*add<mode>3_carry2_cc, *add<mode>3_carry2_cconly, *add<mode>3_cc)
	(*add<mode>3_cconly, *add<mode>3_cconly2, *add<mode>3_imm_cc, *sub<mode>3)
	(*sub<mode>3_borrow_cc, *sub<mode>3_borrow_cconly, *sub<mode>3_cc)
	(*sub<mode>3_cc2, *sub<mode>3_cconly, *sub<mode>3_cconly2)
	(*anddi3_cc, *anddi3_cconly, *anddi3, *andsi3_cc, *andsi3_cconly)
	(*andsi3_zarch, *andsi3_esa, *andhi3_zarch, *andqi3_zarch, *iordi3_cc)
	(*iordi3_cconly, *iordi3, *iorsi3_cc, *iorsi3_cconly, *iorsi3_zarch)
	(*iorhi3_zarch, *iorqi3_zarch, *xordi3_cc, *xordi3_cconly, *xordi3)
	(*xorsi3_cc, *xorsi3_cconly, *xorsi3, *xorhi3, *xorqi3, *<shift><mode>3)
	(*<shift><mode>3_and, *ashr<mode>3_cc, *ashr<mode>3_cconly, *ashr<mode>3)
	(*ashr<mode>3_cc_and, *ashr<mode>3_cconly_and, *ashr<mode>3_and):
	Support new z196 instructions.


Co-Authored-By: Christian Borntraeger <Christian.Borntraeger@de.ibm.com>

From-SVN: r164985
parent 6e572326
Showing with 1336 additions and 486 deletions
gcc/ChangeLog
2010-10-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
Christian Borntraeger <Christian.Borntraeger@de.ibm.com>
* gcc/config/s390/s390.c (z196_cost): New.
(s390_handle_arch_option): Add -march=z196.
(s390_option_override): Use the new cost function and use the z10
defaults also for z196.
(legitimate_reload_constant_p): Adjust comment.
(legitimate_reload_fp_constant_p): New function.
(s390_preferred_reload_class): Distingiush between FP and Int constants.
(preferred_la_operand_p): Avoid la with index on z196.
(s390_adjust_priority): Trigger also for z196.
(s390_issue_rate): Issue rate for z196 is 3.
(s390_z10_fix_long_loop_prediction): Rename to ...
(s390_fix_long_loop_prediction): ... this.
(s390_reorg): Apply the z10 adjustments also for z196.
(s390_loop_unroll_adjust): Do this also for z196.
* gcc/config/s390/s390.h (enum processor_type): Add PROCESSOR_2817_Z196.
(enum processor_flags): Add PF_Z196.
(TARGET_AVOID_CMP_AND_BRANCH): New macro.
(TARGET_CPU_Z196, TARGET_Z196): New macros.
* gcc/config.gcc: Enable z196 for --with-arch.
* gcc/config/s390/2817.md: New file.
* gcc/config/s390/2084.md: New type for multiply and add.
* gcc/config/s390/2097.md: Likewise.
* gcc/config/s390/s390.md (UNSPEC_POPCNT, UNSPEC_COPYSIGN)
(UNSPECV_ATOMIC_OP): New constants.
(fmadddf, fmaddsf): New values for type attribute.
(z196prop): New insn attribute.
(cpu, cpu_facility): Add z196.
(ATOMIC_Z196): New code iterator.
(noxa): New code attribute.
(gk): New mode attribute.
(*mov<mode>_64, *mov<mode>_31, *mov<mode>_64dfp, mov<mode>):
Support load zero for fp constants.
(fixuns_truncdddi2, fixuns_trunctddi2)
(fixuns_trunc<BFP:mode><GPR:mode>2): Use the standard rtx pattern
for z196.
(fixuns_trunc<mode>si2, mov<mode>cc, popcountdi2, popcountsi2)
(popcounthi2, popcountqi2): New expander.
(*fixuns_trunc<FP:mode><GPR:mode>2_z196, floatsi<mode>2)
(floatuns<GPR:mode><FP:mode>2, *mov<mode>cc, sync_<atomic><mode>)
(sync_old_<atomic><mode>, *popcount<mode>, copysign<mode>3): New
insn definition.
(add<mode>3, *add<mode>3_carry1_cc, *add<mode>3_carry1_cconly)
(*add<mode>3_carry2_cc, *add<mode>3_carry2_cconly, *add<mode>3_cc)
(*add<mode>3_cconly, *add<mode>3_cconly2, *add<mode>3_imm_cc, *sub<mode>3)
(*sub<mode>3_borrow_cc, *sub<mode>3_borrow_cconly, *sub<mode>3_cc)
(*sub<mode>3_cc2, *sub<mode>3_cconly, *sub<mode>3_cconly2)
(*anddi3_cc, *anddi3_cconly, *anddi3, *andsi3_cc, *andsi3_cconly)
(*andsi3_zarch, *andsi3_esa, *andhi3_zarch, *andqi3_zarch, *iordi3_cc)
(*iordi3_cconly, *iordi3, *iorsi3_cc, *iorsi3_cconly, *iorsi3_zarch)
(*iorhi3_zarch, *iorqi3_zarch, *xordi3_cc, *xordi3_cconly, *xordi3)
(*xorsi3_cc, *xorsi3_cconly, *xorsi3, *xorhi3, *xorqi3, *<shift><mode>3)
(*<shift><mode>3_and, *ashr<mode>3_cc, *ashr<mode>3_cconly, *ashr<mode>3)
(*ashr<mode>3_cc_and, *ashr<mode>3_cconly_and, *ashr<mode>3_and):
Support new z196 instructions.
2010-10-05 Richard Guenther <rguenther@suse.de> 2010-10-05 Richard Guenther <rguenther@suse.de>
PR middle-end/45877 PR middle-end/45877
gcc/config.gcc
...@@ -3374,7 +3374,7 @@ case "${target}" in ...@@ -3374,7 +3374,7 @@ case "${target}" in
for which in arch tune; do for which in arch tune; do
eval "val=\$with_$which" eval "val=\$with_$which"
case ${val} in case ${val} in
"" | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10) "" | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10 | z196)
# OK # OK
;; ;;
*) *)
......
gcc/config/s390/2084.md
...@@ -168,12 +168,12 @@ ...@@ -168,12 +168,12 @@
(define_insn_reservation "x_fsimpdf" 6 (define_insn_reservation "x_fsimpdf" 6
(and (eq_attr "cpu" "z990,z9_109") (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fsimpdf,fmuldf,fhex")) (eq_attr "type" "fsimpdf,fmuldf,fmadddf,fhex"))
"x_e1_t,x-wr-fp") "x_e1_t,x-wr-fp")
(define_insn_reservation "x_fsimpsf" 6 (define_insn_reservation "x_fsimpsf" 6
(and (eq_attr "cpu" "z990,z9_109") (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fsimpsf,fmulsf,fhex")) (eq_attr "type" "fsimpsf,fmulsf,fmaddsf,fhex"))
"x_e1_t,x-wr-fp") "x_e1_t,x-wr-fp")
......
gcc/config/s390/2097.md
...@@ -463,12 +463,12 @@ ...@@ -463,12 +463,12 @@
(define_insn_reservation "z10_fsimpdf" 6 (define_insn_reservation "z10_fsimpdf" 6
(and (eq_attr "cpu" "z10") (and (eq_attr "cpu" "z10")
(eq_attr "type" "fsimpdf,fmuldf")) (eq_attr "type" "fsimpdf,fmuldf,fmadddf"))
"z10_e1_BOTH, z10_Gate_FP") "z10_e1_BOTH, z10_Gate_FP")
(define_insn_reservation "z10_fsimpsf" 6 (define_insn_reservation "z10_fsimpsf" 6
(and (eq_attr "cpu" "z10") (and (eq_attr "cpu" "z10")
(eq_attr "type" "fsimpsf,fmulsf")) (eq_attr "type" "fsimpsf,fmulsf,fmaddsf"))
"z10_e1_BOTH, z10_Gate_FP") "z10_e1_BOTH, z10_Gate_FP")
(define_insn_reservation "z10_fmultf" 52 (define_insn_reservation "z10_fmultf" 52
......
gcc/config/s390/2817.md 0 → 100644
;; Scheduling description for z196 (cpu 2817).
;; Copyright (C) 2010
;; Free Software Foundation, Inc.
;; Contributed by Christian Borntraeger (Christian.Borntraeger@de.ibm.com)
;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
;; Software Foundation; either version 3, or (at your option) any later
;; version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
;; for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "z196_ipu")
;; Fetch + Decoder
(define_cpu_unit "z196_g1" "z196_ipu")
(define_cpu_unit "z196_g2" "z196_ipu")
(define_cpu_unit "z196_g3" "z196_ipu")
(define_cpu_unit "z196_cr1" "z196_ipu")
(define_cpu_unit "z196_cr2" "z196_ipu")
(define_cpu_unit "z196_cr3" "z196_ipu")
(final_presence_set "z196_g2" "z196_g1")
(final_presence_set "z196_g3" "z196_g2")
(final_presence_set "z196_cr2" "z196_cr1")
(final_presence_set "z196_cr3" "z196_cr2")
(exclusion_set "z196_g1" "z196_cr1")
;; Instructions can be groupable, end a group, or be alone in a group.
(define_reservation "z196_simple" "( z196_g1 | z196_g2 | z196_g3 )")
(define_reservation "z196_ends" "( z196_g3 | ( z196_g2 + z196_g3 ) | ( z196_g1 + z196_g2 + z196_g3 ) )")
;; Try to keep cracked and alone ops together in a clump.
(define_reservation "z196_crack" "( z196_cr1 | z196_cr2 | z196_cr3 )")
(define_reservation "z196_alone" "( z196_cr1 | z196_cr2 | z196_cr3 )")
;; Most simple instruction a fast enough to be handled by OOO even with
;; latency == 0. This reduces life ranges and spilling. We want to increase
;; life range for longer running ops, though, thats why we do not use
;; -fno-schedule-insns.
(define_insn_reservation "z196_simple_LSU" 0
(and (eq_attr "cpu" "z196")
(and (eq_attr "type" "load,store,lr")
(eq_attr "z196prop" "none")))
"z196_simple")
(define_insn_reservation "z196_simple_FXU" 0
(and (eq_attr "cpu" "z196")
(and (eq_attr "type" "integer,la,larl,other")
(and (eq_attr "z196prop" "none")
(eq_attr "op_type" "RR"))))
"z196_simple")
(define_insn_reservation "z196_simple_DUAL" 0
(and (eq_attr "cpu" "z196")
(and (eq_attr "type" "integer,la,larl,other")
(and (eq_attr "z196prop" "none")
(eq_attr "op_type" "!RR"))))
"z196_simple")
(define_insn_reservation "z196_cracked" 0
(and (eq_attr "cpu" "z196")
(and (eq_attr "type" "integer,la,larl,load,lr,store,other")
(eq_attr "z196prop" "z196_cracked")))
"z196_crack")
(define_insn_reservation "z196_alone" 0
(and (eq_attr "cpu" "z196")
(and (eq_attr "type" "integer,la,larl,load,lr,store,other")
(eq_attr "z196prop" "z196_alone")))
"z196_alone")
(define_insn_reservation "z196_ends" 0
(and (eq_attr "cpu" "z196")
(and (eq_attr "type" "integer,la,larl,load,lr,store,other")
(eq_attr "z196prop" "z196_ends")))
"z196_ends")
(define_insn_reservation "z196_branch" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "branch"))
"z196_ends")
(define_insn_reservation "z196_call" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "jsr"))
"z196_ends")
(define_insn_reservation "z196_mul_hi" 10
(and (eq_attr "cpu" "z196")
(eq_attr "type" "imulhi"))
"z196_simple")
(define_insn_reservation "z196_mul_si" 12
(and (eq_attr "cpu" "z196")
(eq_attr "type" "imulsi"))
"z196_simple")
(define_insn_reservation "z196_mul_di" 14
(and (eq_attr "cpu" "z196")
(eq_attr "type" "imuldi"))
"z196_simple")
(define_insn_reservation "z196_div" 73
(and (eq_attr "cpu" "z196")
(eq_attr "type" "idiv"))
"z196_alone")
(define_insn_reservation "z196_sem" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "sem"))
"z196_crack")
(define_insn_reservation "z196_cs" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "cs"))
"z196_crack")
(define_insn_reservation "z196_vs" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "vs"))
"z196_alone")
(define_insn_reservation "z196_lm_stm" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "stm,lm"))
"z196_crack")
;;
;; Binary Floating Point
;;
(define_insn_reservation "z196_fsimptf" 18
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fsimptf,fhex"))
"z196_alone")
(define_insn_reservation "z196_fmultf" 47
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fmultf"))
"z196_alone")
(define_insn_reservation "z196_fsimpdf" 7
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fsimpdf,fmuldf,fhex"))
"z196_simple")
(define_insn_reservation "z196_fmadddf" 7
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fmadddf"))
"z196_alone")
(define_insn_reservation "z196_fsimpsf" 7
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fsimpsf,fmulsf,fhex"))
"z196_simple")
(define_insn_reservation "z196_fmaddsf" 7
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fmaddsf"))
"z196_alone")
(define_insn_reservation "z196_fdivtf" 108
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fdivtf,fsqrttf"))
"z196_alone")
(define_insn_reservation "z196_fdivdf" 36
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fdivdf,fsqrtdf"))
"z196_simple")
(define_insn_reservation "z196_fdivsf" 29
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fdivsf,fsqrtsf"))
"z196_simple")
;; Loads and stores are cheap as well.
(define_insn_reservation "z196_floaddf" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "floaddf"))
"z196_simple")
(define_insn_reservation "z196_floadsf" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "floadsf"))
"z196_simple")
(define_insn_reservation "z196_fstoredf" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fstoredf"))
"z196_simple")
(define_insn_reservation "z196_fstoresf" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fstoresf"))
"z196_simple")
(define_insn_reservation "z196_ftrunctf" 9
(and (eq_attr "cpu" "z196")
(eq_attr "type" "ftrunctf"))
"z196_simple")
(define_insn_reservation "z196_ftruncdf" 7
(and (eq_attr "cpu" "z196")
(eq_attr "type" "ftruncdf"))
"z196_simple")
(define_insn_reservation "z196_ftoi" 7
(and (eq_attr "cpu" "z196")
(eq_attr "type" "ftoi"))
"z196_crack")
(define_insn_reservation "z196_itof" 7
(and (eq_attr "cpu" "z196")
(eq_attr "type" "itoftf,itofdf,itofsf"))
"z196_crack")
;;
;; Decimal Floating Point
;;
;; DDTR
(define_insn_reservation "z196_fdivdd" 33
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fdivdd"))
"z196_simple")
;; DXTR
(define_insn_reservation "z196_fdivtd" 35
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fdivtd"))
"z196_alone")
;; LEDTR
(define_insn_reservation "z196_ftruncsd" 34
(and (eq_attr "cpu" "z196")
(eq_attr "type" "ftruncsd"))
"z196_simple")
;; LDXTR
(define_insn_reservation "z196_ftruncdd" 36
(and (eq_attr "cpu" "z196")
(eq_attr "type" "ftruncdd"))
"z196_simple")
;; These are normal fp loads/stores - which are cheap.
(define_insn_reservation "z196_floadsddd" 0
(and (eq_attr "cpu" "z196")
(eq_attr "type" "floadsd,floaddd,fstoredd,fstoresd"))
"z196_simple")
;; MDTR
(define_insn_reservation "z196_fmuldd" 23
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fmuldd"))
"z196_simple")
;; MXTR
(define_insn_reservation "z196_fmultd" 25
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fmultd"))
"z196_alone")
;; multiple different isns like add, sub etc.
;; Just use the same defaults as z10.
(define_insn_reservation "z196_fsimpsd" 17
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fsimpsd"))
"z196_simple")
(define_insn_reservation "z196_fsimpdd" 17
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fsimpdd"))
"z196_simple")
(define_insn_reservation "z196_fsimptd" 18
(and (eq_attr "cpu" "z196")
(eq_attr "type" "fsimptd"))
"z196_alone")
;; CDGTR
(define_insn_reservation "z196_itofdd" 45
(and (eq_attr "cpu" "z196")
(eq_attr "type" "itofdd"))
"z196_crack")
;; CXGTR
(define_insn_reservation "z196_itoftd" 33
(and (eq_attr "cpu" "z196")
(eq_attr "type" "itoftd"))
"z196_crack")
;; CGXTR, CGDTR
(define_insn_reservation "z196_ftoidfp" 33
(and (eq_attr "cpu" "z196")
(eq_attr "type" "ftoidfp"))
"z196_crack")
gcc/config/s390/s390.c
...@@ -223,6 +223,38 @@ struct processor_costs z10_cost = ...@@ -223,6 +223,38 @@ struct processor_costs z10_cost =
COSTS_N_INSNS (71), /* DSGR */ COSTS_N_INSNS (71), /* DSGR */
}; };
static const
struct processor_costs z196_cost =
{
COSTS_N_INSNS (7), /* M */
COSTS_N_INSNS (5), /* MGHI */
COSTS_N_INSNS (5), /* MH */
COSTS_N_INSNS (5), /* MHI */
COSTS_N_INSNS (7), /* ML */
COSTS_N_INSNS (7), /* MR */
COSTS_N_INSNS (6), /* MS */
COSTS_N_INSNS (8), /* MSG */
COSTS_N_INSNS (6), /* MSGF */
COSTS_N_INSNS (6), /* MSGFR */
COSTS_N_INSNS (8), /* MSGR */
COSTS_N_INSNS (6), /* MSR */
COSTS_N_INSNS (1) , /* multiplication in DFmode */
COSTS_N_INSNS (40), /* MXBR B+40 */
COSTS_N_INSNS (100), /* SQXBR B+100 */
COSTS_N_INSNS (42), /* SQDBR B+42 */
COSTS_N_INSNS (28), /* SQEBR B+28 */
COSTS_N_INSNS (1), /* MADBR B */
COSTS_N_INSNS (1), /* MAEBR B */
COSTS_N_INSNS (101), /* DXBR B+101 */
COSTS_N_INSNS (29), /* DDBR */
COSTS_N_INSNS (22), /* DEBR */
COSTS_N_INSNS (160), /* DLGR cracked */
COSTS_N_INSNS (160), /* DLR cracked */
COSTS_N_INSNS (160), /* DR expanded */
COSTS_N_INSNS (160), /* DSGFR cracked */
COSTS_N_INSNS (160), /* DSGR cracked */
};
extern int reload_completed; extern int reload_completed;
/* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */ /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
...@@ -350,8 +382,8 @@ struct GTY(()) machine_function ...@@ -350,8 +382,8 @@ struct GTY(()) machine_function
(HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1)) (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
/* That's the read ahead of the dynamic branch prediction unit in /* That's the read ahead of the dynamic branch prediction unit in
bytes on a z10 CPU. */ bytes on a z10 (or higher) CPU. */
#define Z10_PREDICT_DISTANCE 384 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
static enum machine_mode static enum machine_mode
s390_libgcc_cmp_return_mode (void) s390_libgcc_cmp_return_mode (void)
...@@ -1506,7 +1538,9 @@ s390_handle_arch_option (const char *arg, ...@@ -1506,7 +1538,9 @@ s390_handle_arch_option (const char *arg,
{"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
| PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP }, | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
{"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
| PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10}, | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
{"z196", PROCESSOR_2817_Z196, PF_IEEE_FLOAT | PF_ZARCH
| PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 },
}; };
size_t i; size_t i;
...@@ -1624,6 +1658,8 @@ s390_option_override (void) ...@@ -1624,6 +1658,8 @@ s390_option_override (void)
break; break;
case PROCESSOR_2097_Z10: case PROCESSOR_2097_Z10:
s390_cost = &z10_cost; s390_cost = &z10_cost;
case PROCESSOR_2817_Z196:
s390_cost = &z196_cost;
break; break;
default: default:
s390_cost = &z900_cost; s390_cost = &z900_cost;
...@@ -1648,7 +1684,8 @@ s390_option_override (void) ...@@ -1648,7 +1684,8 @@ s390_option_override (void)
target_flags |= MASK_LONG_DOUBLE_128; target_flags |= MASK_LONG_DOUBLE_128;
#endif #endif
if (s390_tune == PROCESSOR_2097_Z10) if (s390_tune == PROCESSOR_2097_Z10
|| s390_tune == PROCESSOR_2817_Z196)
{ {
if (!PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS)) if (!PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS))
set_param_value ("max-unrolled-insns", 100); set_param_value ("max-unrolled-insns", 100);
...@@ -2782,7 +2819,9 @@ s390_cannot_force_const_mem (rtx x) ...@@ -2782,7 +2819,9 @@ s390_cannot_force_const_mem (rtx x)
operand during and after reload. The difference to operand during and after reload. The difference to
legitimate_constant_p is that this function will not accept legitimate_constant_p is that this function will not accept
a constant that would need to be forced to the literal pool a constant that would need to be forced to the literal pool
before it can be used as operand. */ before it can be used as operand.
This function accepts all constants which can be loaded directly
into a GPR. */
bool bool
legitimate_reload_constant_p (rtx op) legitimate_reload_constant_p (rtx op)
...@@ -2836,6 +2875,24 @@ legitimate_reload_constant_p (rtx op) ...@@ -2836,6 +2875,24 @@ legitimate_reload_constant_p (rtx op)
return false; return false;
} }
/* Returns true if the constant value OP is a legitimate fp operand
during and after reload.
This function accepts all constants which can be loaded directly
into an FPR. */
static bool
legitimate_reload_fp_constant_p (rtx op)
{
/* Accept floating-point zero operands if the load zero instruction
can be used. */
if (TARGET_Z196
&& GET_CODE (op) == CONST_DOUBLE
&& s390_float_const_zero_p (op))
return true;
return false;
}
/* Given an rtx OP being reloaded into a reg required to be in class RCLASS, /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
return the class of reg to actually use. */ return the class of reg to actually use. */
...@@ -2854,8 +2911,10 @@ s390_preferred_reload_class (rtx op, enum reg_class rclass) ...@@ -2854,8 +2911,10 @@ s390_preferred_reload_class (rtx op, enum reg_class rclass)
else if (reg_class_subset_p (ADDR_REGS, rclass) else if (reg_class_subset_p (ADDR_REGS, rclass)
&& legitimate_reload_constant_p (op)) && legitimate_reload_constant_p (op))
return ADDR_REGS; return ADDR_REGS;
else else if (reg_class_subset_p (FP_REGS, rclass)
return NO_REGS; && legitimate_reload_fp_constant_p (op))
return FP_REGS;
return NO_REGS;
/* If a symbolic constant or a PLUS is reloaded, /* If a symbolic constant or a PLUS is reloaded,
it is most likely being used as an address, so it is most likely being used as an address, so
...@@ -3218,6 +3277,11 @@ preferred_la_operand_p (rtx op1, rtx op2) ...@@ -3218,6 +3277,11 @@ preferred_la_operand_p (rtx op1, rtx op2)
if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx))) if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
return false; return false;
/* Avoid LA instructions with index register on z196; it is
preferable to use regular add instructions when possible. */
if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
return false;
if (!TARGET_64BIT && !addr.pointer) if (!TARGET_64BIT && !addr.pointer)
return false; return false;
...@@ -5398,8 +5462,6 @@ s390_agen_dep_p (rtx dep_insn, rtx insn) ...@@ -5398,8 +5462,6 @@ s390_agen_dep_p (rtx dep_insn, rtx insn)
A STD instruction should be scheduled earlier, A STD instruction should be scheduled earlier,
in order to use the bypass. */ in order to use the bypass. */
static int static int
s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
{ {
...@@ -5408,7 +5470,8 @@ s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) ...@@ -5408,7 +5470,8 @@ s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
if (s390_tune != PROCESSOR_2084_Z990 if (s390_tune != PROCESSOR_2084_Z990
&& s390_tune != PROCESSOR_2094_Z9_109 && s390_tune != PROCESSOR_2094_Z9_109
&& s390_tune != PROCESSOR_2097_Z10) && s390_tune != PROCESSOR_2097_Z10
&& s390_tune != PROCESSOR_2817_Z196)
return priority; return priority;
switch (s390_safe_attr_type (insn)) switch (s390_safe_attr_type (insn))
...@@ -5437,6 +5500,7 @@ s390_issue_rate (void) ...@@ -5437,6 +5500,7 @@ s390_issue_rate (void)
{ {
case PROCESSOR_2084_Z990: case PROCESSOR_2084_Z990:
case PROCESSOR_2094_Z9_109: case PROCESSOR_2094_Z9_109:
case PROCESSOR_2817_Z196:
return 3; return 3;
case PROCESSOR_2097_Z10: case PROCESSOR_2097_Z10:
return 2; return 2;
...@@ -9859,13 +9923,13 @@ s390_optimize_prologue (void) ...@@ -9859,13 +9923,13 @@ s390_optimize_prologue (void)
} }
} }
/* On z10 the dynamic branch prediction must see the backward jump in /* On z10 and later the dynamic branch prediction must see the
a window of 384 bytes. If not it falls back to the static backward jump within a certain windows. If not it falls back to
prediction. This function rearranges the loop backward branch in a the static prediction. This function rearranges the loop backward
way which makes the static prediction always correct. The function branch in a way which makes the static prediction always correct.
returns true if it added an instruction. */ The function returns true if it added an instruction. */
static bool static bool
s390_z10_fix_long_loop_prediction (rtx insn) s390_fix_long_loop_prediction (rtx insn)
{ {
rtx set = single_set (insn); rtx set = single_set (insn);
rtx code_label, label_ref, new_label; rtx code_label, label_ref, new_label;
...@@ -9891,11 +9955,11 @@ s390_z10_fix_long_loop_prediction (rtx insn) ...@@ -9891,11 +9955,11 @@ s390_z10_fix_long_loop_prediction (rtx insn)
if (INSN_ADDRESSES (INSN_UID (code_label)) == -1 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
|| INSN_ADDRESSES (INSN_UID (insn)) == -1 || INSN_ADDRESSES (INSN_UID (insn)) == -1
|| (INSN_ADDRESSES (INSN_UID (insn)) || (INSN_ADDRESSES (INSN_UID (insn))
- INSN_ADDRESSES (INSN_UID (code_label)) < Z10_PREDICT_DISTANCE)) - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
return false; return false;
for (distance = 0, cur_insn = PREV_INSN (insn); for (distance = 0, cur_insn = PREV_INSN (insn);
distance < Z10_PREDICT_DISTANCE - 6; distance < PREDICT_DISTANCE - 6;
distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn)) distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn)) if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
return false; return false;
...@@ -10195,8 +10259,9 @@ s390_reorg (void) ...@@ -10195,8 +10259,9 @@ s390_reorg (void)
/* Try to optimize prologue and epilogue further. */ /* Try to optimize prologue and epilogue further. */
s390_optimize_prologue (); s390_optimize_prologue ();
/* Walk over the insns and do some z10 specific changes. */ /* Walk over the insns and do some >=z10 specific changes. */
if (s390_tune == PROCESSOR_2097_Z10) if (s390_tune == PROCESSOR_2097_Z10
|| s390_tune == PROCESSOR_2817_Z196)
{ {
rtx insn; rtx insn;
bool insn_added_p = false; bool insn_added_p = false;
...@@ -10211,10 +10276,11 @@ s390_reorg (void) ...@@ -10211,10 +10276,11 @@ s390_reorg (void)
continue; continue;
if (JUMP_P (insn)) if (JUMP_P (insn))
insn_added_p |= s390_z10_fix_long_loop_prediction (insn); insn_added_p |= s390_fix_long_loop_prediction (insn);
if (GET_CODE (PATTERN (insn)) == PARALLEL if ((GET_CODE (PATTERN (insn)) == PARALLEL
|| GET_CODE (PATTERN (insn)) == SET) || GET_CODE (PATTERN (insn)) == SET)
&& s390_tune == PROCESSOR_2097_Z10)
insn_added_p |= s390_z10_optimize_cmp (insn); insn_added_p |= s390_z10_optimize_cmp (insn);
} }
...@@ -10360,8 +10426,9 @@ check_dpu (rtx *x, unsigned *mem_count) ...@@ -10360,8 +10426,9 @@ check_dpu (rtx *x, unsigned *mem_count)
} }
/* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
a new number struct loop *loop should be unrolled if tuned for the z10 a new number struct loop *loop should be unrolled if tuned for cpus with
cpu. The loop is analyzed for memory accesses by calling check_dpu for a built-in stride prefetcher.
The loop is analyzed for memory accesses by calling check_dpu for
each rtx of the loop. Depending on the loop_depth and the amount of each rtx of the loop. Depending on the loop_depth and the amount of
memory accesses a new number <=nunroll is returned to improve the memory accesses a new number <=nunroll is returned to improve the
behaviour of the hardware prefetch unit. */ behaviour of the hardware prefetch unit. */
...@@ -10373,8 +10440,7 @@ s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop) ...@@ -10373,8 +10440,7 @@ s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
unsigned i; unsigned i;
unsigned mem_count = 0; unsigned mem_count = 0;
/* Only z10 needs special handling. */ if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
if (s390_tune != PROCESSOR_2097_Z10)
return nunroll; return nunroll;
/* Count the number of memory references within the loop body. */ /* Count the number of memory references within the loop body. */
......
gcc/config/s390/s390.h
...@@ -36,6 +36,7 @@ enum processor_type ...@@ -36,6 +36,7 @@ enum processor_type
PROCESSOR_2084_Z990, PROCESSOR_2084_Z990,
PROCESSOR_2094_Z9_109, PROCESSOR_2094_Z9_109,
PROCESSOR_2097_Z10, PROCESSOR_2097_Z10,
PROCESSOR_2817_Z196,
PROCESSOR_max PROCESSOR_max
}; };
...@@ -48,7 +49,8 @@ enum processor_flags ...@@ -48,7 +49,8 @@ enum processor_flags
PF_LONG_DISPLACEMENT = 4, PF_LONG_DISPLACEMENT = 4,
PF_EXTIMM = 8, PF_EXTIMM = 8,
PF_DFP = 16, PF_DFP = 16,
PF_Z10 = 32 PF_Z10 = 32,
PF_Z196 = 64
}; };
extern enum processor_type s390_tune; extern enum processor_type s390_tune;
...@@ -77,6 +79,8 @@ extern int s390_arch_flags; ...@@ -77,6 +79,8 @@ extern int s390_arch_flags;
(s390_arch_flags & PF_DFP) (s390_arch_flags & PF_DFP)
#define TARGET_CPU_Z10 \ #define TARGET_CPU_Z10 \
(s390_arch_flags & PF_Z10) (s390_arch_flags & PF_Z10)
#define TARGET_CPU_Z196 \
(s390_arch_flags & PF_Z196)
/* These flags indicate that the generated code should run on a cpu /* These flags indicate that the generated code should run on a cpu
providing the respective hardware facility when run in providing the respective hardware facility when run in
...@@ -90,6 +94,11 @@ extern int s390_arch_flags; ...@@ -90,6 +94,11 @@ extern int s390_arch_flags;
(TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT)
#define TARGET_Z10 \ #define TARGET_Z10 \
(TARGET_ZARCH && TARGET_CPU_Z10) (TARGET_ZARCH && TARGET_CPU_Z10)
#define TARGET_Z196 \
(TARGET_ZARCH && TARGET_CPU_Z196)
#define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196)
/* Run-time target specification. */ /* Run-time target specification. */
......
gcc/config/s390/s390.md
...@@ -107,6 +107,10 @@ ...@@ -107,6 +107,10 @@
; Test Data Class (TDC) ; Test Data Class (TDC)
(UNSPEC_TDC_INSN 800) (UNSPEC_TDC_INSN 800)
; Population Count
(UNSPEC_POPCNT 900)
(UNSPEC_COPYSIGN 901)
]) ])
;; ;;
...@@ -133,6 +137,7 @@ ...@@ -133,6 +137,7 @@
; Atomic Support ; Atomic Support
(UNSPECV_CAS 700) (UNSPECV_CAS 700)
(UNSPECV_ATOMIC_OP 701)
]) ])
;; ;;
...@@ -203,6 +208,7 @@ ...@@ -203,6 +208,7 @@
floadtf,floaddf,floadsf,fstoredf,fstoresf, floadtf,floaddf,floadsf,fstoredf,fstoresf,
fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
ftoi,fsqrttf,fsqrtdf,fsqrtsf, ftoi,fsqrttf,fsqrtdf,fsqrtsf,
fmadddf,fmaddsf,
ftrunctf,ftruncdf, ftruncsd, ftruncdd, ftrunctf,ftruncdf, ftruncsd, ftruncdd,
itoftf, itofdf, itofsf, itofdd, itoftd, itoftf, itofdf, itofsf, itofdd, itoftd,
fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
...@@ -244,6 +250,14 @@ ...@@ -244,6 +250,14 @@
z10_c" z10_c"
(const_string "none")) (const_string "none"))
;; Properties concerning Z196 decoding
;; z196_alone: must group alone
;; z196_end: ends a group
;; z196_cracked: instruction is cracked or expanded
(define_attr "z196prop" "none,
z196_alone, z196_ends,
z196_cracked"
(const_string "none"))
;; Length in bytes. ;; Length in bytes.
...@@ -258,10 +272,10 @@ ...@@ -258,10 +272,10 @@
;; distinguish between g5 and g6, but there are differences between the two ;; distinguish between g5 and g6, but there are differences between the two
;; CPUs could in theory be modeled. ;; CPUs could in theory be modeled.
(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10" (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10,z196"
(const (symbol_ref "s390_tune_attr"))) (const (symbol_ref "s390_tune_attr")))
(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10" (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196"
(const_string "standard")) (const_string "standard"))
(define_attr "enabled" "" (define_attr "enabled" ""
...@@ -290,6 +304,10 @@ ...@@ -290,6 +304,10 @@
(and (eq_attr "cpu_facility" "z10") (and (eq_attr "cpu_facility" "z10")
(ne (symbol_ref "TARGET_Z10") (const_int 0))) (ne (symbol_ref "TARGET_Z10") (const_int 0)))
(const_int 1)
(and (eq_attr "cpu_facility" "z196")
(ne (symbol_ref "TARGET_Z196") (const_int 0)))
(const_int 1)] (const_int 1)]
(const_int 0))) (const_int 0)))
...@@ -303,6 +321,9 @@ ...@@ -303,6 +321,9 @@
;; Pipeline description for z10 ;; Pipeline description for z10
(include "2097.md") (include "2097.md")
;; Pipeline description for z196
(include "2817.md")
;; Predicates ;; Predicates
(include "predicates.md") (include "predicates.md")
...@@ -361,8 +382,10 @@ ...@@ -361,8 +382,10 @@
;; This iterator and attribute allow to combine most atomic operations. ;; This iterator and attribute allow to combine most atomic operations.
(define_code_iterator ATOMIC [and ior xor plus minus mult]) (define_code_iterator ATOMIC [and ior xor plus minus mult])
(define_code_iterator ATOMIC_Z196 [and ior xor plus])
(define_code_attr atomic [(and "and") (ior "ior") (xor "xor") (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
(plus "add") (minus "sub") (mult "nand")]) (plus "add") (minus "sub") (mult "nand")])
(define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
...@@ -464,6 +487,11 @@ ...@@ -464,6 +487,11 @@
;; and "cfdbr" in SImode. ;; and "cfdbr" in SImode.
(define_mode_attr gf [(DI "g") (SI "f")]) (define_mode_attr gf [(DI "g") (SI "f")])
;; In GPR templates, a string like sll<gk> will expand to sllg for DI
;; and sllk for SI. This way it is possible to merge the new z196 SI
;; 3 operands shift instructions into the existing patterns.
(define_mode_attr gk [(DI "g") (SI "k")])
;; ICM mask required to load MODE value into the lowest subreg ;; ICM mask required to load MODE value into the lowest subreg
;; of a SImode register. ;; of a SImode register.
(define_mode_attr icm_lo [(HI "3") (QI "1")]) (define_mode_attr icm_lo [(HI "3") (QI "1")])
...@@ -775,7 +803,8 @@ ...@@ -775,7 +803,8 @@
chrl\t%0,%1" chrl\t%0,%1"
[(set_attr "op_type" "RX,RXY,RIL") [(set_attr "op_type" "RX,RXY,RIL")
(set_attr "cpu_facility" "*,*,z10") (set_attr "cpu_facility" "*,*,z10")
(set_attr "type" "*,*,larl")]) (set_attr "type" "*,*,larl")
(set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
(define_insn "*cmphi_ccs_z10" (define_insn "*cmphi_ccs_z10"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
...@@ -783,7 +812,8 @@ ...@@ -783,7 +812,8 @@
(match_operand:HI 1 "immediate_operand" "K")))] (match_operand:HI 1 "immediate_operand" "K")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_Z10" "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
"chhsi\t%0,%1" "chhsi\t%0,%1"
[(set_attr "op_type" "SIL")]) [(set_attr "op_type" "SIL")
(set_attr "z196prop" "z196_cracked")])
(define_insn "*cmpdi_ccs_signhi_rl" (define_insn "*cmpdi_ccs_signhi_rl"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
...@@ -1002,7 +1032,7 @@ ...@@ -1002,7 +1032,7 @@
(label_ref (match_operand 3 "" "")) (label_ref (match_operand 3 "" ""))
(pc))) (pc)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_Z10" "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
{ {
if (get_attr_length (insn) == 6) if (get_attr_length (insn) == 6)
return which_alternative ? return which_alternative ?
...@@ -1030,7 +1060,7 @@ ...@@ -1030,7 +1060,7 @@
(label_ref (match_operand 3 "" "")) (label_ref (match_operand 3 "" ""))
(pc))) (pc)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_Z10" "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
{ {
if (get_attr_length (insn) == 6) if (get_attr_length (insn) == 6)
return which_alternative ? return which_alternative ?
...@@ -1060,7 +1090,7 @@ ...@@ -1060,7 +1090,7 @@
(pc) (pc)
(label_ref (match_operand 3 "" "")))) (label_ref (match_operand 3 "" ""))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_Z10" "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
{ {
if (get_attr_length (insn) == 6) if (get_attr_length (insn) == 6)
return which_alternative ? return which_alternative ?
...@@ -1088,7 +1118,7 @@ ...@@ -1088,7 +1118,7 @@
(pc) (pc)
(label_ref (match_operand 3 "" "")))) (label_ref (match_operand 3 "" ""))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_Z10" "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
{ {
if (get_attr_length (insn) == 6) if (get_attr_length (insn) == 6)
return which_alternative ? return which_alternative ?
...@@ -1928,10 +1958,11 @@ ...@@ -1928,10 +1958,11 @@
"") "")
(define_insn "*mov<mode>_64" (define_insn "*mov<mode>_64"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o, d,QS, d,o") [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
(match_operand:TD_TF 1 "general_operand" " f,o,f,QS, d,dRT,d"))] (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
lzxr\t%0
lxr\t%0,%1 lxr\t%0,%1
# #
# #
...@@ -1939,19 +1970,22 @@ ...@@ -1939,19 +1970,22 @@
stmg\t%1,%N1,%S0 stmg\t%1,%N1,%S0
# #
#" #"
[(set_attr "op_type" "RRE,*,*,RSY,RSY,*,*") [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
(set_attr "type" "fsimptf,*,*,lm,stm,*,*")]) (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
(set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
(define_insn "*mov<mode>_31" (define_insn "*mov<mode>_31"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o") [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
(match_operand:TD_TF 1 "general_operand" " f,o,f"))] (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
"!TARGET_ZARCH" "!TARGET_ZARCH"
"@ "@
lzxr\t%0
lxr\t%0,%1 lxr\t%0,%1
# #
#" #"
[(set_attr "op_type" "RRE,*,*") [(set_attr "op_type" "RRE,RRE,*,*")
(set_attr "type" "fsimptf,*,*")]) (set_attr "type" "fsimptf,fsimptf,*,*")
(set_attr "cpu_facility" "z196,*,*,*")])
; TFmode in GPRs splitters ; TFmode in GPRs splitters
...@@ -2042,11 +2076,12 @@ ...@@ -2042,11 +2076,12 @@
(define_insn "*mov<mode>_64dfp" (define_insn "*mov<mode>_64dfp"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" [(set (match_operand:DD_DF 0 "nonimmediate_operand"
"=f,f,d,f,f,R,T,d,d, d,RT") "=f,f,f,d,f,f,R,T,d,d, d,RT")
(match_operand:DD_DF 1 "general_operand" (match_operand:DD_DF 1 "general_operand"
" f,d,f,R,T,f,f,G,d,RT, d"))] " G,f,d,f,R,T,f,f,G,d,RT, d"))]
"TARGET_DFP" "TARGET_DFP"
"@ "@
lzdr\t%0
ldr\t%0,%1 ldr\t%0,%1
ldgr\t%0,%1 ldgr\t%0,%1
lgdr\t%0,%1 lgdr\t%0,%1
...@@ -2058,17 +2093,18 @@ ...@@ -2058,17 +2093,18 @@
lgr\t%0,%1 lgr\t%0,%1
lg\t%0,%1 lg\t%0,%1
stg\t%1,%0" stg\t%1,%0"
[(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
(set_attr "type" "floaddf,floaddf,floaddf,floaddf,floaddf, (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
fstoredf,fstoredf,*,lr,load,store") fstoredf,fstoredf,*,lr,load,store")
(set_attr "z10prop" "*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
]) (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
(define_insn "*mov<mode>_64" (define_insn "*mov<mode>_64"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d, d,RT") [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
(match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,G,d,RT, d"))] (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
lzdr\t%0
ldr\t%0,%1 ldr\t%0,%1
ld\t%0,%1 ld\t%0,%1
ldy\t%0,%1 ldy\t%0,%1
...@@ -2078,18 +2114,20 @@ ...@@ -2078,18 +2114,20 @@
lgr\t%0,%1 lgr\t%0,%1
lg\t%0,%1 lg\t%0,%1
stg\t%1,%0" stg\t%1,%0"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
(set_attr "type" "fload<mode>,fload<mode>,fload<mode>, (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,*,lr,load,store") fstore<mode>,fstore<mode>,*,lr,load,store")
(set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")]) (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
(set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
(define_insn "*mov<mode>_31" (define_insn "*mov<mode>_31"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" [(set (match_operand:DD_DF 0 "nonimmediate_operand"
"=f,f,f,R,T,d,d,Q,S, d,o") "=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand" (match_operand:DD_DF 1 "general_operand"
" f,R,T,f,f,Q,S,d,d,dPRT,d"))] " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
"!TARGET_ZARCH" "!TARGET_ZARCH"
"@ "@
lzdr\t%0
ldr\t%0,%1 ldr\t%0,%1
ld\t%0,%1 ld\t%0,%1
ldy\t%0,%1 ldy\t%0,%1
...@@ -2101,9 +2139,10 @@ ...@@ -2101,9 +2139,10 @@
stmy\t%1,%N1,%S0 stmy\t%1,%N1,%S0
# #
#" #"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
(set_attr "type" "fload<mode>,fload<mode>,fload<mode>, (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")]) fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
(set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
(define_split (define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "") [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
...@@ -2152,11 +2191,12 @@ ...@@ -2152,11 +2191,12 @@
(define_insn "mov<mode>" (define_insn "mov<mode>"
[(set (match_operand:SD_SF 0 "nonimmediate_operand" [(set (match_operand:SD_SF 0 "nonimmediate_operand"
"=f,f,f,R,T,d,d,d,d,R,T") "=f,f,f,f,R,T,d,d,d,d,R,T")
(match_operand:SD_SF 1 "general_operand" (match_operand:SD_SF 1 "general_operand"
" f,R,T,f,f,G,d,R,T,d,d"))] " G,f,R,T,f,f,G,d,R,T,d,d"))]
"" ""
"@ "@
lzer\t%0
ler\t%0,%1 ler\t%0,%1
le\t%0,%1 le\t%0,%1
ley\t%0,%1 ley\t%0,%1
...@@ -2168,10 +2208,11 @@ ...@@ -2168,10 +2208,11 @@
ly\t%0,%1 ly\t%0,%1
st\t%1,%0 st\t%1,%0
sty\t%1,%0" sty\t%1,%0"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY") [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
(set_attr "type" "fload<mode>,fload<mode>,fload<mode>, (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,*,lr,load,load,store,store") fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
(set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")]) (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
(set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
; ;
; movcc instruction pattern ; movcc instruction pattern
...@@ -2191,7 +2232,8 @@ ...@@ -2191,7 +2232,8 @@
ly\t%1,%0" ly\t%1,%0"
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
(set_attr "type" "lr,*,*,store,store,load,load") (set_attr "type" "lr,*,*,store,store,load,load")
(set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")]) (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
(set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
; ;
; Block move (MVC) patterns. ; Block move (MVC) patterns.
...@@ -3846,100 +3888,141 @@ ...@@ -3846,100 +3888,141 @@
[(parallel [(parallel
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
(clobber (match_scratch:TD 2 "=f"))])] (unspec:DI [(const_int 5)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_DFP" "TARGET_HARD_DFP"
{ {
rtx label1 = gen_label_rtx (); if (!TARGET_Z196)
rtx label2 = gen_label_rtx (); {
rtx temp = gen_reg_rtx (TDmode); rtx label1 = gen_label_rtx ();
REAL_VALUE_TYPE cmp, sub; rtx label2 = gen_label_rtx ();
rtx temp = gen_reg_rtx (TDmode);
decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ REAL_VALUE_TYPE cmp, sub;
decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
/* 2^63 can't be represented as 64bit DFP number with full precision. The decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
solution is doing the check and the subtraction in TD mode and using a
TD -> DI convert afterwards. */ /* 2^63 can't be represented as 64bit DFP number with full precision. The
emit_insn (gen_extendddtd2 (temp, operands[1])); solution is doing the check and the subtraction in TD mode and using a
temp = force_reg (TDmode, temp); TD -> DI convert afterwards. */
emit_cmp_and_jump_insns (temp, emit_insn (gen_extendddtd2 (temp, operands[1]));
CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), temp = force_reg (TDmode, temp);
LT, NULL_RTX, VOIDmode, 0, label1); emit_cmp_and_jump_insns (temp,
emit_insn (gen_subtd3 (temp, temp, CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); LT, NULL_RTX, VOIDmode, 0, label1);
emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); emit_insn (gen_subtd3 (temp, temp,
emit_jump (label2); CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
emit_label (label1); emit_jump (label2);
emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
emit_label (label2); emit_label (label1);
DONE; emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
emit_label (label2);
DONE;
}
}) })
(define_expand "fixuns_trunctddi2" (define_expand "fixuns_trunctddi2"
[(set (match_operand:DI 0 "register_operand" "") [(parallel
(unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))] [(set (match_operand:DI 0 "register_operand" "")
(unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
(unspec:DI [(const_int 5)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_DFP" "TARGET_HARD_DFP"
{ {
rtx label1 = gen_label_rtx (); if (!TARGET_Z196)
rtx label2 = gen_label_rtx (); {
rtx temp = gen_reg_rtx (TDmode); rtx label1 = gen_label_rtx ();
REAL_VALUE_TYPE cmp, sub; rtx label2 = gen_label_rtx ();
rtx temp = gen_reg_rtx (TDmode);
operands[1] = force_reg (TDmode, operands[1]); REAL_VALUE_TYPE cmp, sub;
decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ operands[1] = force_reg (TDmode, operands[1]);
decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
emit_cmp_and_jump_insns (operands[1], decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
LT, NULL_RTX, VOIDmode, 0, label1); emit_cmp_and_jump_insns (operands[1],
emit_insn (gen_subtd3 (temp, operands[1], CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); LT, NULL_RTX, VOIDmode, 0, label1);
emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); emit_insn (gen_subtd3 (temp, operands[1],
emit_jump (label2); CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
emit_label (label1); emit_jump (label2);
emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
emit_label (label2); emit_label (label1);
DONE; emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
emit_label (label2);
DONE;
}
}) })
; ;
; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
; instruction pattern(s). ; instruction pattern(s).
; ;
(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "") [(parallel
(unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))] [(set (match_operand:GPR 0 "register_operand" "")
(unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
(unspec:GPR [(const_int 5)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
{ {
rtx label1 = gen_label_rtx (); if (!TARGET_Z196)
rtx label2 = gen_label_rtx (); {
rtx temp = gen_reg_rtx (<BFP:MODE>mode); rtx label1 = gen_label_rtx ();
REAL_VALUE_TYPE cmp, sub; rtx label2 = gen_label_rtx ();
rtx temp = gen_reg_rtx (<BFP:MODE>mode);
operands[1] = force_reg (<BFP:MODE>mode, operands[1]); REAL_VALUE_TYPE cmp, sub;
real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
emit_cmp_and_jump_insns (operands[1], real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
LT, NULL_RTX, VOIDmode, 0, label1); emit_cmp_and_jump_insns (operands[1],
emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); LT, NULL_RTX, VOIDmode, 0, label1);
emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
GEN_INT (7))); CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
emit_jump (label2); emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
GEN_INT (7)));
emit_label (label1); emit_jump (label2);
emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
operands[1], GEN_INT (5))); emit_label (label1);
emit_label (label2); emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
DONE; operands[1], GEN_INT (5)));
emit_label (label2);
DONE;
}
}) })
; fixuns_trunc(td|dd)si2 expander
(define_expand "fixuns_trunc<mode>si2"
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
(unspec:SI [(const_int 5)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z196 && TARGET_HARD_FLOAT"
"")
; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
; clfdtr, clfxtr, clgdtr, clgxtr
(define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
[(set (match_operand:GPR 0 "register_operand" "=r")
(unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
(unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z196"
"cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
[(set_attr "op_type" "RRF")
(set_attr "type" "ftoi")])
(define_expand "fix_trunc<DSF:mode><GPR:mode>2" (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "") [(set (match_operand:GPR 0 "register_operand" "")
(fix:GPR (match_operand:DSF 1 "register_operand" "")))] (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
...@@ -4024,6 +4107,28 @@ ...@@ -4024,6 +4107,28 @@
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "itof<mode>" )]) (set_attr "type" "itof<mode>" )])
; cxftr, cdftr
(define_insn "floatsi<mode>2"
[(set (match_operand:DFP 0 "register_operand" "=f")
(float:DFP (match_operand:SI 1 "register_operand" "d")))]
"TARGET_Z196 && TARGET_HARD_FLOAT"
"c<xde>ftr\t%0,0,%1,0"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof<mode>" )])
;
; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
;
; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
(define_insn "floatuns<GPR:mode><FP:mode>2"
[(set (match_operand:FP 0 "register_operand" "=f")
(unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
"TARGET_Z196 && TARGET_HARD_FLOAT"
"c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof<FP:mode>" )])
; ;
; truncdfsf2 instruction pattern(s). ; truncdfsf2 instruction pattern(s).
...@@ -4294,7 +4399,8 @@ ...@@ -4294,7 +4399,8 @@
"@ "@
agfr\t%0,%2 agfr\t%0,%2
agf\t%0,%2" agf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")
(set_attr "z196prop" "z196_cracked,z196_cracked")])
(define_insn "*adddi3_zero_cc" (define_insn "*adddi3_zero_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
...@@ -4414,178 +4520,178 @@ ...@@ -4414,178 +4520,178 @@
"@ "@
ah\t%0,%2 ah\t%0,%2
ahy\t%0,%2" ahy\t%0,%2"
[(set_attr "op_type" "RX,RXY")]) [(set_attr "op_type" "RX,RXY")
(set_attr "z196prop" "z196_cracked,z196_cracked")])
; ;
; add(di|si)3 instruction pattern(s). ; add(di|si)3 instruction pattern(s).
; ;
; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
(define_insn "*add<mode>3" (define_insn "*add<mode>3"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS") [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
(plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
(match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) ) (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" ""
"@ "@
a<g>r\t%0,%2 a<g>r\t%0,%2
a<g>rk\t%0,%1,%2
a<g>hi\t%0,%h2 a<g>hi\t%0,%h2
a<g>hik\t%0,%1,%h2
al<g>fi\t%0,%2 al<g>fi\t%0,%2
sl<g>fi\t%0,%n2 sl<g>fi\t%0,%n2
a<g>\t%0,%2 a<g>\t%0,%2
a<y>\t%0,%2 a<y>\t%0,%2
a<g>si\t%0,%c2" a<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY") [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
(set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10") (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
(set_attr "z10prop" "z10_super_E1, (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
z10_super_E1, z10_super_E1,z10_super_E1,z10_super_E1")])
z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1")])
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
(define_insn "*add<mode>3_carry1_cc" (define_insn "*add<mode>3_carry1_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
(match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
(match_dup 1))) (match_dup 1)))
(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d") (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
(plus:GPR (match_dup 1) (match_dup 2)))] (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
al<g>r\t%0,%2 al<g>r\t%0,%2
al<g>rk\t%0,%1,%2
al<g>fi\t%0,%2 al<g>fi\t%0,%2
sl<g>fi\t%0,%n2 sl<g>fi\t%0,%n2
al<g>hsik\t%0,%1,%h2
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2 al<y>\t%0,%2
al<g>si\t%0,%c2" al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
(set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
(set_attr "z10prop" "z10_super_E1, (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
z10_super_E1, z10_super_E1,z10_super_E1,z10_super_E1")])
z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1")])
; alr, al, aly, algr, alg ; alr, al, aly, algr, alg, alrk, algrk
(define_insn "*add<mode>3_carry1_cconly" (define_insn "*add<mode>3_carry1_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T")) (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(match_dup 1))) (match_dup 1)))
(clobber (match_scratch:GPR 0 "=d,d,d"))] (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
al<g>r\t%0,%2 al<g>r\t%0,%2
al<g>rk\t%0,%1,%2
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2" al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_carry2_cc" (define_insn "*add<mode>3_carry2_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
(match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
(match_dup 2))) (match_dup 2)))
(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
(plus:GPR (match_dup 1) (match_dup 2)))] (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
al<g>r\t%0,%2 al<g>r\t%0,%2
al<g>rk\t%0,%1,%2
al<g>fi\t%0,%2 al<g>fi\t%0,%2
sl<g>fi\t%0,%n2 sl<g>fi\t%0,%n2
al<g>hsik\t%0,%1,%h2
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2 al<y>\t%0,%2
al<g>si\t%0,%c2" al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
(set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
(set_attr "z10prop" "z10_super_E1, (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
z10_super_E1, z10_super_E1,z10_super_E1,z10_super_E1")])
z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1")])
; alr, al, aly, algr, alg ; alr, al, aly, algr, alg, alrk, algrk
(define_insn "*add<mode>3_carry2_cconly" (define_insn "*add<mode>3_carry2_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T")) (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(match_dup 2))) (match_dup 2)))
(clobber (match_scratch:GPR 0 "=d,d,d"))] (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
al<g>r\t%0,%2 al<g>r\t%0,%2
al<g>rk\t%0,%1,%2
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2" al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_cc" (define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
(match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
(const_int 0))) (const_int 0)))
(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
(plus:GPR (match_dup 1) (match_dup 2)))] (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)" "s390_match_ccmode (insn, CCLmode)"
"@ "@
al<g>r\t%0,%2 al<g>r\t%0,%2
al<g>rk\t%0,%1,%2
al<g>fi\t%0,%2 al<g>fi\t%0,%2
sl<g>fi\t%0,%n2 sl<g>fi\t%0,%n2
al<g>hsik\t%0,%1,%h2
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2 al<y>\t%0,%2
al<g>si\t%0,%c2" al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
(set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
(set_attr "z10prop" "z10_super_E1, (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
z10_super_E1, *,z10_super_E1,z10_super_E1,z10_super_E1")])
z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1")])
; alr, al, aly, algr, alg ; alr, al, aly, algr, alg, alrk, algrk
(define_insn "*add<mode>3_cconly" (define_insn "*add<mode>3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T")) (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:GPR 0 "=d,d,d"))] (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCLmode)" "s390_match_ccmode (insn, CCLmode)"
"@ "@
al<g>r\t%0,%2 al<g>r\t%0,%2
al<g>rk\t%0,%1,%2
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2" al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, al, aly, algr, alg ; alr, al, aly, algr, alg, alrk, algrk
(define_insn "*add<mode>3_cconly2" (define_insn "*add<mode>3_cconly2"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
(neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T")))) (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
(clobber (match_scratch:GPR 0 "=d,d,d"))] (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode(insn, CCLmode)" "s390_match_ccmode(insn, CCLmode)"
"@ "@
al<g>r\t%0,%2 al<g>r\t%0,%2
al<g>rk\t%0,%1,%2
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2" al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; ahi, afi, aghi, agfi, asi, agsi ; ahi, afi, aghi, agfi, asi, agsi
(define_insn "*add<mode>3_imm_cc" (define_insn "*add<mode>3_imm_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
(match_operand:GPR 2 "const_int_operand" "K,Os,C")) (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
(const_int 0))) (const_int 0)))
(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS") (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
(plus:GPR (match_dup 1) (match_dup 2)))] (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode) "s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
...@@ -4594,11 +4700,12 @@ ...@@ -4594,11 +4700,12 @@
&& INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
"@ "@
a<g>hi\t%0,%h2 a<g>hi\t%0,%h2
a<g>hik\t%0,%1,%h2
a<g>fi\t%0,%2 a<g>fi\t%0,%2
a<g>si\t%0,%c2" a<g>si\t%0,%c2"
[(set_attr "op_type" "RI,RIL,SIY") [(set_attr "op_type" "RI,RIE,RIL,SIY")
(set_attr "cpu_facility" "*,extimm,z10") (set_attr "cpu_facility" "*,z196,extimm,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; ;
; add(tf|df|sf|td|dd)3 instruction pattern(s). ; add(tf|df|sf|td|dd)3 instruction pattern(s).
...@@ -4702,7 +4809,8 @@ ...@@ -4702,7 +4809,8 @@
sgfr\t%0,%2 sgfr\t%0,%2
sgf\t%0,%2" sgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY") [(set_attr "op_type" "RRE,RXY")
(set_attr "z10prop" "z10_c,*")]) (set_attr "z10prop" "z10_c,*")
(set_attr "z196prop" "z196_cracked")])
(define_insn "*subdi3_zero_cc" (define_insn "*subdi3_zero_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
...@@ -4821,117 +4929,132 @@ ...@@ -4821,117 +4929,132 @@
"@ "@
sh\t%0,%2 sh\t%0,%2
shy\t%0,%2" shy\t%0,%2"
[(set_attr "op_type" "RX,RXY")]) [(set_attr "op_type" "RX,RXY")
(set_attr "z196prop" "z196_cracked,z196_cracked")])
; ;
; sub(di|si)3 instruction pattern(s). ; sub(di|si)3 instruction pattern(s).
; ;
; sr, s, sy, sgr, sg ; sr, s, sy, sgr, sg, srk, sgrk
(define_insn "*sub<mode>3" (define_insn "*sub<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d,d,d") [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
(minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T") ) ) (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" ""
"@ "@
s<g>r\t%0,%2 s<g>r\t%0,%2
s<g>rk\t%0,%1,%2
s<g>\t%0,%2 s<g>\t%0,%2
s<y>\t%0,%2" s<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg ; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_borrow_cc" (define_insn "*sub<mode>3_borrow_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T")) (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(match_dup 1))) (match_dup 1)))
(set (match_operand:GPR 0 "register_operand" "=d,d,d") (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
(minus:GPR (match_dup 1) (match_dup 2)))] (minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL2mode)" "s390_match_ccmode (insn, CCL2mode)"
"@ "@
sl<g>r\t%0,%2 sl<g>r\t%0,%2
sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg ; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_borrow_cconly" (define_insn "*sub<mode>3_borrow_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T")) (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(match_dup 1))) (match_dup 1)))
(clobber (match_scratch:GPR 0 "=d,d,d"))] (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCL2mode)" "s390_match_ccmode (insn, CCL2mode)"
"@ "@
sl<g>r\t%0,%2 sl<g>r\t%0,%2
sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg ; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_cc" (define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T")) (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d,d") (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
(minus:GPR (match_dup 1) (match_dup 2)))] (minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)" "s390_match_ccmode (insn, CCLmode)"
"@ "@
sl<g>r\t%0,%2 sl<g>r\t%0,%2
sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg ; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_cc2" (define_insn "*sub<mode>3_cc2"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:GPR 1 "register_operand" "0,0,0") (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T"))) (match_operand:GPR 2 "general_operand" "d,d,R,T")))
(set (match_operand:GPR 0 "register_operand" "=d,d,d") (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
(minus:GPR (match_dup 1) (match_dup 2)))] (minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL3mode)" "s390_match_ccmode (insn, CCL3mode)"
"@ "@
sl<g>r\t%0,%2 sl<g>r\t%0,%2
sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg ; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_cconly" (define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T")) (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:GPR 0 "=d,d,d"))] (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCLmode)" "s390_match_ccmode (insn, CCLmode)"
"@ "@
sl<g>r\t%0,%2 sl<g>r\t%0,%2
sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg ; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_cconly2" (define_insn "*sub<mode>3_cconly2"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:GPR 1 "register_operand" "0,0,0") (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
(match_operand:GPR 2 "general_operand" "d,R,T"))) (match_operand:GPR 2 "general_operand" "d,d,R,T")))
(clobber (match_scratch:GPR 0 "=d,d,d"))] (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCL3mode)" "s390_match_ccmode (insn, CCL3mode)"
"@ "@
sl<g>r\t%0,%2 sl<g>r\t%0,%2
sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*,*")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; ;
...@@ -5008,7 +5131,8 @@ ...@@ -5008,7 +5131,8 @@
"@ "@
alc<g>r\t%0,%2 alc<g>r\t%0,%2
alc<g>\t%0,%2" alc<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")
(set_attr "z196prop" "z196_alone,z196_alone")])
; alcr, alc, alcgr, alcg ; alcr, alc, alcgr, alcg
(define_insn "*add<mode>3_alc_carry1_cconly" (define_insn "*add<mode>3_alc_carry1_cconly"
...@@ -5023,7 +5147,8 @@ ...@@ -5023,7 +5147,8 @@
"@ "@
alc<g>r\t%0,%2 alc<g>r\t%0,%2
alc<g>\t%0,%2" alc<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")
(set_attr "z196prop" "z196_alone,z196_alone")])
; op1 + op2 + c < op2 ; op1 + op2 + c < op2
...@@ -5201,6 +5326,52 @@ ...@@ -5201,6 +5326,52 @@
;; ;;
;; - Conditional move instructions (introduced with z196)
;;
(define_expand "mov<mode>cc"
[(set (match_operand:GPR 0 "nonimmediate_operand" "")
(if_then_else:GPR (match_operand 1 "comparison_operator" "")
(match_operand:GPR 2 "nonimmediate_operand" "")
(match_operand:GPR 3 "nonimmediate_operand" "")))]
"TARGET_Z196"
"operands[1] = s390_emit_compare (GET_CODE (operands[1]),
XEXP (operands[1], 0), XEXP (operands[1], 1));")
; locr, loc, stoc, locgr, lgoc, stgoc
(define_insn_and_split "*mov<mode>cc"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
(if_then_else:GPR
(match_operator 1 "s390_comparison"
[(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
(const_int 0)])
(match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
(match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
"TARGET_Z196"
"@
loc<g>r%C1\t%0,%3
loc<g>r%D1\t%0,%4
l<g>oc%C1\t%0,%3
l<g>oc%D1\t%0,%4
st<g>oc%C1\t%3,%0
st<g>oc%D1\t%4,%0
#"
"&& reload_completed
&& MEM_P (operands[3]) && MEM_P (operands[4])"
[(set (match_dup 0)
(if_then_else:GPR
(match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 3)
(match_dup 0)))
(set (match_dup 0)
(if_then_else:GPR
(match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 0)
(match_dup 4)))]
""
[(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
;;
;;- Multiply instructions. ;;- Multiply instructions.
;; ;;
...@@ -5327,7 +5498,7 @@ ...@@ -5327,7 +5498,7 @@
ma<xde>br\t%0,%1,%2 ma<xde>br\t%0,%1,%2
ma<xde>b\t%0,%1,%2" ma<xde>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmul<mode>")]) (set_attr "type" "fmadd<mode>")])
; msxbr, msdbr, msebr, msxb, msdb, mseb ; msxbr, msdbr, msebr, msxb, msdb, mseb
(define_insn "*fmsub<mode>" (define_insn "*fmsub<mode>"
...@@ -5340,7 +5511,7 @@ ...@@ -5340,7 +5511,7 @@
ms<xde>br\t%0,%1,%2 ms<xde>br\t%0,%1,%2
ms<xde>b\t%0,%1,%2" ms<xde>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmul<mode>")]) (set_attr "type" "fmadd<mode>")])
;; ;;
;;- Divide and modulo instructions. ;;- Divide and modulo instructions.
...@@ -5795,39 +5966,44 @@ ...@@ -5795,39 +5966,44 @@
(define_insn "*anddi3_cc" (define_insn "*anddi3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
(match_operand:DI 2 "general_operand" "d,RT")) (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d, d")
(and:DI (match_dup 1) (match_dup 2)))] (and:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
ngr\t%0,%2 ngr\t%0,%2
ngrk\t%0,%1,%2
ng\t%0,%2" ng\t%0,%2"
[(set_attr "op_type" "RRE,RXY") [(set_attr "op_type" "RRE,RRF,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*anddi3_cconly" (define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
(match_operand:DI 2 "general_operand" "d,RT")) (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d, d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
/* Do not steal TM patterns. */ /* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0" && s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@ "@
ngr\t%0,%2 ngr\t%0,%2
ngrk\t%0,%1,%2
ng\t%0,%2" ng\t%0,%2"
[(set_attr "op_type" "RRE,RXY") [(set_attr "op_type" "RRE,RRF,RXY")
(set_attr "z10prop" "z10_super_E1, z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*anddi3" (define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") [(set (match_operand:DI 0 "nonimmediate_operand"
"=d,d, d, d, d, d, d, d,d,d, d, AQ,Q")
(and:DI (match_operand:DI 1 "nonimmediate_operand" (and:DI (match_operand:DI 1 "nonimmediate_operand"
"%d,o,0,0,0,0,0,0,0,0,0,0") "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
(match_operand:DI 2 "general_operand" (match_operand:DI 2 "general_operand"
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q"))) "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
...@@ -5840,11 +6016,12 @@ ...@@ -5840,11 +6016,12 @@
nihf\t%0,%m2 nihf\t%0,%m2
nilf\t%0,%m2 nilf\t%0,%m2
ngr\t%0,%2 ngr\t%0,%2
ngrk\t%0,%1,%2
ng\t%0,%2 ng\t%0,%2
# #
#" #"
[(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
(set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*") (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
(set_attr "z10prop" "*, (set_attr "z10prop" "*,
*, *,
z10_super_E1, z10_super_E1,
...@@ -5854,6 +6031,7 @@ ...@@ -5854,6 +6031,7 @@
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
*,
z10_super_E1, z10_super_E1,
*, *,
*")]) *")])
...@@ -5875,43 +6053,49 @@ ...@@ -5875,43 +6053,49 @@
(define_insn "*andsi3_cc" (define_insn "*andsi3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
(match_operand:SI 2 "general_operand" "Os,d,R,T")) (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d,d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
(and:SI (match_dup 1) (match_dup 2)))] (and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
nilf\t%0,%o2 nilf\t%0,%o2
nr\t%0,%2 nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2 n\t%0,%2
ny\t%0,%2" ny\t%0,%2"
[(set_attr "op_type" "RIL,RR,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_cconly" (define_insn "*andsi3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
(match_operand:SI 2 "general_operand" "Os,d,R,T")) (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 0 "=d,d,d,d"))] (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode) "s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */ /* Do not steal TM patterns. */
&& s390_single_part (operands[2], SImode, HImode, 0) < 0" && s390_single_part (operands[2], SImode, HImode, 0) < 0"
"@ "@
nilf\t%0,%o2 nilf\t%0,%o2
nr\t%0,%2 nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2 n\t%0,%2
ny\t%0,%2" ny\t%0,%2"
[(set_attr "op_type" "RIL,RR,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_zarch" (define_insn "*andsi3_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") [(set (match_operand:SI 0 "nonimmediate_operand"
"=d,d, d, d, d,d,d,d,d, AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand" (and:SI (match_operand:SI 1 "nonimmediate_operand"
"%d,o,0,0,0,0,0,0,0,0") "%d,o, 0, 0, 0,0,d,0,0, 0,0")
(match_operand:SI 2 "general_operand" (match_operand:SI 2 "general_operand"
"M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q"))) " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
...@@ -5921,26 +6105,29 @@ ...@@ -5921,26 +6105,29 @@
nill\t%0,%j2 nill\t%0,%j2
nilf\t%0,%o2 nilf\t%0,%o2
nr\t%0,%2 nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2 n\t%0,%2
ny\t%0,%2 ny\t%0,%2
# #
#" #"
[(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS") [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
(set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
(set_attr "z10prop" "*, (set_attr "z10prop" "*,
*, *,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
*,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
*, *,
*")]) *")])
(define_insn "*andsi3_esa" (define_insn "*andsi3_esa"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
(match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
...@@ -5967,18 +6154,20 @@ ...@@ -5967,18 +6154,20 @@
; ;
(define_insn "*andhi3_zarch" (define_insn "*andhi3_zarch"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
(match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
nr\t%0,%2 nr\t%0,%2
nrk\t%0,%1,%2
nill\t%0,%x2 nill\t%0,%x2
# #
#" #"
[(set_attr "op_type" "RR,RI,SI,SS") [(set_attr "op_type" "RR,RRF,RI,SI,SS")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*") (set_attr "cpu_facility" "*,z196,*,*,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
]) ])
(define_insn "*andhi3_esa" (define_insn "*andhi3_esa"
...@@ -6010,19 +6199,21 @@ ...@@ -6010,19 +6199,21 @@
; ;
(define_insn "*andqi3_zarch" (define_insn "*andqi3_zarch"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
(match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
nr\t%0,%2 nr\t%0,%2
nrk\t%0,%1,%2
nill\t%0,%b2 nill\t%0,%b2
ni\t%S0,%b2 ni\t%S0,%b2
niy\t%S0,%b2 niy\t%S0,%b2
#" #"
[(set_attr "op_type" "RR,RI,SI,SIY,SS") [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) (set_attr "cpu_facility" "*,z196,*,*,*,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
(define_insn "*andqi3_esa" (define_insn "*andqi3_esa"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
...@@ -6049,7 +6240,8 @@ ...@@ -6049,7 +6240,8 @@
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
"nc\t%O0(%2,%R0),%S1" "nc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")]) [(set_attr "op_type" "SS")
(set_attr "z196prop" "z196_cracked")])
(define_split (define_split
[(set (match_operand 0 "memory_operand" "") [(set (match_operand 0 "memory_operand" "")
...@@ -6114,36 +6306,42 @@ ...@@ -6114,36 +6306,42 @@
(define_insn "*iordi3_cc" (define_insn "*iordi3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
(match_operand:DI 2 "general_operand" "d,RT")) (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d, d")
(ior:DI (match_dup 1) (match_dup 2)))] (ior:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
ogr\t%0,%2 ogr\t%0,%2
ogrk\t%0,%1,%2
og\t%0,%2" og\t%0,%2"
[(set_attr "op_type" "RRE,RXY") [(set_attr "op_type" "RRE,RRF,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*iordi3_cconly" (define_insn "*iordi3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
(match_operand:DI 2 "general_operand" "d,RT")) (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
ogr\t%0,%2 ogr\t%0,%2
ogrk\t%0,%1,%2
og\t%0,%2" og\t%0,%2"
[(set_attr "op_type" "RRE,RXY") [(set_attr "op_type" "RRE,RRF,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*iordi3" (define_insn "*iordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") [(set (match_operand:DI 0 "nonimmediate_operand"
(ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") "=d, d, d, d, d, d,d,d, d, AQ,Q")
(ior:DI (match_operand:DI 1 "nonimmediate_operand"
" %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
(match_operand:DI 2 "general_operand" (match_operand:DI 2 "general_operand"
"N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q"))) "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
...@@ -6154,11 +6352,12 @@ ...@@ -6154,11 +6352,12 @@
oihf\t%0,%k2 oihf\t%0,%k2
oilf\t%0,%k2 oilf\t%0,%k2
ogr\t%0,%2 ogr\t%0,%2
ogrk\t%0,%1,%2
og\t%0,%2 og\t%0,%2
# #
#" #"
[(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
(set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*") (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
(set_attr "z10prop" "z10_super_E1, (set_attr "z10prop" "z10_super_E1,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
...@@ -6166,6 +6365,7 @@ ...@@ -6166,6 +6365,7 @@
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
*,
z10_super_E1, z10_super_E1,
*, *,
*")]) *")])
...@@ -6186,39 +6386,43 @@ ...@@ -6186,39 +6386,43 @@
(define_insn "*iorsi3_cc" (define_insn "*iorsi3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
(match_operand:SI 2 "general_operand" "Os,d,R,T")) (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d,d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
(ior:SI (match_dup 1) (match_dup 2)))] (ior:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
oilf\t%0,%o2 oilf\t%0,%o2
or\t%0,%2 or\t%0,%2
ork\t%0,%1,%2
o\t%0,%2 o\t%0,%2
oy\t%0,%2" oy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_cconly" (define_insn "*iorsi3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
(match_operand:SI 2 "general_operand" "Os,d,R,T")) (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 0 "=d,d,d,d"))] (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
oilf\t%0,%o2 oilf\t%0,%o2
or\t%0,%2 or\t%0,%2
ork\t%0,%1,%2
o\t%0,%2 o\t%0,%2
oy\t%0,%2" oy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_zarch" (define_insn "*iorsi3_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
(match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q"))) (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
...@@ -6226,15 +6430,18 @@ ...@@ -6226,15 +6430,18 @@
oill\t%0,%i2 oill\t%0,%i2
oilf\t%0,%o2 oilf\t%0,%o2
or\t%0,%2 or\t%0,%2
ork\t%0,%1,%2
o\t%0,%2 o\t%0,%2
oy\t%0,%2 oy\t%0,%2
# #
#" #"
[(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS") [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
(set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
(set_attr "z10prop" "z10_super_E1, (set_attr "z10prop" "z10_super_E1,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
*,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
*, *,
...@@ -6269,18 +6476,20 @@ ...@@ -6269,18 +6476,20 @@
; ;
(define_insn "*iorhi3_zarch" (define_insn "*iorhi3_zarch"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
(ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
(match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
or\t%0,%2 or\t%0,%2
ork\t%0,%1,%2
oill\t%0,%x2 oill\t%0,%x2
# #
#" #"
[(set_attr "op_type" "RR,RI,SI,SS") [(set_attr "op_type" "RR,RRF,RI,SI,SS")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) (set_attr "cpu_facility" "*,z196,*,*,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
(define_insn "*iorhi3_esa" (define_insn "*iorhi3_esa"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
...@@ -6310,19 +6519,22 @@ ...@@ -6310,19 +6519,22 @@
; ;
(define_insn "*iorqi3_zarch" (define_insn "*iorqi3_zarch"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
(match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
or\t%0,%2 or\t%0,%2
ork\t%0,%1,%2
oill\t%0,%b2 oill\t%0,%b2
oi\t%S0,%b2 oi\t%S0,%b2
oiy\t%S0,%b2 oiy\t%S0,%b2
#" #"
[(set_attr "op_type" "RR,RI,SI,SIY,SS") [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) (set_attr "cpu_facility" "*,z196,*,*,*,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
z10_super,z10_super,*")])
(define_insn "*iorqi3_esa" (define_insn "*iorqi3_esa"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
...@@ -6349,7 +6561,8 @@ ...@@ -6349,7 +6561,8 @@
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
"oc\t%O0(%2,%R0),%S1" "oc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")]) [(set_attr "op_type" "SS")
(set_attr "z196prop" "z196_cracked")])
(define_split (define_split
[(set (match_operand 0 "memory_operand" "") [(set (match_operand 0 "memory_operand" "")
...@@ -6414,47 +6627,52 @@ ...@@ -6414,47 +6627,52 @@
(define_insn "*xordi3_cc" (define_insn "*xordi3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
(match_operand:DI 2 "general_operand" "d,RT")) (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d, d")
(xor:DI (match_dup 1) (match_dup 2)))] (xor:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
xgr\t%0,%2 xgr\t%0,%2
xgrk\t%0,%1,%2
xg\t%0,%2" xg\t%0,%2"
[(set_attr "op_type" "RRE,RXY") [(set_attr "op_type" "RRE,RRF,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*xordi3_cconly" (define_insn "*xordi3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
(match_operand:DI 2 "general_operand" "d,RT")) (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d, d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
xgr\t%0,%2 xgr\t%0,%2
xgrk\t%0,%1,%2
xg\t%0,%2" xg\t%0,%2"
[(set_attr "op_type" "RRE,RXY") [(set_attr "op_type" "RRE,RRF,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,z196,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*xordi3" (define_insn "*xordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
(match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q"))) (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
xihf\t%0,%k2 xihf\t%0,%k2
xilf\t%0,%k2 xilf\t%0,%k2
xgr\t%0,%2 xgr\t%0,%2
xgrk\t%0,%1,%2
xg\t%0,%2 xg\t%0,%2
# #
#" #"
[(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS") [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
(set_attr "cpu_facility" "extimm,extimm,*,*,*,*") (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
*,z10_super_E1,*,*")])
(define_split (define_split
[(set (match_operand:DI 0 "s_operand" "") [(set (match_operand:DI 0 "s_operand" "")
...@@ -6472,50 +6690,59 @@ ...@@ -6472,50 +6690,59 @@
(define_insn "*xorsi3_cc" (define_insn "*xorsi3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
(match_operand:SI 2 "general_operand" "Os,d,R,T")) (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d,d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
(xor:SI (match_dup 1) (match_dup 2)))] (xor:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
xilf\t%0,%o2 xilf\t%0,%o2
xr\t%0,%2 xr\t%0,%2
xrk\t%0,%1,%2
x\t%0,%2 x\t%0,%2
xy\t%0,%2" xy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1")])
(define_insn "*xorsi3_cconly" (define_insn "*xorsi3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
(match_operand:SI 2 "general_operand" "Os,d,R,T")) (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 0 "=d,d,d,d"))] (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
xilf\t%0,%o2 xilf\t%0,%o2
xr\t%0,%2 xr\t%0,%2
xrk\t%0,%1,%2
x\t%0,%2 x\t%0,%2
xy\t%0,%2" xy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (set_attr "cpu_facility" "*,*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1")])
(define_insn "*xorsi3" (define_insn "*xorsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
(match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q"))) (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)" "s390_logical_operator_ok_p (operands)"
"@ "@
xilf\t%0,%o2 xilf\t%0,%o2
xr\t%0,%2 xr\t%0,%2
xrk\t%0,%1,%2
x\t%0,%2 x\t%0,%2
xy\t%0,%2 xy\t%0,%2
# #
#" #"
[(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,*,*")])
(define_split (define_split
[(set (match_operand:SI 0 "s_operand" "") [(set (match_operand:SI 0 "s_operand" "")
...@@ -6532,18 +6759,20 @@ ...@@ -6532,18 +6759,20 @@
; ;
(define_insn "*xorhi3" (define_insn "*xorhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
(xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
(match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q"))) (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)" "s390_logical_operator_ok_p (operands)"
"@ "@
xilf\t%0,%x2 xilf\t%0,%x2
xr\t%0,%2 xr\t%0,%2
xrk\t%0,%1,%2
# #
#" #"
[(set_attr "op_type" "RIL,RR,SI,SS") [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) (set_attr "cpu_facility" "*,*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
(define_split (define_split
[(set (match_operand:HI 0 "s_operand" "") [(set (match_operand:HI 0 "s_operand" "")
...@@ -6560,19 +6789,21 @@ ...@@ -6560,19 +6789,21 @@
; ;
(define_insn "*xorqi3" (define_insn "*xorqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
(match_operand:QI 2 "general_operand" "Os,d,n,n,Q"))) (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)" "s390_logical_operator_ok_p (operands)"
"@ "@
xilf\t%0,%b2 xilf\t%0,%b2
xr\t%0,%2 xr\t%0,%2
xrk\t%0,%1,%2
xi\t%S0,%b2 xi\t%S0,%b2
xiy\t%S0,%b2 xiy\t%S0,%b2
#" #"
[(set_attr "op_type" "RIL,RR,SI,SIY,SS") [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) (set_attr "cpu_facility" "*,*,z196,*,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
; ;
...@@ -6644,7 +6875,8 @@ ...@@ -6644,7 +6875,8 @@
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
"xc\t%O0(%1,%R0),%S0" "xc\t%O0(%1,%R0),%S0"
[(set_attr "op_type" "SS")]) [(set_attr "op_type" "SS")
(set_attr "z196prop" "z196_cracked")])
(define_peephole2 (define_peephole2
[(parallel [(parallel
...@@ -7167,7 +7399,7 @@ ...@@ -7167,7 +7399,7 @@
; ;
; (ashl|lshr)(di|si)3 instruction pattern(s). ; (ashl|lshr)(di|si)3 instruction pattern(s).
; ; Left shifts and logical right shifts
(define_expand "<shift><mode>3" (define_expand "<shift><mode>3"
[(set (match_operand:DSI 0 "register_operand" "") [(set (match_operand:DSI 0 "register_operand" "")
...@@ -7184,18 +7416,22 @@ ...@@ -7184,18 +7416,22 @@
"!TARGET_ZARCH" "!TARGET_ZARCH"
"s<lr>dl\t%0,%Y2" "s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")
(set_attr "z196prop" "z196_cracked")])
; sll, srl, sllg, srlg ; sll, srl, sllg, srlg, sllk, srlk
(define_insn "*<shift><mode>3" (define_insn "*<shift><mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d,d")
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
"" ""
"s<lr>l<g>\t%0,<1>%Y2" "@
[(set_attr "op_type" "RS<E>") s<lr>l<g>\t%0,<1>%Y2
(set_attr "atype" "reg") s<lr>l<gk>\t%0,%1,%Y2"
(set_attr "z10prop" "z10_super_E1")]) [(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
; sldl, srdl ; sldl, srdl
(define_insn "*<shift>di3_31_and" (define_insn "*<shift>di3_31_and"
...@@ -7208,21 +7444,24 @@ ...@@ -7208,21 +7444,24 @@
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
; sll, srl, sllg, srlg ; sll, srl, sllg, srlg, sllk, srlk
(define_insn "*<shift><mode>3_and" (define_insn "*<shift><mode>3_and"
[(set (match_operand:GPR 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d,d")
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
(match_operand:SI 3 "const_int_operand" "n"))))] (match_operand:SI 3 "const_int_operand" "n,n"))))]
"(INTVAL (operands[3]) & 63) == 63" "(INTVAL (operands[3]) & 63) == 63"
"s<lr>l<g>\t%0,<1>%Y2" "@
[(set_attr "op_type" "RS<E>") s<lr>l<g>\t%0,<1>%Y2
(set_attr "atype" "reg") s<lr>l<gk>\t%0,%1,%Y2"
(set_attr "z10prop" "z10_super_E1")]) [(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
; ;
; ashr(di|si)3 instruction pattern(s). ; ashr(di|si)3 instruction pattern(s).
; ; Arithmetic right shifts
(define_expand "ashr<mode>3" (define_expand "ashr<mode>3"
[(parallel [(parallel
...@@ -7266,44 +7505,53 @@ ...@@ -7266,44 +7505,53 @@
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
; sra, srag ; sra, srag, srak
(define_insn "*ashr<mode>3_cc" (define_insn "*ashr<mode>3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
(const_int 0))) (const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d") (set (match_operand:GPR 0 "register_operand" "=d,d")
(ashiftrt:GPR (match_dup 1) (match_dup 2)))] (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"sra<g>\t%0,<1>%Y2" "@
[(set_attr "op_type" "RS<E>") sra<g>\t%0,<1>%Y2
(set_attr "atype" "reg") sra<gk>\t%0,%1,%Y2"
(set_attr "z10prop" "z10_super_E1")]) [(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
; sra, srag ; sra, srag, srak
(define_insn "*ashr<mode>3_cconly" (define_insn "*ashr<mode>3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:GPR 0 "=d"))] (clobber (match_scratch:GPR 0 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"sra<g>\t%0,<1>%Y2" "@
[(set_attr "op_type" "RS<E>") sra<g>\t%0,<1>%Y2
(set_attr "atype" "reg") sra<gk>\t%0,%1,%Y2"
(set_attr "z10prop" "z10_super_E1")]) [(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
; sra, srag ; sra, srag
(define_insn "*ashr<mode>3" (define_insn "*ashr<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d,d")
(ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" ""
"sra<g>\t%0,<1>%Y2" "@
[(set_attr "op_type" "RS<E>") sra<g>\t%0,<1>%Y2
(set_attr "atype" "reg") sra<gk>\t%0,%1,%Y2"
(set_attr "z10prop" "z10_super_E1")]) [(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
; shift pattern with implicit ANDs ; shift pattern with implicit ANDs
...@@ -7346,47 +7594,55 @@ ...@@ -7346,47 +7594,55 @@
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
; sra, srag ; sra, srag, srak
(define_insn "*ashr<mode>3_cc_and" (define_insn "*ashr<mode>3_cc_and"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
(match_operand:SI 3 "const_int_operand" "n"))) (match_operand:SI 3 "const_int_operand" "n,n")))
(const_int 0))) (const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d") (set (match_operand:GPR 0 "register_operand" "=d,d")
(ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
"sra<g>\t%0,<1>%Y2" "@
[(set_attr "op_type" "RS<E>") sra<g>\t%0,<1>%Y2
(set_attr "atype" "reg") sra<gk>\t%0,%1,%Y2"
(set_attr "z10prop" "z10_super_E1")]) [(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
; sra, srag ; sra, srag, srak
(define_insn "*ashr<mode>3_cconly_and" (define_insn "*ashr<mode>3_cconly_and"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
(match_operand:SI 3 "const_int_operand" "n"))) (match_operand:SI 3 "const_int_operand" "n,n")))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:GPR 0 "=d"))] (clobber (match_scratch:GPR 0 "=d,d"))]
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
"sra<g>\t%0,<1>%Y2" "@
[(set_attr "op_type" "RS<E>") sra<g>\t%0,<1>%Y2
(set_attr "atype" "reg") sra<gk>\t%0,%1,%Y2"
(set_attr "z10prop" "z10_super_E1")]) [(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
; sra, srag ; sra, srag, srak
(define_insn "*ashr<mode>3_and" (define_insn "*ashr<mode>3_and"
[(set (match_operand:GPR 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d,d")
(ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
(match_operand:SI 3 "const_int_operand" "n")))) (match_operand:SI 3 "const_int_operand" "n,n"))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"(INTVAL (operands[3]) & 63) == 63" "(INTVAL (operands[3]) & 63) == 63"
"sra<g>\t%0,<1>%Y2" "@
[(set_attr "op_type" "RS<E>") sra<g>\t%0,<1>%Y2
(set_attr "atype" "reg") sra<gk>\t%0,%1,%Y2"
(set_attr "z10prop" "z10_super_E1")]) [(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "z10prop" "z10_super_E1,*")])
;; ;;
...@@ -7941,7 +8197,8 @@ ...@@ -7941,7 +8197,8 @@
(const_string "RR") (const_string "RX"))) (const_string "RR") (const_string "RX")))
(set_attr "type" "branch") (set_attr "type" "branch")
(set_attr "atype" "agen") (set_attr "atype" "agen")
(set_attr "z10prop" "z10_c")]) (set_attr "z10prop" "z10_c")
(set_attr "z196prop" "z196_cracked")])
(define_insn_and_split "doloop_di" (define_insn_and_split "doloop_di"
[(set (pc) [(set (pc)
...@@ -8261,7 +8518,8 @@ ...@@ -8261,7 +8518,8 @@
&& GET_MODE (operands[2]) == Pmode" && GET_MODE (operands[2]) == Pmode"
"bras\t%2,%0" "bras\t%2,%0"
[(set_attr "op_type" "RI") [(set_attr "op_type" "RI")
(set_attr "type" "jsr")]) (set_attr "type" "jsr")
(set_attr "z196prop" "z196_cracked")])
(define_insn "*brasl" (define_insn "*brasl"
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
...@@ -8272,7 +8530,8 @@ ...@@ -8272,7 +8530,8 @@
&& GET_MODE (operands[2]) == Pmode" && GET_MODE (operands[2]) == Pmode"
"brasl\t%2,%0" "brasl\t%2,%0"
[(set_attr "op_type" "RIL") [(set_attr "op_type" "RIL")
(set_attr "type" "jsr")]) (set_attr "type" "jsr")
(set_attr "z196prop" "z196_cracked")])
(define_insn "*basr" (define_insn "*basr"
[(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
...@@ -8289,7 +8548,8 @@ ...@@ -8289,7 +8548,8 @@
(if_then_else (match_operand 0 "register_operand" "") (if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX"))) (const_string "RR") (const_string "RX")))
(set_attr "type" "jsr") (set_attr "type" "jsr")
(set_attr "atype" "agen")]) (set_attr "atype" "agen")
(set_attr "z196prop" "z196_cracked")])
; ;
; call_value instruction pattern(s). ; call_value instruction pattern(s).
...@@ -8317,7 +8577,8 @@ ...@@ -8317,7 +8577,8 @@
&& GET_MODE (operands[3]) == Pmode" && GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1" "bras\t%3,%1"
[(set_attr "op_type" "RI") [(set_attr "op_type" "RI")
(set_attr "type" "jsr")]) (set_attr "type" "jsr")
(set_attr "z196prop" "z196_cracked")])
(define_insn "*brasl_r" (define_insn "*brasl_r"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
...@@ -8329,7 +8590,8 @@ ...@@ -8329,7 +8590,8 @@
&& GET_MODE (operands[3]) == Pmode" && GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1" "brasl\t%3,%1"
[(set_attr "op_type" "RIL") [(set_attr "op_type" "RIL")
(set_attr "type" "jsr")]) (set_attr "type" "jsr")
(set_attr "z196prop" "z196_cracked")])
(define_insn "*basr_r" (define_insn "*basr_r"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
...@@ -8347,7 +8609,8 @@ ...@@ -8347,7 +8609,8 @@
(if_then_else (match_operand 1 "register_operand" "") (if_then_else (match_operand 1 "register_operand" "")
(const_string "RR") (const_string "RX"))) (const_string "RR") (const_string "RX")))
(set_attr "type" "jsr") (set_attr "type" "jsr")
(set_attr "atype" "agen")]) (set_attr "atype" "agen")
(set_attr "z196prop" "z196_cracked")])
;; ;;
;;- Thread-local storage support. ;;- Thread-local storage support.
...@@ -8416,7 +8679,8 @@ ...@@ -8416,7 +8679,8 @@
&& GET_MODE (operands[3]) == Pmode" && GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1%J4" "bras\t%3,%1%J4"
[(set_attr "op_type" "RI") [(set_attr "op_type" "RI")
(set_attr "type" "jsr")]) (set_attr "type" "jsr")
(set_attr "z196prop" "z196_cracked")])
(define_insn "*brasl_tls" (define_insn "*brasl_tls"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
...@@ -8429,7 +8693,8 @@ ...@@ -8429,7 +8693,8 @@
&& GET_MODE (operands[3]) == Pmode" && GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1%J4" "brasl\t%3,%1%J4"
[(set_attr "op_type" "RIL") [(set_attr "op_type" "RIL")
(set_attr "type" "jsr")]) (set_attr "type" "jsr")
(set_attr "z196prop" "z196_cracked")])
(define_insn "*basr_tls" (define_insn "*basr_tls"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
...@@ -8448,7 +8713,8 @@ ...@@ -8448,7 +8713,8 @@
(if_then_else (match_operand 1 "register_operand" "") (if_then_else (match_operand 1 "register_operand" "")
(const_string "RR") (const_string "RX"))) (const_string "RR") (const_string "RX")))
(set_attr "type" "jsr") (set_attr "type" "jsr")
(set_attr "atype" "agen")]) (set_attr "atype" "agen")
(set_attr "z196prop" "z196_cracked")])
;; ;;
;;- Atomic operations ;;- Atomic operations
...@@ -8557,6 +8823,36 @@ ...@@ -8557,6 +8823,36 @@
"s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
operands[2], false); DONE;") operands[2], false); DONE;")
; z196 load and add, xor, or and and instructions
; lan, lang, lao, laog, lax, laxg, laa, laag
(define_insn "sync_<atomic><mode>"
[(parallel
[(set (match_operand:GPR 0 "memory_operand" "+QS")
(unspec_volatile:GPR
[(ATOMIC_Z196:GPR (match_dup 0)
(match_operand:GPR 1 "general_operand" "d"))]
UNSPECV_ATOMIC_OP))
(clobber (match_scratch:GPR 2 "=d"))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z196"
"la<noxa><g>\t%2,%1,%0")
; lan, lang, lao, laog, lax, laxg, laa, laag
(define_insn "sync_old_<atomic><mode>"
[(parallel
[(set (match_operand:GPR 0 "register_operand" "=d")
(match_operand:GPR 1 "memory_operand" "+QS"))
(set (match_dup 1)
(unspec_volatile
[(ATOMIC_Z196:GPR (match_dup 1)
(match_operand:GPR 2 "general_operand" "d"))]
UNSPECV_ATOMIC_OP))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z196"
"la<noxa><g>\t%0,%2,%1")
(define_expand "sync_<atomic><mode>" (define_expand "sync_<atomic><mode>"
[(set (match_operand:HQI 0 "memory_operand") [(set (match_operand:HQI 0 "memory_operand")
(ATOMIC:HQI (match_dup 0) (ATOMIC:HQI (match_dup 0)
...@@ -8775,7 +9071,8 @@ ...@@ -8775,7 +9071,8 @@
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"basr\t%0,0" "basr\t%0,0"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
(set_attr "type" "la")]) (set_attr "type" "la")
(set_attr "z196prop" "z196_cracked")])
(define_insn "main_base_31_large" (define_insn "main_base_31_large"
[(set (match_operand 0 "register_operand" "=a") [(set (match_operand 0 "register_operand" "=a")
...@@ -8783,7 +9080,8 @@ ...@@ -8783,7 +9080,8 @@
(set (pc) (label_ref (match_operand 2 "" "")))] (set (pc) (label_ref (match_operand 2 "" "")))]
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"bras\t%0,%2" "bras\t%0,%2"
[(set_attr "op_type" "RI")]) [(set_attr "op_type" "RI")
(set_attr "z196prop" "z196_cracked")])
(define_insn "main_base_64" (define_insn "main_base_64"
[(set (match_operand 0 "register_operand" "=a") [(set (match_operand 0 "register_operand" "=a")
...@@ -8811,7 +9109,8 @@ ...@@ -8811,7 +9109,8 @@
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"basr\t%0,0\;la\t%0,%1-.(%0)" "basr\t%0,0\;la\t%0,%1-.(%0)"
[(set_attr "length" "6") [(set_attr "length" "6")
(set_attr "type" "la")]) (set_attr "type" "la")
(set_attr "z196prop" "z196_cracked")])
(define_insn "reload_base_64" (define_insn "reload_base_64"
[(set (match_operand 0 "register_operand" "=a") [(set (match_operand 0 "register_operand" "=a")
...@@ -8984,7 +9283,8 @@ ...@@ -8984,7 +9283,8 @@
} }
[(set_attr "type" "load,larl") [(set_attr "type" "load,larl")
(set_attr "op_type" "RXY,RIL") (set_attr "op_type" "RXY,RIL")
(set_attr "z10prop" "z10_super")]) (set_attr "z10prop" "z10_super")
(set_attr "z196prop" "z196_alone")])
; ;
...@@ -9001,3 +9301,107 @@ ...@@ -9001,3 +9301,107 @@
[(set_attr "type" "*,load") [(set_attr "type" "*,load")
(set_attr "op_type" "RRE,RXY") (set_attr "op_type" "RRE,RXY")
(set_attr "z10prop" "z10_super")]) (set_attr "z10prop" "z10_super")])
;
; Population count instruction
;
; The S/390 popcount instruction counts the bits of op1 in 8 byte
; portions and stores the result in the corresponding bytes in op0.
(define_insn "*popcount<mode>"
[(set (match_operand:INT 0 "register_operand" "=d")
(unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z196"
"popcnt\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_expand "popcountdi2"
[; popcnt op0, op1
(parallel [(set (match_operand:DI 0 "register_operand" "")
(unspec:DI [(match_operand:DI 1 "register_operand")]
UNSPEC_POPCNT))
(clobber (reg:CC CC_REGNUM))])
; sllg op2, op0, 32
(set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
; agr op0, op2
(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
(clobber (reg:CC CC_REGNUM))])
; sllg op2, op0, 16
(set (match_operand:DI 2 "register_operand" "")
(ashift:DI (match_dup 0) (const_int 16)))
; agr op0, op2
(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
(clobber (reg:CC CC_REGNUM))])
; sllg op2, op0, 8
(set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
; agr op0, op2
(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
(clobber (reg:CC CC_REGNUM))])
; srlg op0, op0, 56
(set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
"TARGET_Z196 && TARGET_64BIT"
"operands[2] = gen_reg_rtx (DImode);")
(define_expand "popcountsi2"
[; popcnt op0, op1
(parallel [(set (match_operand:SI 0 "register_operand" "")
(unspec:SI [(match_operand:SI 1 "register_operand")]
UNSPEC_POPCNT))
(clobber (reg:CC CC_REGNUM))])
; sllk op2, op0, 16
(set (match_operand:SI 2 "register_operand" "")
(ashift:SI (match_dup 0) (const_int 16)))
; ar op0, op2
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
(clobber (reg:CC CC_REGNUM))])
; sllk op2, op0, 8
(set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
; ar op0, op2
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
(clobber (reg:CC CC_REGNUM))])
; srl op0, op0, 24
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
"TARGET_Z196"
"operands[2] = gen_reg_rtx (SImode);")
(define_expand "popcounthi2"
[; popcnt op0, op1
(parallel [(set (match_operand:HI 0 "register_operand" "")
(unspec:HI [(match_operand:HI 1 "register_operand")]
UNSPEC_POPCNT))
(clobber (reg:CC CC_REGNUM))])
; sllk op2, op0, 8
(set (match_operand:SI 2 "register_operand" "")
(ashift:SI (match_dup 0) (const_int 8)))
; ar op0, op2
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
(clobber (reg:CC CC_REGNUM))])
; srl op0, op0, 8
(set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
"TARGET_Z196"
"operands[2] = gen_reg_rtx (SImode);")
(define_expand "popcountqi2"
[; popcnt op0, op1
(parallel [(set (match_operand:QI 0 "register_operand" "")
(unspec:QI [(match_operand:QI 1 "register_operand")]
UNSPEC_POPCNT))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z196"
"")
;;
;;- Copy sign instructions
;;
(define_insn "copysign<mode>3"
[(set (match_operand:FP 0 "register_operand" "=f")
(unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
(match_operand:FP 2 "register_operand" "f")]
UNSPEC_COPYSIGN))]
"TARGET_Z196"
"cpsdr\t%0,%2,%1"
[(set_attr "op_type" "RRF")
(set_attr "type" "fsimp<mode>")])
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