re PR target/61794 (internal error: unrecognizable insn, from avx512 extract instruction)

	PR target/61794
	* config/i386/sse.md (avx512f_vextract<shuffletype>32x4_1_maskm):
	Fix instruction constraint.
	(<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>): Ditto.

testsuite/ChangeLog:

	PR target/61794
	* gcc.target/i386/pr61794.c: New test.

From-SVN: r212824

gcc/ChangeLog

+2014-07-18  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/61794
+	* config/i386/sse.md (avx512f_vextract<shuffletype>32x4_1_maskm):
+	Fix instruction constraint.
+	(<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>): Ditto.
+
 2014-07-18  Jonathan Wakely  <jwakely@redhat.com>
 
 	* doc/extend.texi (Template Instantiation): Remove stray parenthesis.

gcc/config/i386/sse.md

@@ -5892,9 +5892,10 @@
 	      (match_operand 5  "const_0_to_15_operand")]))
 	  (match_operand:<ssequartermode> 6 "memory_operand" "0")
 	  (match_operand:QI 7 "register_operand" "Yk")))]
-  "TARGET_AVX512F && (INTVAL (operands[2]) = INTVAL (operands[3]) - 1)
-  && (INTVAL (operands[3]) = INTVAL (operands[4]) - 1)
-  && (INTVAL (operands[4]) = INTVAL (operands[5]) - 1)"
+  "TARGET_AVX512F
+   && (INTVAL (operands[2]) == (INTVAL (operands[3]) - 1)
+       && INTVAL (operands[3]) == (INTVAL (operands[4]) - 1)
+       && INTVAL (operands[4]) == (INTVAL (operands[5]) - 1))"
 {
   operands[2] = GEN_INT ((INTVAL (operands[2])) >> 2);
   return "vextract<shuffletype>32x4\t{%2, %1, %0%{%7%}|%0%{%7%}, %1, %2}";
@@ -5914,9 +5915,10 @@
             (match_operand 3  "const_0_to_15_operand")
             (match_operand 4  "const_0_to_15_operand")
             (match_operand 5  "const_0_to_15_operand")])))]
-  "TARGET_AVX512F && (INTVAL (operands[2]) = INTVAL (operands[3]) - 1)
-  && (INTVAL (operands[3]) = INTVAL (operands[4]) - 1)
-  && (INTVAL (operands[4]) = INTVAL (operands[5]) - 1)"
+  "TARGET_AVX512F
+   && (INTVAL (operands[2]) == (INTVAL (operands[3]) - 1)
+       && INTVAL (operands[3]) == (INTVAL (operands[4]) - 1)
+       && INTVAL (operands[4]) == (INTVAL (operands[5]) - 1))"
 {
   operands[2] = GEN_INT ((INTVAL (operands[2])) >> 2);
   return "vextract<shuffletype>32x4\t{%2, %1, %0<mask_operand6>|%0<mask_operand6>, %1, %2}";

gcc/testsuite/ChangeLog

+2014-07-18  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/61794
+	* gcc.target/i386/pr61794.c: New test.
+
 2014-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 
 	* gcc.target/mips/umips-lwp-1.c (foo): Use a shift/add sequence
@@ -45,7 +50,7 @@
 2014-07-17  Uros Bizjak  <ubizjak@gmail.com>
 
 	* gcc.dg/atomic/c11-atomic-exec-5.c (dg-additional-options): Use
-	-mfp-trap-mode=sui instead of -miee-with-inexact for alpha*-*-*.
+	-mfp-trap-mode=sui instead of -mieee-with-inexact for alpha*-*-*.
 	* gfortran.dg/ieee/ieee_1.F90 (dg-additional-options): Ditto.
 
 2014-07-17  Paolo Carlini  <paolo.carlini@oracle.com>

gcc/testsuite/gcc.target/i386/pr61794.c

+/* { dg-do compile } */
+/* { dg-options "-mavx512f" } */
+
+#include <x86intrin.h>
+
+__m512i zmm;
+__m128i xmm;
+
+void test (void)
+{
+  xmm = _mm512_extracti32x4_epi32 (zmm, 0);
+}