Skip to content

R
riscv-gcc-1
Commit 61c07d3c by David Edelsohn
Options

rs6000.md (fix_truncdfsi2_internal): Ignore DImode in FPR as preference. 

        * config/rs6000/rs6000.md (fix_truncdfsi2_internal): Ignore DImode
        in FPR as preference.
        (fctiwz): Same.
        (floatdidf2, fix_truncdfdi2): Same.
        (floatdisf2, floatditf2, fix_trunctfdi2): Same.
        (floatditf2): Same.
        (floatsitf2, fix_trunctfsi2): SImode in GPR.
        (ctrdi): Remove FPR alternative and splitter.

From-SVN: r55212
parent 77966be3
Showing with 68 additions and 105 deletions
gcc/ChangeLog
2002-07-02 Will Cohen <wcohen@redhat.com> 2002-07-03 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.md (fix_truncdfsi2_internal): Ignore DImode
in FPR as preference.
(fctiwz): Same.
(floatdidf2, fix_truncdfdi2): Same.
(floatdisf2, floatditf2, fix_trunctfdi2): Same.
(floatditf2): Same.
(floatsitf2, fix_trunctfsi2): SImode in GPR.
(ctrdi): Remove FPR alternative and splitter.
2002-07-03 Will Cohen <wcohen@redhat.com>
* config/i386/i386.c (x86_integer_DFmode_moves): Disable for PPro. * config/i386/i386.c (x86_integer_DFmode_moves): Disable for PPro.
......
gcc/config/rs6000/rs6000.md
...@@ -5486,7 +5486,7 @@ ...@@ -5486,7 +5486,7 @@
(define_insn "*fix_truncdfsi2_internal" (define_insn "*fix_truncdfsi2_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) (clobber (match_operand:DI 2 "gpc_reg_operand" "=*f"))
(clobber (match_operand:DI 3 "memory_operand" "=o"))] (clobber (match_operand:DI 3 "memory_operand" "=o"))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
"#" "#"
...@@ -5522,7 +5522,7 @@ ...@@ -5522,7 +5522,7 @@
; because the first makes it clear that operand 0 is not live ; because the first makes it clear that operand 0 is not live
; before the instruction. ; before the instruction.
(define_insn "fctiwz" (define_insn "fctiwz"
[(set (match_operand:DI 0 "gpc_reg_operand" "=f") [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
"{fcirz|fctiwz} %0,%1" "{fcirz|fctiwz} %0,%1"
...@@ -5530,13 +5530,13 @@ ...@@ -5530,13 +5530,13 @@
(define_insn "floatdidf2" (define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT" "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"fcfid %0,%1" "fcfid %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "fix_truncdfdi2" (define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=f") [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT" "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"fctidz %0,%1" "fctidz %0,%1"
...@@ -5545,7 +5545,7 @@ ...@@ -5545,7 +5545,7 @@
;; This only is safe if rounding mode set appropriately. ;; This only is safe if rounding mode set appropriately.
(define_insn_and_split "floatdisf2" (define_insn_and_split "floatdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "f"))) (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
(clobber (match_scratch:DF 2 "=f"))] (clobber (match_scratch:DF 2 "=f"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations" "TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
"#" "#"
...@@ -8316,7 +8316,7 @@ ...@@ -8316,7 +8316,7 @@
(define_insn_and_split "floatditf2" (define_insn_and_split "floatditf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f") [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
(float:TF (match_operand:DI 1 "gpc_reg_operand" "f"))) (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f")))
(clobber (match_scratch:DF 2 "=f"))] (clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
...@@ -8330,7 +8330,7 @@ ...@@ -8330,7 +8330,7 @@
(define_insn_and_split "floatsitf2" (define_insn_and_split "floatsitf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f") [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
(float:TF (match_operand:SI 1 "gpc_reg_operand" "f"))) (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))
(clobber (match_scratch:DF 2 "=f"))] (clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#" "#"
...@@ -8342,7 +8342,7 @@ ...@@ -8342,7 +8342,7 @@
"") "")
(define_insn_and_split "fix_trunctfdi2" (define_insn_and_split "fix_trunctfdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=f") [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
(fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))] (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))]
"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
...@@ -8355,7 +8355,7 @@ ...@@ -8355,7 +8355,7 @@
"") "")
(define_insn_and_split "fix_trunctfsi2" (define_insn_and_split "fix_trunctfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=f") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))] (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#" "#"
...@@ -13333,11 +13333,9 @@ ...@@ -13333,11 +13333,9 @@
(plus:DI (match_dup 0) (plus:DI (match_dup 0)
(const_int -1))) (const_int -1)))
(clobber (match_scratch:CC 2 "")) (clobber (match_scratch:CC 2 ""))
(clobber (match_scratch:DI 3 "")) (clobber (match_scratch:DI 3 ""))])]
(clobber (match_dup 4))])]
"TARGET_POWERPC64" "TARGET_POWERPC64"
" "")
{ operands[4] = gen_reg_rtx (DImode); }")
;; We need to be able to do this for any operand, including MEM, or we ;; We need to be able to do this for any operand, including MEM, or we
;; will cause reload to blow up since we don't allow output reloads on ;; will cause reload to blow up since we don't allow output reloads on
...@@ -13395,16 +13393,15 @@ ...@@ -13395,16 +13393,15 @@
(define_insn "*ctrdi_internal1" (define_insn "*ctrdi_internal1"
[(set (pc) [(set (pc)
(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1)) (const_int 1))
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc))) (pc)))
(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1) (plus:DI (match_dup 1)
(const_int -1))) (const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:CC 3 "=X,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,r,r")) (clobber (match_scratch:DI 4 "=X,X,r"))]
(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"* "*
{ {
...@@ -13416,20 +13413,19 @@ ...@@ -13416,20 +13413,19 @@
return \"bdz $+8\;b %l0\"; return \"bdz $+8\;b %l0\";
}" }"
[(set_attr "type" "branch") [(set_attr "type" "branch")
(set_attr "length" "*,12,16,24")]) (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal2" (define_insn "*ctrdi_internal2"
[(set (pc) [(set (pc)
(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1)) (const_int 1))
(pc) (pc)
(label_ref (match_operand 0 "" "")))) (label_ref (match_operand 0 "" ""))))
(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1) (plus:DI (match_dup 1)
(const_int -1))) (const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:CC 3 "=X,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,r,r")) (clobber (match_scratch:DI 4 "=X,X,r"))]
(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"* "*
{ {
...@@ -13441,7 +13437,7 @@ ...@@ -13441,7 +13437,7 @@
return \"{bdn|bdnz} $+8\;b %l0\"; return \"{bdn|bdnz} $+8\;b %l0\";
}" }"
[(set_attr "type" "branch") [(set_attr "type" "branch")
(set_attr "length" "*,12,16,24")]) (set_attr "length" "*,12,16")])
;; Similar, but we can use GE since we have a REG_NONNEG. ;; Similar, but we can use GE since we have a REG_NONNEG.
...@@ -13495,16 +13491,15 @@ ...@@ -13495,16 +13491,15 @@
(define_insn "*ctrdi_internal3" (define_insn "*ctrdi_internal3"
[(set (pc) [(set (pc)
(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 0)) (const_int 0))
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc))) (pc)))
(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1) (plus:DI (match_dup 1)
(const_int -1))) (const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:CC 3 "=X,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,r,r")) (clobber (match_scratch:DI 4 "=X,X,r"))]
(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"* "*
{ {
...@@ -13516,20 +13511,19 @@ ...@@ -13516,20 +13511,19 @@
return \"bdz $+8\;b %l0\"; return \"bdz $+8\;b %l0\";
}" }"
[(set_attr "type" "branch") [(set_attr "type" "branch")
(set_attr "length" "*,12,16,24")]) (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal4" (define_insn "*ctrdi_internal4"
[(set (pc) [(set (pc)
(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 0)) (const_int 0))
(pc) (pc)
(label_ref (match_operand 0 "" "")))) (label_ref (match_operand 0 "" ""))))
(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1) (plus:DI (match_dup 1)
(const_int -1))) (const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:CC 3 "=X,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,r,r")) (clobber (match_scratch:DI 4 "=X,X,r"))]
(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"* "*
{ {
...@@ -13541,7 +13535,7 @@ ...@@ -13541,7 +13535,7 @@
return \"{bdn|bdnz} $+8\;b %l0\"; return \"{bdn|bdnz} $+8\;b %l0\";
}" }"
[(set_attr "type" "branch") [(set_attr "type" "branch")
(set_attr "length" "*,12,16,24")]) (set_attr "length" "*,12,16")])
;; Similar but use EQ ;; Similar but use EQ
...@@ -13595,16 +13589,15 @@ ...@@ -13595,16 +13589,15 @@
(define_insn "*ctrdi_internal5" (define_insn "*ctrdi_internal5"
[(set (pc) [(set (pc)
(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1)) (const_int 1))
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc))) (pc)))
(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1) (plus:DI (match_dup 1)
(const_int -1))) (const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:CC 3 "=X,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,r,r")) (clobber (match_scratch:DI 4 "=X,X,r"))]
(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"* "*
{ {
...@@ -13616,20 +13609,19 @@ ...@@ -13616,20 +13609,19 @@
return \"{bdn|bdnz} $+8\;b %l0\"; return \"{bdn|bdnz} $+8\;b %l0\";
}" }"
[(set_attr "type" "branch") [(set_attr "type" "branch")
(set_attr "length" "*,12,16,24")]) (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal6" (define_insn "*ctrdi_internal6"
[(set (pc) [(set (pc)
(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1)) (const_int 1))
(pc) (pc)
(label_ref (match_operand 0 "" "")))) (label_ref (match_operand 0 "" ""))))
(set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1) (plus:DI (match_dup 1)
(const_int -1))) (const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:CC 3 "=X,&x,&x"))
(clobber (match_scratch:DI 4 "=X,X,r,r")) (clobber (match_scratch:DI 4 "=X,X,r"))]
(clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"* "*
{ {
...@@ -13641,7 +13633,7 @@ ...@@ -13641,7 +13633,7 @@
return \"bdz $+8\;b %l0\"; return \"bdz $+8\;b %l0\";
}" }"
[(set_attr "type" "branch") [(set_attr "type" "branch")
(set_attr "length" "*,12,16,24")]) (set_attr "length" "*,12,16")])
;; Now the splitters if we could not allocate the CTR register ;; Now the splitters if we could not allocate the CTR register
...@@ -13705,15 +13697,14 @@ ...@@ -13705,15 +13697,14 @@
(if_then_else (match_operator 2 "comparison_operator" (if_then_else (match_operator 2 "comparison_operator"
[(match_operand:DI 1 "gpc_reg_operand" "") [(match_operand:DI 1 "gpc_reg_operand" "")
(const_int 1)]) (const_int 1)])
(match_operand 6 "" "") (match_operand 5 "" "")
(match_operand 7 "" ""))) (match_operand 6 "" "")))
(set (match_operand:DI 0 "gpc_reg_operand" "") (set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (match_dup 1) (plus:DI (match_dup 1)
(const_int -1))) (const_int -1)))
(clobber (match_scratch:CC 3 "")) (clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:DI 4 "")) (clobber (match_scratch:DI 4 ""))]
(clobber (match_operand:DI 5 "nonimmediate_operand" ""))] "TARGET_POWERPC64 && reload_completed"
"TARGET_POWERPC64 && reload_completed && INT_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 3) [(parallel [(set (match_dup 3)
(compare:CC (plus:DI (match_dup 1) (compare:CC (plus:DI (match_dup 1)
(const_int -1)) (const_int -1))
...@@ -13721,11 +13712,11 @@ ...@@ -13721,11 +13712,11 @@
(set (match_dup 0) (set (match_dup 0)
(plus:DI (match_dup 1) (plus:DI (match_dup 1)
(const_int -1)))]) (const_int -1)))])
(set (pc) (if_then_else (match_dup 8) (set (pc) (if_then_else (match_dup 7)
(match_dup 6) (match_dup 5)
(match_dup 7)))] (match_dup 6)))]
" "
{ operands[8] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx); }") const0_rtx); }")
(define_split (define_split
...@@ -13733,13 +13724,12 @@ ...@@ -13733,13 +13724,12 @@
(if_then_else (match_operator 2 "comparison_operator" (if_then_else (match_operator 2 "comparison_operator"
[(match_operand:DI 1 "gpc_reg_operand" "") [(match_operand:DI 1 "gpc_reg_operand" "")
(const_int 1)]) (const_int 1)])
(match_operand 6 "" "") (match_operand 5 "" "")
(match_operand 7 "" ""))) (match_operand 6 "" "")))
(set (match_operand:DI 0 "nonimmediate_operand" "") (set (match_operand:DI 0 "nonimmediate_operand" "")
(plus:DI (match_dup 1) (const_int -1))) (plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:CC 3 "")) (clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:DI 4 "")) (clobber (match_scratch:DI 4 ""))]
(clobber (match_operand:DI 5 "nonimmediate_operand" ""))]
"TARGET_POWERPC64 && reload_completed "TARGET_POWERPC64 && reload_completed
&& ! gpc_reg_operand (operands[0], DImode)" && ! gpc_reg_operand (operands[0], DImode)"
[(parallel [(set (match_dup 3) [(parallel [(set (match_dup 3)
...@@ -13751,51 +13741,13 @@ ...@@ -13751,51 +13741,13 @@
(const_int -1)))]) (const_int -1)))])
(set (match_dup 0) (set (match_dup 0)
(match_dup 4)) (match_dup 4))
(set (pc) (if_then_else (match_dup 8) (set (pc) (if_then_else (match_dup 7)
(match_dup 6) (match_dup 5)
(match_dup 7)))] (match_dup 6)))]
" "
{ operands[8] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx); }") const0_rtx); }")
(define_split
[(set (pc)
(if_then_else (match_operator 2 "comparison_operator"
[(match_operand:DI 1 "gpc_reg_operand" "")
(const_int 1)])
(match_operand 6 "" "")
(match_operand 7 "" "")))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:DI 4 ""))
(clobber (match_operand:DI 5 "nonimmediate_operand" ""))]
"TARGET_POWERPC64 && reload_completed && FP_REGNO_P (REGNO (operands[0]))"
[(set (match_dup 5)
(match_dup 1))
(set (match_dup 4)
(match_dup 5))
(parallel [(set (match_dup 3)
(compare:CC (plus:DI (match_dup 4)
(const_int -1))
(const_int 0)))
(set (match_dup 4)
(plus:DI (match_dup 4)
(const_int -1)))])
(set (match_dup 5)
(match_dup 4))
(set (match_dup 0)
(match_dup 5))
(set (pc) (if_then_else (match_dup 8)
(match_dup 6)
(match_dup 7)))]
"
{
operands[8] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx);
}")
(define_insn "trap" (define_insn "trap"
[(trap_if (const_int 1) (const_int 0))] [(trap_if (const_int 1) (const_int 0))]
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment