Commit 5d00b10a by Alexandre Oliva Committed by Alexandre Oliva

sh.md: Clobber MACH_REG and MACL_REG in SImode, instead of just MACH_REG in DImode.

* config/sh/sh.md: Clobber MACH_REG and MACL_REG in SImode,
instead of just MACH_REG in DImode.  Always refer to FPSCR_REG
in PSImode.

From-SVN: r37720
parent 00e93036
Fri Nov 24 19:46:16 2000 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md: Clobber MACH_REG and MACL_REG in SImode,
instead of just MACH_REG in DImode. Always refer to FPSCR_REG
in PSImode.
Fri Nov 24 22:37:41 2000 Denis Chertykov <denisc@overta.ru> Fri Nov 24 22:37:41 2000 Denis Chertykov <denisc@overta.ru>
* config/avr/avr.c (out_tsthi,out_tstsi): Test simplification bug * config/avr/avr.c (out_tsthi,out_tstsi): Test simplification bug
......
...@@ -1310,7 +1310,8 @@ ...@@ -1310,7 +1310,8 @@
(mult:DI (mult:DI
(sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r")))) (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
(clobber (reg:DI MACH_REG))] (clobber (reg:SI MACH_REG))
(clobber (reg:SI MACL_REG))]
"TARGET_SH2" "TARGET_SH2"
"#") "#")
...@@ -1319,7 +1320,8 @@ ...@@ -1319,7 +1320,8 @@
(mult:DI (mult:DI
(sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "")) (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))) (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
(clobber (reg:DI MACH_REG))] (clobber (reg:SI MACH_REG))
(clobber (reg:SI MACL_REG))]
"TARGET_SH2" "TARGET_SH2"
[(const_int 0)] [(const_int 0)]
" "
...@@ -1356,7 +1358,8 @@ ...@@ -1356,7 +1358,8 @@
(mult:DI (mult:DI
(zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r")))) (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
(clobber (reg:DI MACH_REG))] (clobber (reg:SI MACH_REG))
(clobber (reg:SI MACL_REG))]
"TARGET_SH2" "TARGET_SH2"
"#") "#")
...@@ -1364,7 +1367,8 @@ ...@@ -1364,7 +1367,8 @@
[(set (match_operand:DI 0 "arith_reg_operand" "") [(set (match_operand:DI 0 "arith_reg_operand" "")
(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "")) (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))) (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
(clobber (reg:DI MACH_REG))] (clobber (reg:SI MACH_REG))
(clobber (reg:SI MACL_REG))]
"TARGET_SH2" "TARGET_SH2"
[(const_int 0)] [(const_int 0)]
" "
...@@ -3369,7 +3373,7 @@ ...@@ -3369,7 +3373,7 @@
(define_insn "calli" (define_insn "calli"
[(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
(match_operand 1 "" "")) (match_operand 1 "" ""))
(use (reg:SI FPSCR_REG)) (use (reg:PSI FPSCR_REG))
(clobber (reg:SI PR_REG))] (clobber (reg:SI PR_REG))]
"" ""
"jsr @%0%#" "jsr @%0%#"
...@@ -3384,7 +3388,7 @@ ...@@ -3384,7 +3388,7 @@
(define_insn "calli_pcrel" (define_insn "calli_pcrel"
[(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
(match_operand 1 "" "")) (match_operand 1 "" ""))
(use (reg:SI FPSCR_REG)) (use (reg:PSI FPSCR_REG))
(use (match_operand 2 "" "")) (use (match_operand 2 "" ""))
(clobber (reg:SI PR_REG))] (clobber (reg:SI PR_REG))]
"TARGET_SH2" "TARGET_SH2"
...@@ -3399,7 +3403,7 @@ ...@@ -3399,7 +3403,7 @@
[(set (match_operand 0 "" "=rf") [(set (match_operand 0 "" "=rf")
(call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(use (reg:SI FPSCR_REG)) (use (reg:PSI FPSCR_REG))
(clobber (reg:SI PR_REG))] (clobber (reg:SI PR_REG))]
"" ""
"jsr @%1%#" "jsr @%1%#"
...@@ -3413,7 +3417,7 @@ ...@@ -3413,7 +3417,7 @@
[(set (match_operand 0 "" "=rf") [(set (match_operand 0 "" "=rf")
(call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(use (reg:SI FPSCR_REG)) (use (reg:PSI FPSCR_REG))
(use (match_operand 3 "" "")) (use (match_operand 3 "" ""))
(clobber (reg:SI PR_REG))] (clobber (reg:SI PR_REG))]
"TARGET_SH2" "TARGET_SH2"
...@@ -3427,7 +3431,7 @@ ...@@ -3427,7 +3431,7 @@
(define_expand "call" (define_expand "call"
[(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" "")) [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
(match_operand 1 "" "")) (match_operand 1 "" ""))
(use (reg:SI FPSCR_REG)) (use (reg:PSI FPSCR_REG))
(clobber (reg:SI PR_REG))])] (clobber (reg:SI PR_REG))])]
"" ""
" "
...@@ -3454,7 +3458,7 @@ ...@@ -3454,7 +3458,7 @@
[(parallel [(set (match_operand 0 "arith_reg_operand" "") [(parallel [(set (match_operand 0 "arith_reg_operand" "")
(call (mem:SI (match_operand 1 "arith_reg_operand" "")) (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(use (reg:SI FPSCR_REG)) (use (reg:PSI FPSCR_REG))
(clobber (reg:SI PR_REG))])] (clobber (reg:SI PR_REG))])]
"" ""
" "
...@@ -4401,7 +4405,7 @@ ...@@ -4401,7 +4405,7 @@
;; (define_insn "fix_truncsfsi2_i4_2" ;; (define_insn "fix_truncsfsi2_i4_2"
;; [(set (match_operand:SI 0 "arith_reg_operand" "=r") ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f"))) ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
;; (use (reg:SI FPSCR_REG)) ;; (use (reg:PSI FPSCR_REG))
;; (clobber (reg:SI FPUL_REG))] ;; (clobber (reg:SI FPUL_REG))]
;; "TARGET_SH4" ;; "TARGET_SH4"
;; "#" ;; "#"
......
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