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riscv-gcc-1
Commit 5ce6f47b by Eric Christopher
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config.sub: Import from master repository. 

2002-08-15  Eric Christopher  <echristo@redhat.com>

        * config.sub: Import from master repository.
        * config.guess: Ditto.
2002-08-15  Eric Christopher  <echristo@redhat.com>
	    Jeff Knaggs  <jknaggs@redhat.com>

	* config.gcc (mipsisa64sr71k-elf): New target.
	* config/mips/sr71k.md: New file.
	* config/mips/mips.md: Use it.
	(rot*): Add sr71k specifics.
	* config/mips/t-sr71k: New file.
	* config/mips/mips.h (sr71k): New cpu.
	(TARGET_SR71K): Use it.
	(TUNE_SR71K): Ditto.
	(GENERATE_BRANCHLIKELY): Ditto.
	(ISA_HAS_MULHI, ISA_HAS_MULS, ISA_HAS_MSAC, ISA_HAS_MACC,
	ISA_HAS_ROTR_SIISA_HAS_ROTR_DI): Ditto.
	* config/mips/mips.c (sr71k): New cpu.
	(mips_use_dfa_pipeline_interface): Use.

2002-08-15  Eric Christopher  <echristo@redhat.com>
            Richard Sandiford <rsandifo@redhat.com>
	    Aldy Hernandez  <aldyh@redhat.com>
	    Graham Stott    <grahams@redhat.com>
	    Michael Meissner  <meissner@redhat.com>
	    Gavin Romig-Koch  <gavin@redhat.com>
	    Ken Raeburn  <raeburn@cygnus.com>
	    Alexandre Oliva <aoliva@redhat.com>

	* config.gcc (mips64vr-elf): New target.
	* config/mips/5400.md: New file.
	* config/mips/5500.md: Ditto.
	* config/mips/mips.md: Use them.
	(frsqrt): New.
	* config/mips/mips.c (vr4111, vr4121, vr4320, vr5400, vr5500): New
	cpus.
	(mips_issue_rate): Use them.
	(mips_use_dfa_pipeline_interface): New function. Use for 5400 and 5500.
	(TARGET_SCHEDUSE_DFA_PIPELINE_INTERFACE): Define. Use above.
	* config/mips/mips.h (vr4111, vr4121, vr4320, vr5400, vr5500): New
	cpus.
	(TARGET_MIPSx): Use them.
	(TUNE_MIPSx): Ditto.
	(GETNATE_MULT3_SI): Ditto.
	(ISA_HAS_BRANCHLIKELY): Ditto.
	(ISA_HAS_CONDMOVE): Ditto.
	(ISA_HAS_NMADD_NMSUB): Ditto.
	(ISA_HAS_MULHI): New. Ditto.
	(ISA_HAS_MULS): Ditto.
	(ISA_HAS_MSAC): Ditto.
	(ISA_HAS_MACC): Ditto.
	(ISA_HAS_ROTR_SI): Ditto.
	(ISA_HAS_ROTR_DI): Ditto.
	(RTX_COSTS): Use.

From-SVN: r56471
parent fe932535
Showing with 754 additions and 13 deletions
ChangeLog
2002-08-15 Eric Christopher <echristo@redhat.com>
* config.sub: Import from master repository.
* config.guess: Ditto.
2002-08-19 Alexandre Oliva <aoliva@redhat.com>
* Makefile.in (GCC_FOR_TARGET): Prepend STAGE_CC_WRAPPER.
......
config.guess
......@@ -3,7 +3,7 @@
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
# 2000, 2001, 2002 Free Software Foundation, Inc.
timestamp='2002-07-09'
timestamp='2002-08-19'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
......@@ -231,6 +231,7 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
# A Tn.n version is a released field test version.
# A Xn.n version is an unreleased experimental baselevel.
# 1.2 uses "1.2" for uname -r.
eval $set_cc_for_build
cat <<EOF >$dummy.s
.data
\$Lformat:
......@@ -256,7 +257,6 @@ main:
jsr \$26,exit
.end main
EOF
eval $set_cc_for_build
$CC_FOR_BUILD $dummy.s -o $dummy 2>/dev/null
if test "$?" = 0 ; then
case `$dummy` in
......@@ -281,6 +281,9 @@ EOF
2-1307)
UNAME_MACHINE="alphaev68"
;;
3-1307)
UNAME_MACHINE="alphaev7"
;;
esac
fi
rm -f $dummy.s $dummy && rmdir $tmpdir
......@@ -1079,6 +1082,9 @@ EOF
SX-5:SUPER-UX:*:*)
echo sx5-nec-superux${UNAME_RELEASE}
exit 0 ;;
SX-6:SUPER-UX:*:*)
echo sx6-nec-superux${UNAME_RELEASE}
exit 0 ;;
Power*:Rhapsody:*:*)
echo powerpc-apple-rhapsody${UNAME_RELEASE}
exit 0 ;;
......
config.sub
......@@ -3,7 +3,7 @@
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
# 2000, 2001, 2002 Free Software Foundation, Inc.
timestamp='2002-07-03'
timestamp='2002-08-20'
# This file is (in principle) common to ALL GNU software.
# The presence of a machine in this file suggests that SOME GNU software
......@@ -239,6 +239,7 @@ case $basic_machine in
| mips | mipsbe | mipseb | mipsel | mipsle \
| mips16 \
| mips64 | mips64el \
| mips64vr | mips64vrel \
| mips64orion | mips64orionel \
| mips64vr4100 | mips64vr4100el \
| mips64vr4300 | mips64vr4300el \
......@@ -246,6 +247,7 @@ case $basic_machine in
| mipsisa32 | mipsisa32el \
| mipsisa64 | mipsisa64el \
| mipsisa64sb1 | mipsisa64sb1el \
| mipsisa64sr71k | mipsisa64sr71kel \
| mipstx39 | mipstx39el \
| mn10200 | mn10300 \
| ns16k | ns32k \
......@@ -307,6 +309,7 @@ case $basic_machine in
| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
| mips16-* \
| mips64-* | mips64el-* \
| mips64vr-* | mips64vrel-* \
| mips64orion-* | mips64orionel-* \
| mips64vr4100-* | mips64vr4100el-* \
| mips64vr4300-* | mips64vr4300el-* \
......@@ -314,6 +317,7 @@ case $basic_machine in
| mipsisa32-* | mipsisa32el-* \
| mipsisa64-* | mipsisa64el-* \
| mipsisa64sb1-* | mipsisa64sb1el-* \
| mipsisa64sr71k-* | mipsisa64sr71kel-* \
| mipstx39 | mipstx39el \
| none-* | np1-* | ns16k-* | ns32k-* \
| orion-* \
......@@ -751,7 +755,7 @@ case $basic_machine in
pentium | p5 | k5 | k6 | nexgen | viac3)
basic_machine=i586-pc
;;
pentiumpro | p6 | 6x86 | athlon)
pentiumpro | p6 | 6x86 | athlon | athlon_*)
basic_machine=i686-pc
;;
pentiumii | pentium2)
......@@ -818,6 +822,12 @@ case $basic_machine in
basic_machine=a29k-amd
os=-udi
;;
sb1)
basic_machine=mipsisa64sb1-unknown
;;
sb1el)
basic_machine=mipsisa64sb1el-unknown
;;
sequent)
basic_machine=i386-sequent
;;
......
gcc/ChangeLog
2002-08-15 Eric Christopher <echristo@redhat.com>
Jeff Knaggs <jknaggs@redhat.com>
* config.gcc (mipsisa64sr71k-elf): New target.
* config/mips/sr71k.md: New file.
* config/mips/mips.md: Use it.
(rot*): Add sr71k specifics.
* config/mips/t-sr71k: New file.
* config/mips/mips.h (sr71k): New cpu.
(TARGET_SR71K): Use it.
(TUNE_SR71K): Ditto.
(GENERATE_BRANCHLIKELY): Ditto.
(ISA_HAS_MULHI, ISA_HAS_MULS, ISA_HAS_MSAC, ISA_HAS_MACC,
ISA_HAS_ROTR_SIISA_HAS_ROTR_DI): Ditto.
* config/mips/mips.c (sr71k): New cpu.
(mips_use_dfa_pipeline_interface): Use.
2002-08-15 Eric Christopher <echristo@redhat.com>
Richard Sandiford <rsandifo@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Graham Stott <grahams@redhat.com>
Michael Meissner <meissner@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Ken Raeburn <raeburn@cygnus.com>
Alexandre Oliva <aoliva@redhat.com>
* config.gcc (mips64vr-elf): New target.
* config/mips/5400.md: New file.
* config/mips/5500.md: Ditto.
* config/mips/mips.md: Use them.
(frsqrt): New.
* config/mips/mips.c (vr4111, vr4121, vr4320, vr5400, vr5500): New
cpus.
(mips_issue_rate): Use them.
(mips_use_dfa_pipeline_interface): New function. Use for 5400 and 5500.
(TARGET_SCHEDUSE_DFA_PIPELINE_INTERFACE): Define. Use above.
* config/mips/mips.h (vr4111, vr4121, vr4320, vr5400, vr5500): New
cpus.
(TARGET_MIPSx): Use them.
(TUNE_MIPSx): Ditto.
(GETNATE_MULT3_SI): Ditto.
(ISA_HAS_BRANCHLIKELY): Ditto.
(ISA_HAS_CONDMOVE): Ditto.
(ISA_HAS_NMADD_NMSUB): Ditto.
(ISA_HAS_MULHI): New. Ditto.
(ISA_HAS_MULS): Ditto.
(ISA_HAS_MSAC): Ditto.
(ISA_HAS_MACC): Ditto.
(ISA_HAS_ROTR_SI): Ditto.
(ISA_HAS_ROTR_DI): Ditto.
(RTX_COSTS): Use.
2002-08-20 John David Anglin <dave@hiauly1.hia.nrc.ca>
* cppinit.c (remove_dup_dir): Add head_ptr argument to handle removal
......
gcc/config.gcc
......@@ -1875,6 +1875,12 @@ mipsisa64-*-elf* | mipsisa64el-*-elf*)
target_cpu_default="MASK_64BIT|MASK_FLOAT64|MASK_GAS"
tm_defines="MIPS_ISA_DEFAULT=64 MIPS_ABI_DEFAULT=ABI_MEABI"
;;
mipsisa64sr71k-*-elf*)
tm_file="${tm_file} mips/elf.h"
tmake_file=mips/t-sr71k
target_cpu_default="MASK_64BIT|MASK_FLOAT64|MASK_GAS"
tm_defines="MIPS_ISA_DEFAULT=64 MIPS_CPU_STRING_DEFAULT=\\\"sr71000\\\" MIPS_ABI_DEFAULT=ABI_MEABI"
;;
mipsisa64sb1-*-elf* | mipsisa64sb1el-*-elf*)
tm_file="${tm_file} mips/elf.h"
tmake_file=mips/t-elf
......@@ -1891,6 +1897,11 @@ mips64-*-elf* | mips64el-*-elf*)
target_cpu_default="MASK_64BIT|MASK_FLOAT64|MASK_GAS"
tm_defines="MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64"
;;
mips64vr-*-elf* | mips64vrel-*-elf*)
tm_file="mips/vr.h ${tm_file} mips/elf64.h"
tm_defines="MIPS_ABI_DEFAULT=ABI_O64"
tmake_file=mips/t-vr
;;
mips64orion-*-elf* | mips64orionel-*-elf*)
tm_file="${tm_file} mips/elforion.h mips/elf64.h"
tmake_file=mips/t-elf
......
gcc/config/mips/5400.md 0 → 100644
;; DFA-based pipeline description for 5400
(define_automaton "vr54")
(define_cpu_unit "vr54_dp0" "vr54")
(define_cpu_unit "vr54_dp1" "vr54")
(define_cpu_unit "vr54_mem" "vr54")
(define_cpu_unit "vr54_mac" "vr54")
;;
;; The ordering of the instruction-execution-path/resource-usage
;; descriptions (also known as reservation RTL) is roughly ordered
;; based on the define attribute RTL for the "type" classification.
;; When modifying, remember that the first test that matches is the
;; reservation used!
;;
(define_insn_reservation "ir_vr54_unknown" 1
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "unknown"))
"vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
;; Assume prediction fails.
(define_insn_reservation "ir_vr54_branch" 3
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "branch,jump,call"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_load" 2
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "load")
(eq_attr "mode" "!SF,DF,FPSW")))
"vr54_mem")
(define_insn_reservation "ir_vr54_store" 1
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "store")
(eq_attr "mode" "!SF,DF,FPSW")))
"vr54_mem")
(define_insn_reservation "ir_vr54_fstore" 1
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "store")
(eq_attr "mode" "SF,DF")))
"vr54_mem")
;; This reservation is for conditional move based on integer
;; or floating point CC. This could probably use some refinement
;; as "move" type attr seems to be overloaded in rtl.
(define_insn_reservation "ir_vr54_move" 4
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "move"))
"vr54_dp0|vr54_dp1")
;; Move to/from FPU registers
(define_insn_reservation "ir_vr54_xfer" 2
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "xfer"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_hilo" 1
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "hilo"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_arith" 1
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "arith,darith,icmp,nop"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imul_si" 3
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "imul")
(eq_attr "mode" "SI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imul_di" 4
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "imul")
(eq_attr "mode" "DI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imadd_si" 3
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "imul"))
"vr54_mac")
(define_insn_reservation "ir_vr54_idiv_si" 42
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "SI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_idiv_di" 74
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "DI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fadd" 4
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "fadd"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fmul_sf" 5
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "fmul")
(eq_attr "mode" "SF")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fmul_df" 6
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "fmul")
(eq_attr "mode" "DF")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fmadd_sf" 9
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "fmadd")
(eq_attr "mode" "SF")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fmadd_df" 10
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "fmadd")
(eq_attr "mode" "DF")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fdiv_sf" 42
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "SF")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fdiv_df" 72
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fabs" 2
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "fabs,fneg"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fcmp" 2
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "fcmp"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_fcvt" 6
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "fcvt"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_frsqrt_sf" 61
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "SF")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_frsqrt_df" 121
(and (eq_attr "cpu" "r5400")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_multi" 1
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "multi"))
"vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
gcc/config/mips/5500.md 0 → 100644
;; DFA-based pipeline description for 5500
(define_automaton "vr55")
(define_cpu_unit "vr55_dp0" "vr55")
(define_cpu_unit "vr55_dp1" "vr55")
(define_cpu_unit "vr55_mem" "vr55")
(define_cpu_unit "vr55_mac" "vr55")
(define_cpu_unit "vr55_fp" "vr55")
(define_cpu_unit "vr55_bru" "vr55")
;;
;; The ordering of the instruction-execution-path/resource-usage
;; descriptions (also known as reservation RTL) is roughly ordered
;; based on the define attribute RTL for the "type" classification.
;; When modifying, remember that the first test that matches is the
;; reservation used!
;;
(define_insn_reservation "ir_vr55_unknown" 1
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "unknown"))
"vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru")
;; Assume prediction fails.
(define_insn_reservation "ir_vr55_branch" 2
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "branch,jump,call"))
"vr55_bru")
(define_insn_reservation "ir_vr55_load" 3
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "load"))
"vr55_mem")
(define_insn_reservation "ir_vr55_store" 1
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "store"))
"vr55_mem")
;; This reservation is for conditional move based on integer
;; or floating point CC. This could probably use some refinement
;; as "move" type attr seems to be overloaded in rtl.
(define_insn_reservation "ir_vr55_move" 2
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "move"))
"vr55_dp0|vr55_dp1")
;; Move to/from FPU registers
(define_insn_reservation "ir_vr55_xfer" 2
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "xfer"))
"vr55_dp0|vr55_dp1")
(define_insn_reservation "ir_vr55_hilo" 2
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "hilo"))
"vr55_dp0|vr55_dp1")
(define_insn_reservation "ir_vr55_arith" 1
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "arith,darith,icmp,nop"))
"vr55_dp0|vr55_dp1")
(define_insn_reservation "ir_vr55_imul_si" 3
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "imul")
(eq_attr "mode" "SI")))
"vr55_mac")
(define_insn_reservation "ir_vr55_imul_di" 4
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "imul")
(eq_attr "mode" "DI")))
"vr55_mac")
(define_insn_reservation "ir_vr55_imadd_si" 3
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "imul"))
"vr55_mac")
;; Divide algorithm is early out with best latency of 7 pcycles.
;; Use worst case for scheduling purposes.
(define_insn_reservation "ir_vr55_idiv_si" 42
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "SI")))
"vr55_mac")
(define_insn_reservation "ir_vr55_idiv_di" 74
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "DI")))
"vr55_mac")
(define_insn_reservation "ir_vr55_fadd" 4
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "fadd"))
"vr55_fp")
(define_insn_reservation "ir_vr55_fmul_sf" 5
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "fmul")
(eq_attr "mode" "SF")))
"vr55_mac")
(define_insn_reservation "ir_vr55_fmul_df" 6
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "fmul")
(eq_attr "mode" "DF")))
"vr55_mac")
(define_insn_reservation "ir_vr55_fmadd_sf" 9
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "fmadd")
(eq_attr "mode" "SF")))
"vr55_mac")
(define_insn_reservation "ir_vr55_fmadd_df" 10
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "fmadd")
(eq_attr "mode" "DF")))
"vr55_mac")
(define_insn_reservation "ir_vr55_fdiv_sf" 30
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "SF")))
"vr55_mac")
(define_insn_reservation "ir_vr55_fdiv_df" 59
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
"vr55_mac")
(define_insn_reservation "ir_vr55_fabs" 2
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "fabs,fneg"))
"vr55_fp")
(define_insn_reservation "ir_vr55_fcmp" 2
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "fcmp"))
"vr55_fp")
(define_insn_reservation "ir_vr55_fcvt_sf" 4
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "fcvt")
(eq_attr "mode" "SF")))
"vr55_fp")
(define_insn_reservation "ir_vr55_fcvt_df" 6
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "fcvt")
(eq_attr "mode" "DF")))
"vr55_fp")
(define_insn_reservation "ir_vr55_frsqrt_sf" 60
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "SF")))
"vr55_mac")
(define_insn_reservation "ir_vr55_frsqrt_df" 118
(and (eq_attr "cpu" "r5500")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
"vr55_mac")
(define_insn_reservation "ir_vr55_multi" 1
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "multi"))
"vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru")
gcc/config/mips/mips.c
......@@ -149,6 +149,7 @@ static void mips_unique_section PARAMS ((tree, int))
ATTRIBUTE_UNUSED;
static void mips_select_rtx_section PARAMS ((enum machine_mode, rtx,
unsigned HOST_WIDE_INT));
static int mips_use_dfa_pipeline_interface PARAMS ((void));
static void mips_encode_section_info PARAMS ((tree, int));
/* Structure to be filled in by compute_frame_size with register
......@@ -592,7 +593,10 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
/* MIPS III */
{ "r4000", PROCESSOR_R4000, 3 },
{ "vr4100", PROCESSOR_R4100, 3 },
{ "vr4111", PROCESSOR_R4111, 3 },
{ "vr4121", PROCESSOR_R4121, 3 },
{ "vr4300", PROCESSOR_R4300, 3 },
{ "vr4320", PROCESSOR_R4320, 3 },
{ "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
{ "r4600", PROCESSOR_R4600, 3 },
{ "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
......@@ -601,6 +605,9 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
/* MIPS IV */
{ "r8000", PROCESSOR_R8000, 4 },
{ "vr5000", PROCESSOR_R5000, 4 },
{ "vr5400", PROCESSOR_R5400, 4 },
{ "vr5500", PROCESSOR_R5500, 4 },
/* MIPS 32 */
{ "4kc", PROCESSOR_R4KC, 32 },
......@@ -609,6 +616,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
/* MIPS 64 */
{ "5kc", PROCESSOR_R5KC, 64 },
{ "20kc", PROCESSOR_R20KC, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
/* Broadcom SB-1 CPU core */
{ "sb1", PROCESSOR_SB1, 64 },
......@@ -645,6 +653,8 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
#define TARGET_SCHED_ADJUST_COST mips_adjust_cost
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
......@@ -3981,7 +3991,9 @@ output_block_move (insn, operands, num_regs, move_type)
}
/* ??? Fails because of a MIPS assembler bug? */
else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
else if (TARGET_64BIT && bytes >= 8
&& ! TARGET_SR71K
&& ! TARGET_MIPS16)
{
if (BYTES_BIG_ENDIAN)
{
......@@ -4018,7 +4030,9 @@ output_block_move (insn, operands, num_regs, move_type)
bytes -= 4;
}
else if (bytes >= 4 && ! TARGET_MIPS16)
else if (bytes >= 4
&& ! TARGET_SR71K
&& ! TARGET_MIPS16)
{
if (BYTES_BIG_ENDIAN)
{
......@@ -10455,8 +10469,9 @@ mips_issue_rate ()
{
switch (mips_tune)
{
case PROCESSOR_R3000:
return 1;
case PROCESSOR_R3000: return 1;
case PROCESSOR_R5400: return 2;
case PROCESSOR_R5500: return 2;
default:
return 1;
......@@ -10466,6 +10481,25 @@ mips_issue_rate ()
}
/* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
processors that have a DFA pipeline description. */
static int
mips_use_dfa_pipeline_interface ()
{
switch (mips_tune)
{
case PROCESSOR_R5400:
case PROCESSOR_R5500:
case PROCESSOR_SR71000:
return true;
default:
return false;
}
}
const char *
mips_emit_prefetch (operands)
rtx operands[];
......
gcc/config/mips/mips.h
......@@ -63,14 +63,20 @@ enum processor_type {
PROCESSOR_R6000,
PROCESSOR_R4000,
PROCESSOR_R4100,
PROCESSOR_R4111,
PROCESSOR_R4121,
PROCESSOR_R4300,
PROCESSOR_R4320,
PROCESSOR_R4600,
PROCESSOR_R4650,
PROCESSOR_R5000,
PROCESSOR_R5400,
PROCESSOR_R5500,
PROCESSOR_R8000,
PROCESSOR_R4KC,
PROCESSOR_R5KC,
PROCESSOR_R20KC,
PROCESSOR_SR71000,
PROCESSOR_SB1
};
......@@ -351,19 +357,27 @@ extern void sbss_section PARAMS ((void));
/* Architecture target defines. */
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100
#define TARGET_MIPS4121 (mips_arch == PROCESSOR_R4121)
#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
#define TARGET_MIPS4320 (mips_arch == PROCESSOR_R4320)
#define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
#define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
/* Scheduling target defines. */
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
#define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
/* Define preprocessor macros for the -march and -mtune options.
PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
......@@ -749,10 +763,15 @@ extern void sbss_section PARAMS ((void));
/* This is meant to be redefined in the host dependent files. */
#define SUBTARGET_TARGET_OPTIONS
#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
&& !TARGET_SR71K \
&& !TARGET_MIPS16)
/* Generate three-operand multiply instructions for SImode. */
#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
|| TARGET_MIPS4320 \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| ISA_MIPS32 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
......@@ -784,12 +803,14 @@ extern void sbss_section PARAMS ((void));
/* ISA has branch likely instructions (eg. mips2). */
/* Disable branchlikely for tx39 until compare rewrite. They haven't
been generated up to this point. */
#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
&& !TARGET_MIPS5500)
/* ISA has the conditional move instructions introduced in mips4. */
#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS64) \
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
/* ISA has just the integer condition move instructions (movn,movz) */
......@@ -820,6 +841,7 @@ extern void sbss_section PARAMS ((void));
/* ISA has floating-point nmadd and nmsub instructions. */
#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
|| ISA_MIPS64) \
&& (!TARGET_MIPS5400 || TARGET_MAD) \
&& ! TARGET_MIPS16)
/* ISA has count leading zeroes/ones instruction (not implemented). */
......@@ -832,6 +854,47 @@ extern void sbss_section PARAMS ((void));
#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
&& !TARGET_MIPS16)
/* ISA has three operand multiply instructions that put
the high part in an accumulator: mulhi or mulhiu. */
#define ISA_HAS_MULHI (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
/* ISA has three operand multiply instructions that
negates the result and puts the result in an accumulator. */
#define ISA_HAS_MULS (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
/* ISA has three operand multiply instructions that subtracts the
result from a 4th operand and puts the result in an accumulator. */
#define ISA_HAS_MSAC (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
/* ISA has three operand multiply instructions that the result
from a 4th operand and puts the result in an accumulator. */
#define ISA_HAS_MACC (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
/* ISA has 32-bit rotate right instruction. */
#define ISA_HAS_ROTR_SI (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
/* ISA has 32-bit rotate right instruction. */
#define ISA_HAS_ROTR_DI (TARGET_64BIT \
&& (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
))
/* ISA has data prefetch instruction. */
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| ISA_MIPS32 \
......@@ -3517,7 +3580,9 @@ typedef struct mips_args {
|| TUNE_MIPS3900 \
|| TUNE_MIPS5000) \
return COSTS_N_INSNS (4); \
else if (TUNE_MIPS6000) \
else if (TUNE_MIPS6000 \
|| TUNE_MIPS5400 \
|| TUNE_MIPS5500) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (7); \
......@@ -3529,7 +3594,9 @@ typedef struct mips_args {
|| TUNE_MIPS3900 \
|| TUNE_MIPS5000) \
return COSTS_N_INSNS (5); \
else if (TUNE_MIPS6000) \
else if (TUNE_MIPS6000 \
|| TUNE_MIPS5400 \
|| TUNE_MIPS5500) \
return COSTS_N_INSNS (6); \
else \
return COSTS_N_INSNS (8); \
......@@ -3539,6 +3606,8 @@ typedef struct mips_args {
return COSTS_N_INSNS (12); \
else if (TUNE_MIPS3900) \
return COSTS_N_INSNS (2); \
else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
return COSTS_N_INSNS ((xmode == DImode) ? 4 : 3); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (17); \
else if (TUNE_MIPS5000) \
......@@ -3558,6 +3627,8 @@ typedef struct mips_args {
return COSTS_N_INSNS (12); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (15); \
else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
return COSTS_N_INSNS (30); \
else \
return COSTS_N_INSNS (23); \
} \
......@@ -3567,6 +3638,8 @@ typedef struct mips_args {
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (19); \
else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
return COSTS_N_INSNS (59); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (16); \
else \
......@@ -3584,6 +3657,8 @@ typedef struct mips_args {
return COSTS_N_INSNS (38); \
else if (TUNE_MIPS5000) \
return COSTS_N_INSNS (36); \
else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
return COSTS_N_INSNS ((GET_MODE (X) == SImode) ? 42 : 74); \
else \
return COSTS_N_INSNS (69); \
\
......
gcc/config/mips/t-sr71k 0 → 100644
CONFIG2_H = $(srcdir)/config/mips/elf.h $(srcdir)/config/mips/mips.h
# Suppress building libgcc1.a, since the MIPS compiler port is complete
# and does not need anything from libgcc1.a.
LIBGCC1 =
CROSS_LIBGCC1 =
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
# Don't let CTOR_LIST end up in sdata section.
CRTSTUFF_T_CFLAGS = -G 0
# Assemble startup files.
$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
# We must build libgcc2.a with -G 0, in case the user wants to link
# without the $gp register.
TARGET_LIBGCC2_CFLAGS = -G 0
# fp-bit and dp-bit are really part of libgcc1, but this will cause
# them to be built correctly, so... [taken from t-sparclite]
# We want fine grained libraries, so use the new code to build the
# floating point emulation libraries.
FPBIT = fp-bit.c
DPBIT = dp-bit.c
dp-bit.c: $(srcdir)/config/fp-bit.c
echo '#ifdef __MIPSEL__' > dp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
echo '#endif' >> dp-bit.c
echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
cat $(srcdir)/config/fp-bit.c >> dp-bit.c
fp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define FLOAT' > fp-bit.c
echo '#ifdef __MIPSEL__' >> fp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
echo '#endif' >> fp-bit.c
echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
# Build the libraries for both hard and soft floating point
MULTILIB_OPTIONS = EL/EB msoft-float mips2
MULTILIB_DIRNAMES = el eb soft-float mips2
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
# Add additional dependencies to recompile selected modules whenever the
# tm.h file changes. The files compiled are:
#
# gcc.c (*_SPEC changes)
# toplev.c (new switches + assembly output changes)
# sdbout.c (debug format changes)
# dbxout.c (debug format changes)
# dwarfout.c (debug format changes)
# final.c (assembly output changes)
# varasm.c (assembly output changes)
# cse.c (cost functions)
# insn-output.c (possible ifdef changes in tm.h)
# regclass.c (fixed/call used register changes)
# cccp.c (new preprocessor macros, -v version #)
# explow.c (GO_IF_LEGITIMATE_ADDRESS)
# recog.c (GO_IF_LEGITIMATE_ADDRESS)
# reload.c (GO_IF_LEGITIMATE_ADDRESS)
gcc.o: $(CONFIG2_H)
toplev.o: $(CONFIG2_H)
sdbout.o: $(CONFIG2_H)
dbxout.o: $(CONFIG2_H)
dwarfout.o: $(CONFIG2_H)
final.o: $(CONFIG2_H)
varasm.o: $(CONFIG2_H)
cse.o: $(CONFIG2_H)
insn-output.o: $(CONFIG2_H)
regclass.o: $(CONFIG2_H)
cccp.o: $(CONFIG2_H)
explow.o: $(CONFIG2_H)
recog.o: $(CONFIG2_H)
reload.o: $(CONFIG2_H)
gcc/config/mips/t-vr 0 → 100644
# BEGIN boiler-plate MIPS stuff
# Don't let CTOR_LIST end up in sdata section.
CRTSTUFF_T_CFLAGS = -G 0
# We must build libgcc2.a with -G 0, in case the user wants to link
# without the $gp register.
TARGET_LIBGCC2_CFLAGS = -G 0
LIB2FUNCS_EXTRA = $(srcdir)/config/mips/mips16.S
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
# Assemble startup files.
$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
# END boiler-plate
# Endianness: EB or EL
#
# ABIs: mabi=32
# mabi=o64
# mabi=eabi
# meabi=eabi/mlong32
# mabi=eabi/mgp32
# mabi=eabi/mgp32/mlong64
#
# Architecture: march=vr5400
# march=vr4100
# march=vr4100/mips16
#
# Total: 2 * 6 * 3 = 36 multilibs.
MULTILIB_OPTIONS = \
EL/EB \
mabi=32/mabi=o64/mabi=eabi \
mgp32 \
mlong32/mlong64 \
mips16 \
march=vr5400/march=vr4100
MULTILIB_DIRNAMES = \
el eb \
o32 o64 eabi \
gp32 \
long32 long64 \
mips16 \
vr5400 vr4100
MULTILIB_MATCHES = EL=mel EB=meb
# Assume a 4000-series is the default: we'd need a *mips16 entry if
# the default processor didn't support mips16. Also assume o64,
# which means we need to extend the o64 exceptions to combinations
# without a -mabi flag.
MULTILIB_EXCEPTIONS = \
*mabi=32/mlong64* \
*mabi=32/mgp32/mlong64* \
*mabi=o64/mgp32* \
*mabi=o64/mlong64* \
mgp32* E[LB]/mgp32* \
mlong64* E[LB]/mlong64* \
*mips16/march=vr5*
# The real value of this macro is very long, so generate it using a
# shell fragment. The idea is to tell the GCC driver how -mabi,
# -mgp32, -mlong32 and -mlong64 interact, so that it choses the right
# library when some options are specified redundantly (for example,
# -mabi=32 -mgp32).
# The core equalities are listed after "for changes in ". The first
# entry assumes o64 is the default ABI.
MULTILIB_REDUNDANT_DIRS=` \
for endian in '' 'el' 'eb'; do \
for arch in '' 'vr5400' 'vr4100' \
'mips16' 'mips16/vr100'; do \
for changes in long32= \
o32/gp32=o32 \
o32/gp32/long32=o32 \
o32/long32=o32 \
o64/long32=o64 \
eabi/gp32/long32=eabi/gp32 \
eabi/long64=eabi; do \
from=\`echo \$${changes} | sed 's/=.*//'\`; \
to=\`echo \$${changes} | sed 's/.*=//'\`; \
echo \$$endian \$$from \$$arch=\$$endian \$$to \$$arch \
| sed -e 's: *= *:=:' \
-e 's: *:/:g' \
-e 's:=$$:=.:'; \
done; \
done; \
done`
gcc/config/mips/vr.h 0 → 100644
/* Definitions of target machine for GNU compiler.
NEC VR Series Processors
Copyright (c) 2002 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#define MIPS_CPU_STRING_DEFAULT "vr4100"
#define MULTILIB_DEFAULTS \
{ MULTILIB_ENDIAN_DEFAULT, MULTILIB_ABI_DEFAULT, "march=vr4100" }
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