Commit 5bbeea44 by Jan Hubicka Committed by Jan Hubicka

config.gcc: Add support for nocoma/prescott/pentium-m/pentium3m /pentium4m.

	* config.gcc: Add support for nocoma/prescott/pentium-m/pentium3m
	/pentium4m.
	* i386.c (override_options): Add support for new CPUs.
	* i386.h (TARGET_CPU_DEFAULT_NAMES): New names.
	(TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_pentium4e): New
	constants.
	* invoke.texi: Extend documentation of -mtune/-march for new CPUs.

From-SVN: r78524
parent a749e46c
2004-02-26 Jan Hubicka <jh@suse.cz>
* config.gcc: Add support for nocoma/prescott/pentium-m/pentium3m
/pentium4m.
* i386.c (override_options): Add support for new CPUs.
* i386.h (TARGET_CPU_DEFAULT_NAMES): New names.
(TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_pentium4e): New
constants.
* invoke.texi: Extend documentation of -mtune/-march for new CPUs.
2004-02-26 Bob Wilson <bob.wilson@acm.org> 2004-02-26 Bob Wilson <bob.wilson@acm.org>
* config/xtensa/xtensa.h (TARGET_CPU_CPP_BUILTINS): Define __xtensa__. * config/xtensa/xtensa.h (TARGET_CPU_CPP_BUILTINS): Define __xtensa__.
......
...@@ -2139,12 +2139,21 @@ if test x$with_cpu = x ; then ...@@ -2139,12 +2139,21 @@ if test x$with_cpu = x ; then
pentium2-*) pentium2-*)
with_cpu=pentium2 with_cpu=pentium2
;; ;;
pentium3-*) pentium3-*|pentium3m-*)
with_cpu=pentium3 with_cpu=pentium3
;; ;;
pentium4-*) pentium4-*|pentium4m-*)
with_cpu=pentium4 with_cpu=pentium4
;; ;;
prescott-*)
with_cpu=prescott
;;
nocona-*)
with_cpu=nocona
;;
pentium_m-*)
with_cpu=pentium-m
;;
*) *)
with_cpu=pentiumpro with_cpu=pentiumpro
;; ;;
...@@ -2326,7 +2335,8 @@ fi ...@@ -2326,7 +2335,8 @@ fi
| c3 | c3-2 | i686 | pentiumpro | pentium2 | pentium3 \ | c3 | c3-2 | i686 | pentiumpro | pentium2 | pentium3 \
| pentium4 | k6 | k6-2 | k6-3 | athlon | athlon-tbird \ | pentium4 | k6 | k6-2 | k6-3 | athlon | athlon-tbird \
| athlon-4 | athlon-xp | athlon-mp | k8 | opteron \ | athlon-4 | athlon-xp | athlon-mp | k8 | opteron \
| athlon64 | athlon-fx) | athlon64 | athlon-fx | prescott | pentium-m \
| pentium4m | pentium3m| nocona)
# OK # OK
;; ;;
*) *)
......
...@@ -1089,9 +1089,10 @@ override_options (void) ...@@ -1089,9 +1089,10 @@ override_options (void)
{ {
PTA_SSE = 1, PTA_SSE = 1,
PTA_SSE2 = 2, PTA_SSE2 = 2,
PTA_MMX = 4, PTA_SSE3 = 4,
PTA_PREFETCH_SSE = 8, PTA_MMX = 8,
PTA_3DNOW = 16, PTA_PREFETCH_SSE = 16,
PTA_3DNOW = 32,
PTA_3DNOW_A = 64, PTA_3DNOW_A = 64,
PTA_64BIT = 128 PTA_64BIT = 128
} flags; } flags;
...@@ -1111,8 +1112,16 @@ override_options (void) ...@@ -1111,8 +1112,16 @@ override_options (void)
{"pentiumpro", PROCESSOR_PENTIUMPRO, 0}, {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
{"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX}, {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
{"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE}, {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
{"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 | {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
PTA_MMX | PTA_PREFETCH_SSE}, {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
{"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
| PTA_MMX | PTA_PREFETCH_SSE},
{"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
| PTA_MMX | PTA_PREFETCH_SSE},
{"prescott", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_MMX | PTA_PREFETCH_SSE},
{"nocona", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
| PTA_MMX | PTA_PREFETCH_SSE},
{"k6", PROCESSOR_K6, PTA_MMX}, {"k6", PROCESSOR_K6, PTA_MMX},
{"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW}, {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
{"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW}, {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
...@@ -1234,6 +1243,9 @@ override_options (void) ...@@ -1234,6 +1243,9 @@ override_options (void)
if (processor_alias_table[i].flags & PTA_SSE2 if (processor_alias_table[i].flags & PTA_SSE2
&& !(target_flags_explicit & MASK_SSE2)) && !(target_flags_explicit & MASK_SSE2))
target_flags |= MASK_SSE2; target_flags |= MASK_SSE2;
if (processor_alias_table[i].flags & PTA_SSE3
&& !(target_flags_explicit & MASK_SSE3))
target_flags |= MASK_SSE3;
if (processor_alias_table[i].flags & PTA_PREFETCH_SSE) if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
x86_prefetch_sse = true; x86_prefetch_sse = true;
if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT)) if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
......
...@@ -691,11 +691,15 @@ extern int x86_prefetch_sse; ...@@ -691,11 +691,15 @@ extern int x86_prefetch_sse;
#define TARGET_CPU_DEFAULT_athlon 11 #define TARGET_CPU_DEFAULT_athlon 11
#define TARGET_CPU_DEFAULT_athlon_sse 12 #define TARGET_CPU_DEFAULT_athlon_sse 12
#define TARGET_CPU_DEFAULT_k8 13 #define TARGET_CPU_DEFAULT_k8 13
#define TARGET_CPU_DEFAULT_pentium_m 14
#define TARGET_CPU_DEFAULT_prescott 15
#define TARGET_CPU_DEFAULT_nocona 15
#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
"pentiumpro", "pentium2", "pentium3", \ "pentiumpro", "pentium2", "pentium3", \
"pentium4", "k6", "k6-2", "k6-3",\ "pentium4", "k6", "k6-2", "k6-3",\
"athlon", "athlon-4", "k8"} "athlon", "athlon-4", "k8", \
"pentium-m", "prescott", "nocona"}
#ifndef CC1_SPEC #ifndef CC1_SPEC
#define CC1_SPEC "%(cc1_cpu) " #define CC1_SPEC "%(cc1_cpu) "
......
...@@ -8105,11 +8105,20 @@ Intel PentiumMMX CPU based on Pentium core with MMX instruction set support. ...@@ -8105,11 +8105,20 @@ Intel PentiumMMX CPU based on Pentium core with MMX instruction set support.
Intel PentiumPro CPU. Intel PentiumPro CPU.
@item pentium2 @item pentium2
Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support. Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support.
@item pentium3 @item pentium3, pentium3m
Intel Pentium3 CPU based on PentiumPro core with MMX and SSE instruction set Intel Pentium3 CPU based on PentiumPro core with MMX and SSE instruction set
support. support.
@item pentium4 @item pentium-m
Low power version of Intel Pentium3 CPU with MMX, SSE and SSE2 instruction set
support. Used by Centrino notebooks.
@item pentium4, pentium4m
Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set support. Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set support.
@item prescott
Improved version of Intel Pentium4 CPU with MMX, SSE, SSE2 and SSE3 instruction
set support.
@item nocona
Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE,
SSE2 and SSE3 instruction set support.
@item k6 @item k6
AMD K6 CPU with MMX instruction set support. AMD K6 CPU with MMX instruction set support.
@item k6-2, k6-3 @item k6-2, k6-3
......
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