Skip to content

R
riscv-gcc-1
Commit 5a9335ef by Nick Clifton Committed by Nick Clifton
Options

config.gcc: Add an extra_header for ARM targets. 

	* config.gcc: Add an extra_header for ARM targets.
        Support configuring with --with-cpu=iwmmxt.
	* doc/invoke.texi: Document new value for -mcpu= ARM switch.
        * config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
	names.  Fix formatting.
        * config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
	names.
        * config/arm/arm-protos.h (arm_emit_vector_const): New
	prototype.
	(arm_output_load_gr): New prototype.
	* config/arm/arm.c (extra_reg_names1): Delete.
        (TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
	* arch_is_iwmmxt): Define.
	(all_cores, all_architecture): Add entry for iwmmxt.
	(arm_override_options): Add support for iwmmxt.
	(use_return_insn, arm_function_arg, arm_legitimate_index_p,
	arm_print_value, arm_rtx_costs_1, output_move_double,
	arm_compute_save_reg_mask, arm_output_epilogue,
	arm_get_frame_size, arm_expand_prologue, arm_print_operand,
	arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
	Likewise.
	(arm_init_cumulative_args): Count iwmmxt registers.
	(arm_function_ok_for_sibcall): Return false of sibcall_blocked
	has been set.
	(struct minipool_node): Add fix_size field.
	(add_minipool_forward_ref): Add support for 8-byte aligning of
	the pool.
	(add_minipool_backward_ref, add_minipool_offsets,
	dump_minipool, push_minipool_fix): Likewise.
	(struct builtin_description): New struct.
        (builtin_description): New array of iwmmxt builtin functions.
        (arm_init_iwmmxt_builtins): New function.
        (arm_init_builtins): New function.
        (safe_vector_operand): New function.
        (arm_expand_binop_builtin): New function.
        (arm_expand_unop_builtin): New function.
        (arm_expand_builtin): New function.
        (arm_emit_vector_const): New function.
        (arm_output_load_gr): New function.
        * config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
	TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
	TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
	DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
        (BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
        (CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
        (FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
	reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
	REG_CLASS_FOR_LETTER): Add iwmmxt registers.
        (SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
	registers unless the iwmmxt target is selected.
        (FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
	FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
	IS_IWMMXT_GR_REGNUM): Define.
        (FIRST_PSEUDO_REGISTER): Bump to 63.
        (struct machine_function): Add sibcall_blocked field.
        (Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
	nargs fields.
        (enum arm_builtins): New enum list.
        * config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
	UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
	UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
	UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
	(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
	VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
        (movv2si, movv4hi, movv8qi): New expands for vector moves.
        Include iwmmxt.md.
	* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
	multilib.
        (MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
        * config/arm/mmintrin.h: New ARM specific header file.
        * config/arm/iwmmx.md: New iWMMXt specific machine patterns.

From-SVN: r68157
parent 7d8b7202
Showing with 250 additions and 82 deletions
gcc/ChangeLog
2003-06-18 Nick Clifton <nickc@redhat.com>
* config.gcc: Add an extra_header for ARM targets.
Support configuring with --with-cpu=iwmmxt.
* doc/invoke.texi: Document new value for -mcpu= ARM switch.
* config/arm/aof.h (REGISTER_NAMES): Add iwmmxt register
names. Fix formatting.
* config/arm/aout.h (REGISTER_NAMES): Add iwmmxt register
names.
* config/arm/arm-protos.h (arm_emit_vector_const): New
prototype.
(arm_output_load_gr): New prototype.
* config/arm/arm.c (extra_reg_names1): Delete.
(TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN, FL_IWMMXT,
* arch_is_iwmmxt): Define.
(all_cores, all_architecture): Add entry for iwmmxt.
(arm_override_options): Add support for iwmmxt.
(use_return_insn, arm_function_arg, arm_legitimate_index_p,
arm_print_value, arm_rtx_costs_1, output_move_double,
arm_compute_save_reg_mask, arm_output_epilogue,
arm_get_frame_size, arm_expand_prologue, arm_print_operand,
arm_assemble_integer, arm_hard_regno_ok, arm_regno_class):
Likewise.
(arm_init_cumulative_args): Count iwmmxt registers.
(arm_function_ok_for_sibcall): Return false of sibcall_blocked
has been set.
(struct minipool_node): Add fix_size field.
(add_minipool_forward_ref): Add support for 8-byte aligning of
the pool.
(add_minipool_backward_ref, add_minipool_offsets,
dump_minipool, push_minipool_fix): Likewise.
(struct builtin_description): New struct.
(builtin_description): New array of iwmmxt builtin functions.
(arm_init_iwmmxt_builtins): New function.
(arm_init_builtins): New function.
(safe_vector_operand): New function.
(arm_expand_binop_builtin): New function.
(arm_expand_unop_builtin): New function.
(arm_expand_builtin): New function.
(arm_emit_vector_const): New function.
(arm_output_load_gr): New function.
* config/arm/arm.h (TARGET_CPU_iwmmxt, TARGET_IWMMXT,
TARGET_REALLY_IWMMXT, arm_arch_iwmmxt, IWMMXT_ALIGNMENT,
TYPE_NEEDS_IWMMXT_ALIGNMENT, ADJUST_FIELD_ALIGN,
DATA_ALIGNMENT, LOCAL_ALIGNMENT, VECTOR_MODE_SUPPORTED_P): Define.
(BIGGEST_ALIGNMENT): Set to 64 if ATPCS support is enabled.
(CPP_CPU_ARCH_SPEC): Add entries for iwmmxt.
(FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER,
reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS,
REG_CLASS_FOR_LETTER): Add iwmmxt registers.
(SUBTARGET_CONDITIONAL_REGISTER_USAGE): Disable iwmmxt
registers unless the iwmmxt target is selected.
(FIRST_IWMMXT_GR_REGNUM, LAST_IWMMXT_GR_REGNUM,
FIRST_IWMMXT_REGNUM, LAST_IWMMXT_REGNUM, IS_IWMMXT_REGNUM,
IS_IWMMXT_GR_REGNUM): Define.
(FIRST_PSEUDO_REGISTER): Bump to 63.
(struct machine_function): Add sibcall_blocked field.
(Struct CUMULATIVE_ARGS): Add iwmmxt_nregs, named_count and
nargs fields.
(enum arm_builtins): New enum list.
* config/arm/arm.md (UNSPEC_WSHUFH, UNSPEC_WACC,
UNSPEC_TMOVMSK, UNSPEC_WSAD, UNSPEC_WSADZ, UNSPEC_WMACS,
UNSPEC_WMACU, UNSPEC_WMACSZ, UNSPEC_WMACUZ, UNSPEC_CLRDI,
UNSPEC_WMADDS, UNSPEC_WMADDU): New unspecs.
(VUNSPEC_TMRC, VUNSPEC_TMCR, VUNSPEC_ALIGN8, VUNSPEC_WCMP_EQ,
VUNSPEC_WCMP_GTU, VUNSPEC_WCMP_GT): New vunspecs.
(movv2si, movv4hi, movv8qi): New expands for vector moves.
Include iwmmxt.md.
* config/arm/t-xscale-elf (MULTILIB_OPITONS): Add iwmmxt
multilib.
(MULTILIB_DIRNAMES, MULTILIB_REDUNDANT_DIRS): Likewise.
* config/arm/mmintrin.h: New ARM specific header file.
* config/arm/iwmmx.md: New iWMMXt specific machine patterns.
2003-06-18 J"orn Rennecke <joern.rennecke@superh.com>
* toplev.c (Remaining -d letters summary): Update.
......
gcc/config.gcc
......@@ -281,12 +281,14 @@ strongarm*-*-*)
;;
arm*-*-*)
cpu_type=arm
extra_headers="mmintrin.h"
;;
ep9312*-*-*)
cpu_type=arm
;;
xscale-*-*)
cpu_type=arm
extra_headers="mmintrin.h"
;;
i[34567]86-*-*)
cpu_type=i386
......@@ -2303,7 +2305,7 @@ then
| xarm920t | xarm940t | xarm9e | xarm10tdmi \
| xarm7100 | xarm7500 | xarm7500fe | xarm810 \
| xarm1020t \
| xxscale \
| xxscale | xiwmmxt \
| xep9312 \
| xstrongarm | xstrongarm110 | xstrongarm11[01]0)
# OK
......
gcc/config/arm/aof.h
/* Definitions of target machine for GNU compiler, for Advanced RISC Machines
ARM compilation, AOF Assembler.
Copyright (C) 1995, 1996, 1997, 2000 Free Software Foundation, Inc.
Copyright (C) 1995, 1996, 1997, 2000, 2003 Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rearnsha@armltd.co.uk)
This file is part of GCC.
......@@ -59,64 +59,70 @@
#define EXTRA_SECTIONS in_zero_init, in_common
#define EXTRA_SECTION_FUNCTIONS \
ZERO_INIT_SECTION \
COMMON_SECTION
ZERO_INIT_SECTION \
COMMON_SECTION
#define ZERO_INIT_SECTION \
void \
zero_init_section () \
{ \
void \
zero_init_section () \
{ \
static int zero_init_count = 1; \
\
if (in_section != in_zero_init) \
{ \
fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", \
zero_init_count++); \
in_section = in_zero_init; \
} \
}
}
/* Used by ASM_OUTPUT_COMMON (below) to tell varasm.c that we've
changed areas. */
#define COMMON_SECTION \
void \
common_section () \
{ \
if (in_section != in_common) \
void \
common_section () \
{ \
if (in_section != in_common) \
in_section = in_common; \
} \
}
}
#define CTOR_LIST_BEGIN \
asm (CTORS_SECTION_ASM_OP); \
extern func_ptr __CTOR_END__[1]; \
func_ptr __CTOR_LIST__[1] = {__CTOR_END__};
asm (CTORS_SECTION_ASM_OP); \
extern func_ptr __CTOR_END__[1]; \
func_ptr __CTOR_LIST__[1] = {__CTOR_END__};
#define CTOR_LIST_END \
asm (CTORS_SECTION_ASM_OP); \
func_ptr __CTOR_END__[1] = { (func_ptr) 0 };
asm (CTORS_SECTION_ASM_OP); \
func_ptr __CTOR_END__[1] = { (func_ptr) 0 };
#define DO_GLOBAL_CTORS_BODY \
do { \
do \
{ \
func_ptr *ptr = __CTOR_LIST__ + 1; \
\
while (*ptr) \
(*ptr++) (); \
} while (0)
} \
while (0)
#define DTOR_LIST_BEGIN \
asm (DTORS_SECTION_ASM_OP); \
extern func_ptr __DTOR_END__[1]; \
func_ptr __DTOR_LIST__[1] = {__DTOR_END__};
asm (DTORS_SECTION_ASM_OP); \
extern func_ptr __DTOR_END__[1]; \
func_ptr __DTOR_LIST__[1] = {__DTOR_END__};
#define DTOR_LIST_END \
asm (DTORS_SECTION_ASM_OP); \
func_ptr __DTOR_END__[1] = { (func_ptr) 0 };
asm (DTORS_SECTION_ASM_OP); \
func_ptr __DTOR_END__[1] = { (func_ptr) 0 };
#define DO_GLOBAL_DTORS_BODY \
do { \
do \
{ \
func_ptr *ptr = __DTOR_LIST__ + 1; \
\
while (*ptr) \
(*ptr++) (); \
} while (0)
} \
while (0)
/* We really want to put Thumb tables in a read-only data section, but
switching to another section during function output is not
......@@ -171,12 +177,10 @@ do { \
#define SYMBOL__MAIN __gccmain
#define ASM_COMMENT_START ";"
#define ASM_APP_ON ""
#define ASM_APP_OFF ""
#define ASM_OUTPUT_ASCII(STREAM,PTR,LEN) \
#define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
{ \
int i; \
const char *ptr = (PTR); \
......@@ -191,16 +195,16 @@ do { \
#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '\n')
/* Output of Uninitialized Variables */
/* Output of Uninitialized Variables. */
#define ASM_OUTPUT_COMMON(STREAM,NAME,SIZE,ROUNDED) \
#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
(common_section (), \
fprintf ((STREAM), "\tAREA "), \
assemble_name ((STREAM), (NAME)), \
fprintf ((STREAM), ", DATA, COMMON\n\t%% %d\t%s size=%d\n", \
(int)(ROUNDED), ASM_COMMENT_START, (int)(SIZE)))
#define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
(zero_init_section (), \
assemble_name ((STREAM), (NAME)), \
fprintf ((STREAM), "\n"), \
......@@ -208,7 +212,6 @@ do { \
(int)(ROUNDED), ASM_COMMENT_START, (int)(SIZE)))
/* Output and Generation of Labels */
extern int arm_main_function;
/* Globalizing directive for a label. */
......@@ -258,12 +261,12 @@ do { \
#define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
sprintf ((STRING), "*|%s..%ld|", (PREFIX), (long)(NUM))
/* How initialization functions are handled */
/* How initialization functions are handled. */
#define CTORS_SECTION_ASM_OP "\tAREA\t|C$$gnu_ctorsvec|, DATA, READONLY"
#define DTORS_SECTION_ASM_OP "\tAREA\t|C$$gnu_dtorsvec|, DATA, READONLY"
/* Output of Assembler Instructions */
/* Output of Assembler Instructions. */
#define REGISTER_NAMES \
{ \
......@@ -273,7 +276,16 @@ do { \
"ip", "sp", "lr", "pc", \
"f0", "f1", "f2", "f3", \
"f4", "f5", "f6", "f7", \
"cc", "sfp", "afp" \
"cc", "sfp", "afp", \
"mv0", "mv1", "mv2", "mv3", \
"mv4", "mv5", "mv6", "mv7", \
"mv8", "mv9", "mv10", "mv11", \
"mv12", "mv13", "mv14", "mv15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
"wr0", "wr1", "wr2", "wr3", \
"wr4", "wr5", "wr6", "wr7", \
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15"
}
#define ADDITIONAL_REGISTER_NAMES \
......@@ -303,37 +315,40 @@ do { \
/* AOF does not prefix user function names with an underscore. */
#define ARM_MCOUNT_NAME "_mcount"
/* Output of Dispatch Tables */
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
do { \
/* Output of Dispatch Tables. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
do \
{ \
if (TARGET_ARM) \
fprintf ((STREAM), "\tb\t|L..%d|\n", (VALUE)); \
else \
fprintf ((STREAM), "\tDCD\t|L..%d| - |L..%d|\n", (VALUE), (REL)); \
} while (0)
} \
while (0)
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
fprintf ((STREAM), "\tDCD\t|L..%d|\n", (VALUE))
/* A label marking the start of a jump table is a data label. */
#define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
#define ASM_OUTPUT_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \
fprintf ((STREAM), "\tALIGN\n|%s..%d|\n", (PREFIX), (NUM))
/* Assembler Commands for Alignment */
/* Assembler Commands for Alignment. */
#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
fprintf ((STREAM), "\t%%\t%d\n", (int) (NBYTES))
#define ASM_OUTPUT_SKIP(STREAM,NBYTES) \
fprintf ((STREAM), "\t%%\t%d\n", (int)(NBYTES))
#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
do { \
register int amount = 1 << (POWER); \
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
do \
{ \
int amount = 1 << (POWER); \
\
if (amount == 2) \
fprintf ((STREAM), "\tALIGN 2\n"); \
else if (amount == 4) \
fprintf ((STREAM), "\tALIGN\n"); \
else \
fprintf ((STREAM), "\tALIGN %d\n", amount); \
} while (0)
} \
while (0)
#undef DBX_DEBUGGING_INFO
gcc/config/arm/aout.h
......@@ -65,7 +65,6 @@
#define LOCAL_LABEL_PREFIX ""
#endif
/* The assembler's names for the registers. */
#ifndef REGISTER_NAMES
#define REGISTER_NAMES \
......@@ -74,9 +73,15 @@
"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
"cc", "sfp", "afp", \
"mv0", "mv1", "mv2", "mv3", "mv4", "mv5", \
"mv6", "mv7", "mv8", "mv9", "mv10", "mv11",\
"mv12", "mv13", "mv14", "mv15" \
"mv0", "mv1", "mv2", "mv3", \
"mv4", "mv5", "mv6", "mv7", \
"mv8", "mv9", "mv10", "mv11", \
"mv12", "mv13", "mv14", "mv15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
"wr0", "wr1", "wr2", "wr3", \
"wr4", "wr5", "wr6", "wr7", \
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15" \
}
#endif
......@@ -235,12 +240,12 @@
#undef ASM_OUTPUT_ASCII
#define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
output_ascii_pseudo_op (STREAM, (const unsigned char *)(PTR), LEN)
output_ascii_pseudo_op (STREAM, (const unsigned char *) (PTR), LEN)
/* Output a gap. In fact we fill it with nulls. */
#undef ASM_OUTPUT_SKIP
#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
fprintf (STREAM, "\t.space\t%d\n", (int)(NBYTES))
fprintf (STREAM, "\t.space\t%d\n", (int) (NBYTES))
/* Align output to a power of two. Horrible /bin/as. */
#ifndef ASM_OUTPUT_ALIGN
......
gcc/config/arm/arm-protos.h
......@@ -135,6 +135,8 @@ extern void arm_final_prescan_insn (rtx);
extern int arm_go_if_legitimate_address (enum machine_mode, rtx);
extern int arm_debugger_arg_offset (int, rtx);
extern int arm_is_longcall_p (rtx, int, int);
extern int arm_emit_vector_const (FILE *, rtx);
extern const char * arm_output_load_gr (rtx *);
#if defined TREE_CODE
extern rtx arm_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
......
gcc/config/arm/arm.md
......@@ -75,6 +75,18 @@
; and stack frame generation. Operand 0 is the
; register to "use".
(UNSPEC_CHECK_ARCH 7); Set CCs to indicate 26-bit or 32-bit mode.
(UNSPEC_WSHUFH 8) ; Used by the instrinsic form of the iWMMXt WSHUFH instruction.
(UNSPEC_WACC 9) ; Used by the instrinsic form of the iWMMXt WACC instruction.
(UNSPEC_TMOVMSK 10) ; Used by the instrinsic form of the iWMMXt TMOVMSK instruction.
(UNSPEC_WSAD 11) ; Used by the instrinsic form of the iWMMXt WSAD instruction.
(UNSPEC_WSADZ 12) ; Used by the instrinsic form of the iWMMXt WSADZ instruction.
(UNSPEC_WMACS 13) ; Used by the instrinsic form of the iWMMXt WMACS instruction.
(UNSPEC_WMACU 14) ; Used by the instrinsic form of the iWMMXt WMACU instruction.
(UNSPEC_WMACSZ 15) ; Used by the instrinsic form of the iWMMXt WMACSZ instruction.
(UNSPEC_WMACUZ 16) ; Used by the instrinsic form of the iWMMXt WMACUZ instruction.
(UNSPEC_CLRDI 17) ; Used by the instrinsic form of the iWMMXt CLRDI instruction.
(UNSPEC_WMADDS 18) ; Used by the instrinsic form of the iWMMXt WMADDS instruction.
(UNSPEC_WMADDU 19) ; Used by the instrinsic form of the iWMMXt WMADDU instruction.
]
)
......@@ -99,6 +111,12 @@
; a 32-bit object.
(VUNSPEC_POOL_8 7) ; `pool-entry(8)'. An entry in the constant pool for
; a 64-bit object.
(VUNSPEC_TMRC 8) ; Used by the iWMMXt TMRC instruction.
(VUNSPEC_TMCR 9) ; Used by the iWMMXt TMCR instruction.
(VUNSPEC_ALIGN8 10) ; 8-byte alignment version of VUNSPEC_ALIGN
(VUNSPEC_WCMP_EQ 11) ; Used by the iWMMXt WCMPEQ instructions
(VUNSPEC_WCMP_GTU 12) ; Used by the iWMMXt WCMPGTU instructions
(VUNSPEC_WCMP_GT 13) ; Used by the iwMMXT WCMPGT instructions
]
)
......@@ -1369,7 +1387,7 @@
(match_operator:DI 6 "logical_binary_operator"
[(match_operand:DI 1 "s_register_operand" "")
(match_operand:DI 2 "s_register_operand" "")]))]
"TARGET_ARM && reload_completed"
"TARGET_ARM && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
[(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
(set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))]
"
......@@ -1446,7 +1464,7 @@
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (match_operand:DI 1 "s_register_operand" "%0,r")
(match_operand:DI 2 "s_register_operand" "r,r")))]
"TARGET_ARM"
"TARGET_ARM && ! TARGET_IWMMXT"
"#"
[(set_attr "length" "8")]
)
......@@ -1800,7 +1818,7 @@
(match_operand:DI 2 "s_register_operand" "0,r")))]
"TARGET_ARM"
"#"
"TARGET_ARM && reload_completed"
"TARGET_ARM && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
[(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2)))
(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))]
"
......@@ -1926,7 +1944,7 @@
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(ior:DI (match_operand:DI 1 "s_register_operand" "%0,r")
(match_operand:DI 2 "s_register_operand" "r,r")))]
"TARGET_ARM"
"TARGET_ARM && ! TARGET_IWMMXT"
"#"
[(set_attr "length" "8")
(set_attr "predicable" "yes")]
......@@ -2048,7 +2066,7 @@
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(xor:DI (match_operand:DI 1 "s_register_operand" "%0,r")
(match_operand:DI 2 "s_register_operand" "r,r")))]
"TARGET_ARM"
"TARGET_ARM && !TARGET_IWMMXT"
"#"
[(set_attr "length" "8")
(set_attr "predicable" "yes")]
......@@ -2390,7 +2408,7 @@
[(set (match_operand:DI 0 "s_register_operand" "")
(ashift:DI (match_operand:DI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"TARGET_ARM && (TARGET_CIRRUS)"
"TARGET_ARM && (TARGET_IWMMXT || TARGET_CIRRUS)"
"
if (! s_register_operand (operands[1], DImode))
operands[1] = copy_to_mode_reg (DImode, operands[1]);
......@@ -3588,7 +3606,7 @@
(define_insn "*arm_movdi"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, o<>")
(match_operand:DI 1 "di_operand" "rIK,mi,r"))]
"TARGET_ARM && !TARGET_CIRRUS"
"TARGET_ARM && !TARGET_CIRRUS && ! TARGET_IWMMXT"
"*
return (output_move_double (operands));
"
......@@ -3687,7 +3705,7 @@
(define_insn "*arm_movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m")
(match_operand:SI 1 "general_operand" "rI,K,mi,r"))]
"TARGET_ARM
"TARGET_ARM && ! TARGET_IWMMXT
&& ( register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
......@@ -4742,6 +4760,28 @@
(set_attr "pool_range" "*,*,*,1020,*,*")]
)
;; Vector Moves
(define_expand "movv2si"
[(set (match_operand:V2SI 0 "nonimmediate_operand" "")
(match_operand:V2SI 1 "general_operand" ""))]
"TARGET_REALLY_IWMMXT"
{
})
(define_expand "movv4hi"
[(set (match_operand:V4HI 0 "nonimmediate_operand" "")
(match_operand:V4HI 1 "general_operand" ""))]
"TARGET_REALLY_IWMMXT"
{
})
(define_expand "movv8qi"
[(set (match_operand:V8QI 0 "nonimmediate_operand" "")
(match_operand:V8QI 1 "general_operand" ""))]
"TARGET_REALLY_IWMMXT"
{
})
;; load- and store-multiple insns
;; The arm can load/store any set of registers, provided that they are in
......@@ -6011,8 +6051,8 @@
)
(define_insn "*call_value_reg"
[(set (match_operand 0 "" "=r,f,v")
(call (mem:SI (match_operand:SI 1 "s_register_operand" "r,r,r"))
[(set (match_operand 0 "" "=ryfv")
(call (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNUM))]
......@@ -6025,8 +6065,8 @@
)
(define_insn "*call_value_mem"
[(set (match_operand 0 "" "=r,f,v")
(call (mem:SI (match_operand:SI 1 "memory_operand" "m,m,m"))
[(set (match_operand 0 "" "=ryfv")
(call (mem:SI (match_operand:SI 1 "memory_operand" "m"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNUM))]
......@@ -6057,8 +6097,8 @@
)
(define_insn "*call_value_symbol"
[(set (match_operand 0 "s_register_operand" "=r,f,v")
(call (mem:SI (match_operand:SI 1 "" "X,X,X"))
[(set (match_operand 0 "s_register_operand" "=ryfv")
(call (mem:SI (match_operand:SI 1 "" "X"))
(match_operand:SI 2 "" "")))
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNUM))]
......@@ -6140,8 +6180,8 @@
)
(define_insn "*sibcall_value_insn"
[(set (match_operand 0 "s_register_operand" "=r,f,v")
(call (mem:SI (match_operand:SI 1 "" "X,X,X"))
[(set (match_operand 0 "s_register_operand" "=ryfv")
(call (mem:SI (match_operand:SI 1 "" "X"))
(match_operand 2 "" "")))
(return)
(use (match_operand 3 "" ""))]
......@@ -6166,6 +6206,7 @@
return output_return_instruction (const_true_rtx, TRUE, FALSE);
}"
[(set_attr "type" "load")
(set_attr "length" "12")
(set_attr "predicable" "yes")]
)
......@@ -6186,6 +6227,7 @@
return output_return_instruction (operands[0], TRUE, FALSE);
}"
[(set_attr "conds" "use")
(set_attr "length" "12")
(set_attr "type" "load")]
)
......@@ -8324,7 +8366,10 @@
(match_dup 0)
(match_operand 4 "" "")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed"
;; Note we have to suppress this split for the iwmmxt because it
;; creates a conditional movsi and the iwmmxt_movsi_insn pattern
;; is not predicable. This sucks.
"TARGET_ARM && reload_completed && ! TARGET_IWMMXT"
[(set (match_dup 5) (match_dup 6))
(cond_exec (match_dup 7)
(set (match_dup 0) (match_dup 4)))]
......@@ -8352,7 +8397,10 @@
(match_operand 4 "" "")
(match_dup 0)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed"
;; Note we have to suppress this split for the iwmmxt because it
;; creates a conditional movsi and the iwmmxt_movsi_insn pattern
;; is not predicable. This sucks.
"TARGET_ARM && reload_completed && ! TARGET_IWMMXT"
[(set (match_dup 5) (match_dup 6))
(cond_exec (match_op_dup 1 [(match_dup 5) (const_int 0)])
(set (match_dup 0) (match_dup 4)))]
......@@ -8373,7 +8421,10 @@
(match_operand 4 "" "")
(match_operand 5 "" "")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed"
;; Note we have to suppress this split for the iwmmxt because it
;; creates a conditional movsi and the iwmmxt_movsi_insn pattern
;; is not predicable. This sucks.
"TARGET_ARM && reload_completed && ! TARGET_IWMMXT"
[(set (match_dup 6) (match_dup 7))
(cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
(set (match_dup 0) (match_dup 4)))
......@@ -8405,7 +8456,10 @@
(not:SI
(match_operand:SI 5 "s_register_operand" ""))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && reload_completed"
;; Note we have to suppress this split for the iwmmxt because it
;; creates a conditional movsi and the iwmmxt_movsi_insn pattern
;; is not predicable. This sucks.
"TARGET_ARM && reload_completed && ! TARGET_IWMMXT"
[(set (match_dup 6) (match_dup 7))
(cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
(set (match_dup 0) (match_dup 4)))
......@@ -8559,6 +8613,15 @@
"
)
(define_insn "align_8"
[(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN8)]
"TARGET_REALLY_IWMMXT"
"*
assemble_align (64);
return \"\";
"
)
(define_insn "consttable_end"
[(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
"TARGET_EITHER"
......@@ -8745,3 +8808,5 @@
(include "fpa.md")
;; Load the Maverick co-processor patterns
(include "cirrus.md")
;; Load the Intel Wireless Multimedia Extension patterns
(include "iwmmxt.md")
gcc/config/arm/lib1funcs.asm
......@@ -158,11 +158,12 @@ divisor .req r1
overdone .req r2
result .req r2
curbit .req r3
#if 0
ip .req r12
sp .req r13
lr .req r14
pc .req r15
#endif
/* ------------------------------------------------------------------------ */
/* Bodies of the divsion and modulo routines. */
/* ------------------------------------------------------------------------ */
......
gcc/config/arm/t-xscale-elf
......@@ -37,6 +37,10 @@ MULTILIB_EXCEPTIONS += *mhard-float/*mthumb*
MULTILIB_REDUNDANT_DIRS = interwork/thumb=thumb
MULTILIB_OPTIONS += mcpu=iwmmxt
MULTILIB_DIRNAMES += iwmmxt
MULTILIB_REDUNDANT_DIRS += interwork/thumb/iwmmxt=thumb
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
LIBGCC = stmp-multilib
......
gcc/doc/invoke.texi
......@@ -6338,7 +6338,7 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250},
@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
@samp{arm920t}, @samp{arm940t}, @samp{arm9tdmi}, @samp{arm10tdmi},
@samp{arm1020t}, @samp{xscale}, @samp{ep9312}.
@samp{arm1020t}, @samp{xscale}, @samp{iwmmxt}, @samp{ep9312}.
@itemx -mtune=@var{name}
@opindex mtune
......@@ -6358,7 +6358,7 @@ name to determine what kind of instructions it can emit when generating
assembly code. This option can be used in conjunction with or instead
of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{ep9312}.
@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{iwmmxt}, @samp{ep9312}.
@item -mfpe=@var{number}
@itemx -mfp=@var{number}
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment