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riscv-gcc-1
Commit 59a2f0fa by Alan Lawrence Committed by Alan Lawrence
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[MIPS] Migrate reduction optabs in mips-ps-3d.md 

	* config/mips/mips-ps-3d.md (reduc_splus_v2sf): Remove.
	(reduc_plus_scal_v2sf): New.
	(reduc_smax_v2sf): Rename to...
	(reduc_smax_scal_v2sf): ...here, make result SFmode, add vec_extract.
	(reduc_smin_v2sf): Rename to...
	(reduc_smin_scal_v2sf): ...here, make result SFmode, add vec_extract.

From-SVN: r232371
parent a7ccb9e7
Showing with 31 additions and 12 deletions
gcc/ChangeLog
2016-01-14 Alan Lawrence <alan.lawrence@arm.com>
* config/mips/mips-ps-3d.md (reduc_splus_v2sf): Remove.
(reduc_plus_scal_v2sf): New.
(reduc_smax_v2sf): Rename to...
(reduc_smax_scal_v2sf): ...here, make result SFmode, add vec_extract.
(reduc_smin_v2sf): Rename to...
(reduc_smin_scal_v2sf): ...here, make result SFmode, add vec_extract.
2016-01-14 Jan Hubicka <hubicka@ucw.cz> 2016-01-14 Jan Hubicka <hubicka@ucw.cz>
* alias.c (compare_base_symbol_refs): New function. * alias.c (compare_base_symbol_refs): New function.
......
gcc/config/mips/mips-ps-3d.md
...@@ -371,13 +371,17 @@ ...@@ -371,13 +371,17 @@
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "reduc_splus_v2sf" (define_expand "reduc_plus_scal_v2sf"
[(set (match_operand:V2SF 0 "register_operand" "=f") [(match_operand:SF 0 "register_operand" "=f")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") (match_operand:V2SF 1 "register_operand" "f")]
(match_dup 1)]
UNSPEC_ADDR_PS))]
"TARGET_HARD_FLOAT && TARGET_MIPS3D" "TARGET_HARD_FLOAT && TARGET_MIPS3D"
"") {
rtx temp = gen_reg_rtx (V2SFmode);
emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1]));
rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx;
emit_insn (gen_vec_extractv2sf (operands[0], temp, lane));
DONE;
})
; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word
(define_insn "mips_cvt_pw_ps" (define_insn "mips_cvt_pw_ps"
...@@ -745,20 +749,26 @@ ...@@ -745,20 +749,26 @@
DONE; DONE;
}) })
(define_expand "reduc_smin_v2sf" (define_expand "reduc_smin_scal_v2sf"
[(match_operand:V2SF 0 "register_operand") [(match_operand:SF 0 "register_operand")
(match_operand:V2SF 1 "register_operand")] (match_operand:V2SF 1 "register_operand")]
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{ {
mips_expand_vec_reduc (operands[0], operands[1], gen_sminv2sf3); rtx temp = gen_reg_rtx (V2SFmode);
mips_expand_vec_reduc (temp, operands[1], gen_sminv2sf3);
rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx;
emit_insn (gen_vec_extractv2sf (operands[0], temp, lane));
DONE; DONE;
}) })
(define_expand "reduc_smax_v2sf" (define_expand "reduc_smax_scal_v2sf"
[(match_operand:V2SF 0 "register_operand") [(match_operand:SF 0 "register_operand")
(match_operand:V2SF 1 "register_operand")] (match_operand:V2SF 1 "register_operand")]
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{ {
mips_expand_vec_reduc (operands[0], operands[1], gen_smaxv2sf3); rtx temp = gen_reg_rtx (V2SFmode);
mips_expand_vec_reduc (temp, operands[1], gen_smaxv2sf3);
rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx;
emit_insn (gen_vec_extractv2sf (operands[0], temp, lane));
DONE; DONE;
}) })
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