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riscv-gcc-1
Commit 58ebda9c by Kazu Hirata Committed by Kazu Hirata
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re PR target/13380 (An unrecognized insn.) 

	PR target/13380.
	* config/m32r/m32r.md: Replace (reg:SI 17) with (reg:CC 17)
	or (ne:SI (reg:CC 17) (const_int 0)).
	Be specific about modes wherever possible.

From-SVN: r75586
parent 81ad38a6
Showing with 103 additions and 96 deletions
gcc/ChangeLog
2004-01-09 Kazu Hirata <kazu@cs.umass.edu> 2004-01-09 Kazu Hirata <kazu@cs.umass.edu>
PR target/13380.
* config/m32r/m32r.md: Replace (reg:SI 17) with (reg:CC 17)
or (ne:SI (reg:CC 17) (const_int 0)).
Be specific about modes wherever possible.
2004-01-09 Kazu Hirata <kazu@cs.umass.edu>
* config/m32r/m32r.c (m32r_expand_block_move): Call * config/m32r/m32r.c (m32r_expand_block_move): Call
gen_movestrsi_internal with two more arguments. gen_movestrsi_internal with two more arguments.
(m32r_output_block_move): Adjust operand numbers. (m32r_output_block_move): Adjust operand numbers.
......
gcc/config/m32r/m32r.md
...@@ -579,7 +579,7 @@ ...@@ -579,7 +579,7 @@
(define_insn "*load_sda_base" (define_insn "*load_sda_base"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(unspec [(const_int 0)] 2))] (unspec:SI [(const_int 0)] 2))]
"" ""
"ld24 %0,#_SDA_BASE_" "ld24 %0,#_SDA_BASE_"
[(set_attr "type" "int4") [(set_attr "type" "int4")
...@@ -900,7 +900,7 @@ ...@@ -900,7 +900,7 @@
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "%0") (plus:DI (match_operand:DI 1 "register_operand" "%0")
(match_operand:DI 2 "register_operand" "r"))) (match_operand:DI 2 "register_operand" "r")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -911,23 +911,23 @@ ...@@ -911,23 +911,23 @@
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" ""))) (match_operand:DI 2 "register_operand" "")))
(clobber (match_operand 3 "" ""))] (clobber (reg:CC 17))]
"reload_completed" "reload_completed"
[(parallel [(set (match_dup 3) [(parallel [(set (reg:CC 17)
(const_int 0)) (const_int 0))
(use (match_dup 4))]) (use (match_dup 4))])
(parallel [(set (match_dup 4) (parallel [(set (match_dup 4)
(plus:SI (match_dup 4) (plus:SI (match_dup 4)
(plus:SI (match_dup 5) (plus:SI (match_dup 5)
(match_dup 3)))) (ne:SI (reg:CC 17) (const_int 0)))))
(set (match_dup 3) (set (reg:CC 17)
(unspec [(const_int 0)] 3))]) (unspec:CC [(const_int 0)] 3))])
(parallel [(set (match_dup 6) (parallel [(set (match_dup 6)
(plus:SI (match_dup 6) (plus:SI (match_dup 6)
(plus:SI (match_dup 7) (plus:SI (match_dup 7)
(match_dup 3)))) (ne:SI (reg:CC 17) (const_int 0)))))
(set (match_dup 3) (set (reg:CC 17)
(unspec [(const_int 0)] 3))])] (unspec:CC [(const_int 0)] 3))])]
" "
{ {
operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode); operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
...@@ -937,7 +937,7 @@ ...@@ -937,7 +937,7 @@
}") }")
(define_insn "*clear_c" (define_insn "*clear_c"
[(set (reg:SI 17) [(set (reg:CC 17)
(const_int 0)) (const_int 0))
(use (match_operand:SI 0 "register_operand" "r"))] (use (match_operand:SI 0 "register_operand" "r"))]
"" ""
...@@ -949,9 +949,9 @@ ...@@ -949,9 +949,9 @@
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_operand:SI 1 "register_operand" "%0") (plus:SI (match_operand:SI 1 "register_operand" "%0")
(plus:SI (match_operand:SI 2 "register_operand" "r") (plus:SI (match_operand:SI 2 "register_operand" "r")
(reg:SI 17)))) (ne:SI (reg:CC 17) (const_int 0)))))
(set (reg:SI 17) (set (reg:CC 17)
(unspec [(const_int 0)] 3))] (unspec:CC [(const_int 0)] 3))]
"" ""
"addx %0,%2" "addx %0,%2"
[(set_attr "type" "int2") [(set_attr "type" "int2")
...@@ -970,7 +970,7 @@ ...@@ -970,7 +970,7 @@
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (match_operand:DI 1 "register_operand" "0") (minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "register_operand" "r"))) (match_operand:DI 2 "register_operand" "r")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -981,23 +981,23 @@ ...@@ -981,23 +981,23 @@
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "") (minus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" ""))) (match_operand:DI 2 "register_operand" "")))
(clobber (match_operand 3 "" ""))] (clobber (reg:CC 17))]
"reload_completed" "reload_completed"
[(parallel [(set (match_dup 3) [(parallel [(set (reg:CC 17)
(const_int 0)) (const_int 0))
(use (match_dup 4))]) (use (match_dup 4))])
(parallel [(set (match_dup 4) (parallel [(set (match_dup 4)
(minus:SI (match_dup 4) (minus:SI (match_dup 4)
(minus:SI (match_dup 5) (minus:SI (match_dup 5)
(match_dup 3)))) (ne:SI (reg:CC 17) (const_int 0)))))
(set (match_dup 3) (set (reg:CC 17)
(unspec [(const_int 0)] 3))]) (unspec:CC [(const_int 0)] 3))])
(parallel [(set (match_dup 6) (parallel [(set (match_dup 6)
(minus:SI (match_dup 6) (minus:SI (match_dup 6)
(minus:SI (match_dup 7) (minus:SI (match_dup 7)
(match_dup 3)))) (ne:SI (reg:CC 17) (const_int 0)))))
(set (match_dup 3) (set (reg:CC 17)
(unspec [(const_int 0)] 3))])] (unspec:CC [(const_int 0)] 3))])]
" "
{ {
operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode); operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
...@@ -1010,9 +1010,9 @@ ...@@ -1010,9 +1010,9 @@
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "register_operand" "%0") (minus:SI (match_operand:SI 1 "register_operand" "%0")
(minus:SI (match_operand:SI 2 "register_operand" "r") (minus:SI (match_operand:SI 2 "register_operand" "r")
(reg:SI 17)))) (ne:SI (reg:CC 17) (const_int 0)))))
(set (reg:SI 17) (set (reg:CC 17)
(unspec [(const_int 0)] 3))] (unspec:CC [(const_int 0)] 3))]
"" ""
"subx %0,%2" "subx %0,%2"
[(set_attr "type" "int2") [(set_attr "type" "int2")
...@@ -1241,7 +1241,7 @@ ...@@ -1241,7 +1241,7 @@
;; preferred. ;; preferred.
(define_expand "cmpsi" (define_expand "cmpsi"
[(set (reg:SI 17) [(set (reg:CC 17)
(compare:CC (match_operand:SI 0 "register_operand" "") (compare:CC (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "reg_or_cmp_int16_operand" "")))] (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
"" ""
...@@ -1253,8 +1253,8 @@ ...@@ -1253,8 +1253,8 @@
}") }")
(define_insn "cmp_eqsi_zero_insn" (define_insn "cmp_eqsi_zero_insn"
[(set (reg:SI 17) [(set (reg:CC 17)
(eq:SI (match_operand:SI 0 "register_operand" "r,r") (eq:CC (match_operand:SI 0 "register_operand" "r,r")
(match_operand:SI 1 "reg_or_zero_operand" "r,P")))] (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
"TARGET_M32RX || TARGET_M32R2" "TARGET_M32RX || TARGET_M32R2"
"@ "@
...@@ -1268,8 +1268,8 @@ ...@@ -1268,8 +1268,8 @@
;; is quite inefficient. However, it is rarely used. ;; is quite inefficient. However, it is rarely used.
(define_insn "cmp_eqsi_insn" (define_insn "cmp_eqsi_insn"
[(set (reg:SI 17) [(set (reg:CC 17)
(eq:SI (match_operand:SI 0 "register_operand" "r,r") (eq:CC (match_operand:SI 0 "register_operand" "r,r")
(match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P"))) (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
(clobber (match_scratch:SI 2 "=&r,&r"))] (clobber (match_scratch:SI 2 "=&r,&r"))]
"" ""
...@@ -1293,8 +1293,8 @@ ...@@ -1293,8 +1293,8 @@
(set_attr "length" "8,8")]) (set_attr "length" "8,8")])
(define_insn "cmp_ltsi_insn" (define_insn "cmp_ltsi_insn"
[(set (reg:SI 17) [(set (reg:CC 17)
(lt:SI (match_operand:SI 0 "register_operand" "r,r") (lt:CC (match_operand:SI 0 "register_operand" "r,r")
(match_operand:SI 1 "reg_or_int16_operand" "r,J")))] (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
"" ""
"@ "@
...@@ -1304,8 +1304,8 @@ ...@@ -1304,8 +1304,8 @@
(set_attr "length" "2,4")]) (set_attr "length" "2,4")])
(define_insn "cmp_ltusi_insn" (define_insn "cmp_ltusi_insn"
[(set (reg:SI 17) [(set (reg:CC 17)
(ltu:SI (match_operand:SI 0 "register_operand" "r,r") (ltu:CC (match_operand:SI 0 "register_operand" "r,r")
(match_operand:SI 1 "reg_or_int16_operand" "r,J")))] (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
"" ""
"@ "@
...@@ -1696,7 +1696,7 @@ ...@@ -1696,7 +1696,7 @@
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (match_operand:SI 1 "register_operand" "%r") (eq:SI (match_operand:SI 1 "register_operand" "%r")
(match_operand:SI 2 "reg_or_zero_operand" "rP"))) (match_operand:SI 2 "reg_or_zero_operand" "rP")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"TARGET_M32RX || TARGET_M32R2" "TARGET_M32RX || TARGET_M32R2"
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -1706,20 +1706,20 @@ ...@@ -1706,20 +1706,20 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(eq:SI (match_operand:SI 1 "register_operand" "") (eq:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_zero_operand" ""))) (match_operand:SI 2 "reg_or_zero_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"TARGET_M32RX || TARGET_M32R2" "TARGET_M32RX || TARGET_M32R2"
[(set (reg:SI 17) [(set (reg:CC 17)
(eq:SI (match_dup 1) (eq:CC (match_dup 1)
(match_dup 2))) (match_dup 2)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17))] (ne:SI (reg:CC 17) (const_int 0)))]
"") "")
(define_insn "seq_zero_insn" (define_insn "seq_zero_insn"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (match_operand:SI 1 "register_operand" "r") (eq:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0))) (const_int 0)))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"TARGET_M32R" "TARGET_M32R"
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -1729,7 +1729,7 @@ ...@@ -1729,7 +1729,7 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(eq:SI (match_operand:SI 1 "register_operand" "") (eq:SI (match_operand:SI 1 "register_operand" "")
(const_int 0))) (const_int 0)))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"TARGET_M32R" "TARGET_M32R"
[(match_dup 3)] [(match_dup 3)]
" "
...@@ -1748,7 +1748,7 @@ ...@@ -1748,7 +1748,7 @@
[(set (match_operand:SI 0 "register_operand" "=r,r,??r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r") (eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK"))) (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
(clobber (reg:SI 17)) (clobber (reg:CC 17))
(clobber (match_scratch:SI 3 "=1,2,&r,r"))] (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
"TARGET_M32R" "TARGET_M32R"
"#" "#"
...@@ -1759,7 +1759,7 @@ ...@@ -1759,7 +1759,7 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(eq:SI (match_operand:SI 1 "register_operand" "") (eq:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_eq_int16_operand" ""))) (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
(clobber (reg:SI 17)) (clobber (reg:CC 17))
(clobber (match_scratch:SI 3 ""))] (clobber (match_scratch:SI 3 ""))]
"TARGET_M32R && reload_completed" "TARGET_M32R && reload_completed"
[(match_dup 4)] [(match_dup 4)]
...@@ -1837,7 +1837,7 @@ ...@@ -1837,7 +1837,7 @@
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(ne:SI (match_operand:SI 1 "register_operand" "r") (ne:SI (match_operand:SI 1 "register_operand" "r")
(const_int 0))) (const_int 0)))
(clobber (reg:SI 17)) (clobber (reg:CC 17))
(clobber (match_scratch:SI 2 "=&r"))] (clobber (match_scratch:SI 2 "=&r"))]
"" ""
"#" "#"
...@@ -1848,16 +1848,16 @@ ...@@ -1848,16 +1848,16 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(ne:SI (match_operand:SI 1 "register_operand" "") (ne:SI (match_operand:SI 1 "register_operand" "")
(const_int 0))) (const_int 0)))
(clobber (reg:SI 17)) (clobber (reg:CC 17))
(clobber (match_scratch:SI 2 ""))] (clobber (match_scratch:SI 2 ""))]
"reload_completed" "reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(const_int 0)) (const_int 0))
(set (reg:SI 17) (set (reg:CC 17)
(ltu:SI (match_dup 2) (ltu:CC (match_dup 2)
(match_dup 1))) (match_dup 1)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17))] (ne:SI (reg:CC 17) (const_int 0)))]
"") "")
(define_expand "slt" (define_expand "slt"
...@@ -1887,7 +1887,7 @@ ...@@ -1887,7 +1887,7 @@
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(lt:SI (match_operand:SI 1 "register_operand" "r,r") (lt:SI (match_operand:SI 1 "register_operand" "r,r")
(match_operand:SI 2 "reg_or_int16_operand" "r,J"))) (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -1897,13 +1897,13 @@ ...@@ -1897,13 +1897,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(lt:SI (match_operand:SI 1 "register_operand" "") (lt:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_int16_operand" ""))) (match_operand:SI 2 "reg_or_int16_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
[(set (reg:SI 17) [(set (reg:CC 17)
(lt:SI (match_dup 1) (lt:CC (match_dup 1)
(match_dup 2))) (match_dup 2)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17))] (ne:SI (reg:CC 17) (const_int 0)))]
"") "")
(define_expand "sle" (define_expand "sle"
...@@ -1950,7 +1950,7 @@ ...@@ -1950,7 +1950,7 @@
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(le:SI (match_operand:SI 1 "register_operand" "r") (le:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r"))) (match_operand:SI 2 "register_operand" "r")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -1960,13 +1960,13 @@ ...@@ -1960,13 +1960,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(le:SI (match_operand:SI 1 "register_operand" "") (le:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" ""))) (match_operand:SI 2 "register_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"!optimize_size" "!optimize_size"
[(set (reg:SI 17) [(set (reg:CC 17)
(lt:SI (match_dup 2) (lt:CC (match_dup 2)
(match_dup 1))) (match_dup 1)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17)) (ne:SI (reg:CC 17) (const_int 0)))
(set (match_dup 0) (set (match_dup 0)
(xor:SI (match_dup 0) (xor:SI (match_dup 0)
(const_int 1)))] (const_int 1)))]
...@@ -1978,13 +1978,13 @@ ...@@ -1978,13 +1978,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(le:SI (match_operand:SI 1 "register_operand" "") (le:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" ""))) (match_operand:SI 2 "register_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"optimize_size" "optimize_size"
[(set (reg:SI 17) [(set (reg:CC 17)
(lt:SI (match_dup 2) (lt:CC (match_dup 2)
(match_dup 1))) (match_dup 1)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17)) (ne:SI (reg:CC 17) (const_int 0)))
(set (match_dup 0) (set (match_dup 0)
(plus:SI (match_dup 0) (plus:SI (match_dup 0)
(const_int -1))) (const_int -1)))
...@@ -2042,7 +2042,7 @@ ...@@ -2042,7 +2042,7 @@
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(ge:SI (match_operand:SI 1 "register_operand" "r,r") (ge:SI (match_operand:SI 1 "register_operand" "r,r")
(match_operand:SI 2 "reg_or_int16_operand" "r,J"))) (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -2052,13 +2052,13 @@ ...@@ -2052,13 +2052,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(ge:SI (match_operand:SI 1 "register_operand" "") (ge:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_int16_operand" ""))) (match_operand:SI 2 "reg_or_int16_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"!optimize_size" "!optimize_size"
[(set (reg:SI 17) [(set (reg:CC 17)
(lt:SI (match_dup 1) (lt:CC (match_dup 1)
(match_dup 2))) (match_dup 2)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17)) (ne:SI (reg:CC 17) (const_int 0)))
(set (match_dup 0) (set (match_dup 0)
(xor:SI (match_dup 0) (xor:SI (match_dup 0)
(const_int 1)))] (const_int 1)))]
...@@ -2070,13 +2070,13 @@ ...@@ -2070,13 +2070,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(ge:SI (match_operand:SI 1 "register_operand" "") (ge:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_int16_operand" ""))) (match_operand:SI 2 "reg_or_int16_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"optimize_size" "optimize_size"
[(set (reg:SI 17) [(set (reg:CC 17)
(lt:SI (match_dup 1) (lt:CC (match_dup 1)
(match_dup 2))) (match_dup 2)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17)) (ne:SI (reg:CC 17) (const_int 0)))
(set (match_dup 0) (set (match_dup 0)
(plus:SI (match_dup 0) (plus:SI (match_dup 0)
(const_int -1))) (const_int -1)))
...@@ -2111,7 +2111,7 @@ ...@@ -2111,7 +2111,7 @@
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(ltu:SI (match_operand:SI 1 "register_operand" "r,r") (ltu:SI (match_operand:SI 1 "register_operand" "r,r")
(match_operand:SI 2 "reg_or_int16_operand" "r,J"))) (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -2121,13 +2121,13 @@ ...@@ -2121,13 +2121,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(ltu:SI (match_operand:SI 1 "register_operand" "") (ltu:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_int16_operand" ""))) (match_operand:SI 2 "reg_or_int16_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
[(set (reg:SI 17) [(set (reg:CC 17)
(ltu:SI (match_dup 1) (ltu:CC (match_dup 1)
(match_dup 2))) (match_dup 2)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17))] (ne:SI (reg:CC 17) (const_int 0)))]
"") "")
(define_expand "sleu" (define_expand "sleu"
...@@ -2171,7 +2171,7 @@ ...@@ -2171,7 +2171,7 @@
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(leu:SI (match_operand:SI 1 "register_operand" "r") (leu:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r"))) (match_operand:SI 2 "register_operand" "r")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -2181,13 +2181,13 @@ ...@@ -2181,13 +2181,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(leu:SI (match_operand:SI 1 "register_operand" "") (leu:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" ""))) (match_operand:SI 2 "register_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"!optimize_size" "!optimize_size"
[(set (reg:SI 17) [(set (reg:CC 17)
(ltu:SI (match_dup 2) (ltu:CC (match_dup 2)
(match_dup 1))) (match_dup 1)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17)) (ne:SI (reg:CC 17) (const_int 0)))
(set (match_dup 0) (set (match_dup 0)
(xor:SI (match_dup 0) (xor:SI (match_dup 0)
(const_int 1)))] (const_int 1)))]
...@@ -2199,13 +2199,13 @@ ...@@ -2199,13 +2199,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(leu:SI (match_operand:SI 1 "register_operand" "") (leu:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" ""))) (match_operand:SI 2 "register_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"optimize_size" "optimize_size"
[(set (reg:SI 17) [(set (reg:CC 17)
(ltu:SI (match_dup 2) (ltu:CC (match_dup 2)
(match_dup 1))) (match_dup 1)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17)) (ne:SI (reg:CC 17) (const_int 0)))
(set (match_dup 0) (set (match_dup 0)
(plus:SI (match_dup 0) (plus:SI (match_dup 0)
(const_int -1))) (const_int -1)))
...@@ -2263,7 +2263,7 @@ ...@@ -2263,7 +2263,7 @@
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(geu:SI (match_operand:SI 1 "register_operand" "r,r") (geu:SI (match_operand:SI 1 "register_operand" "r,r")
(match_operand:SI 2 "reg_or_int16_operand" "r,J"))) (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"" ""
"#" "#"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -2273,13 +2273,13 @@ ...@@ -2273,13 +2273,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(geu:SI (match_operand:SI 1 "register_operand" "") (geu:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_int16_operand" ""))) (match_operand:SI 2 "reg_or_int16_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"!optimize_size" "!optimize_size"
[(set (reg:SI 17) [(set (reg:CC 17)
(ltu:SI (match_dup 1) (ltu:CC (match_dup 1)
(match_dup 2))) (match_dup 2)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17)) (ne:SI (reg:CC 17) (const_int 0)))
(set (match_dup 0) (set (match_dup 0)
(xor:SI (match_dup 0) (xor:SI (match_dup 0)
(const_int 1)))] (const_int 1)))]
...@@ -2291,13 +2291,13 @@ ...@@ -2291,13 +2291,13 @@
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(geu:SI (match_operand:SI 1 "register_operand" "") (geu:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_int16_operand" ""))) (match_operand:SI 2 "reg_or_int16_operand" "")))
(clobber (reg:SI 17))] (clobber (reg:CC 17))]
"optimize_size" "optimize_size"
[(set (reg:SI 17) [(set (reg:CC 17)
(ltu:SI (match_dup 1) (ltu:CC (match_dup 1)
(match_dup 2))) (match_dup 2)))
(set (match_dup 0) (set (match_dup 0)
(reg:SI 17)) (ne:SI (reg:CC 17) (const_int 0)))
(set (match_dup 0) (set (match_dup 0)
(plus:SI (match_dup 0) (plus:SI (match_dup 0)
(const_int -1))) (const_int -1)))
...@@ -2307,7 +2307,7 @@ ...@@ -2307,7 +2307,7 @@
(define_insn "movcc_insn" (define_insn "movcc_insn"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(reg:SI 17))] (ne:SI (reg:CC 17) (const_int 0)))]
"" ""
"mvfc %0, cbr" "mvfc %0, cbr"
[(set_attr "type" "misc") [(set_attr "type" "misc")
......
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