arm.md (*addsi3_compare0_scratch): New insn.
* arm.md (*addsi3_compare0_scratch): New insn.
(*movsi_compare0, *cmpsi_insn, *cmpsi_shiftsi): Make sure the
compare has mode CC.
(cmp{si,sf,df,xf} expands): Just provide sufficient information
to allow the parameters to be matched properly.
(*cmpsi_negsi): Delete (of dubious validity).
(*cmpsi_shiftsi_swp): New pattern.
(*condbranch_reversed): No longer needs to check REVERSIBLE_CC_MODE.
(mov{si,sf,df}cc, *mov{si,sf,df}{,_hard,_soft}_insn): The mode of the
IF_THEN_ELSE must be appropriate to the target (not void).
(*and_scc): Match cc_register, not reversible_cc_register.
(*ior_compare_compare): Delete.
(split for ior_compare_compare + condjump): Delete.
(*impossible_cond_compare): Delete.
(*condition_compare_ior): Delete.
(*cond_move): Mode for the IF_THEN_ELSE must be SImode.
(*and_scc_scc): Delete.
(split for and_scc_scc + condjump): Delete.
(*impossible_cond_branch_and): Delete.
(*cmp_ite0, *cmp_ite1): New patterns.
(if_compare_not): Should be an anonymous pattern.
(Peephole for move and compare): Compare mode must be mode CCmode.
(Split pattern for comparing shifted reg then branch): Delete.
(*loadqi_compare): Delete, replaced with a split pattern to do
the same thing.
(*cond_move_not): Match cc_register, not reversible_cc_register.
(load/store multiple peepholes): Rewrite using the above
functions.
(all patterns taking immediate_operand): If the code later assumes
this is a CONST_INT, then match const_int_operand instead.
From-SVN: r11352
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