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riscv-gcc-1
Commit 56e25830 by Oleg Endo
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sh.md: Group and sort shift related patterns. 

	* config/sh/sh.md: Group and sort shift related patterns.
	(ashlsi3_n, *ashlhi3_n, lshrsi3_n): Remove length attributes.

From-SVN: r189730
parent c21a1dbb
Showing with 281 additions and 299 deletions
gcc/ChangeLog
2012-07-20 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.md: Group and sort shift related patterns.
(ashlsi3_n, *ashlhi3_n, lshrsi3_n): Remove length attributes.
2012-07-20 Hans-Peter Nilsson <hp@axis.com> 2012-07-20 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.c (cris_asm_output_ident): Remove unused * config/cris/cris.c (cris_asm_output_ident): Remove unused
......
gcc/config/sh/sh.md
...@@ -3496,12 +3496,35 @@ label: ...@@ -3496,12 +3496,35 @@ label:
FAIL; FAIL;
}) })
;; ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
;; shift left ;; SImode shift left
(define_expand "ashlsi3"
[(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "nonmemory_operand" "")))
(clobber (reg:SI T_REG))])]
""
{
if (TARGET_SHMEDIA)
{
emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
DONE;
}
if (CONST_INT_P (operands[2])
&& sh_dynamicalize_shift_p (operands[2]))
operands[2] = force_reg (SImode, operands[2]);
if (TARGET_SH3 || TARGET_SH2A)
{
emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
DONE;
}
if (! immediate_operand (operands[2], GET_MODE (operands[2])))
FAIL;
})
;; This pattern is used by init_expmed for computing the costs of shift ;; This pattern is used by init_expmed for computing the costs of shift
;; insns. ;; insns.
(define_insn_and_split "ashlsi3_std" (define_insn_and_split "ashlsi3_std"
[(set (match_operand:SI 0 "arith_reg_dest" "=r,r,r,r") [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,r,r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0") (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
...@@ -3528,16 +3551,6 @@ label: ...@@ -3528,16 +3551,6 @@ label:
[(set_attr "length" "*,*,*,4") [(set_attr "length" "*,*,*,4")
(set_attr "type" "dyn_shift,arith,arith,arith")]) (set_attr "type" "dyn_shift,arith,arith,arith")])
(define_insn "ashlhi3_k"
[(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
(match_operand:HI 2 "const_int_operand" "M,P27")))]
"TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
"@
add %0,%0
shll%O2 %0"
[(set_attr "type" "arith")])
(define_insn_and_split "ashlsi3_n" (define_insn_and_split "ashlsi3_n"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
...@@ -3550,16 +3563,37 @@ label: ...@@ -3550,16 +3563,37 @@ label:
{ {
gen_shifty_op (ASHIFT, operands); gen_shifty_op (ASHIFT, operands);
DONE; DONE;
} })
[(set (attr "length")
(cond [(match_test "shift_insns_rtx (insn)") (define_insn "ashlsi_c"
(const_string "2") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2)) (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
(const_string "4") (set (reg:SI T_REG)
(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3)) (lt:SI (match_dup 1) (const_int 0)))]
(const_string "6")] "TARGET_SH1"
(const_string "8"))) "shll %0"
(set_attr "type" "arith")]) [(set_attr "type" "arith")])
(define_insn "*ashlsi_c_void"
[(set (reg:SI T_REG)
(lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
(clobber (match_scratch:SI 1 "=0"))]
"TARGET_SH1 && cse_not_expected"
"shll %0"
[(set_attr "type" "arith")])
(define_peephole2
[(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
(set (reg:SI T_REG)
(gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
"TARGET_SH1
&& peep2_reg_dead_p (2, operands[0])
&& peep2_reg_dead_p (2, operands[1])"
[(const_int 0)]
{
emit_insn (gen_ashlsi_c (operands[1], operands[1]));
DONE;
})
(define_insn "ashlsi3_media" (define_insn "ashlsi3_media"
[(set (match_operand:SI 0 "arith_reg_dest" "=r,r") [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
...@@ -3572,29 +3606,8 @@ label: ...@@ -3572,29 +3606,8 @@ label:
[(set_attr "type" "arith_media") [(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")]) (set_attr "highpart" "ignore")])
(define_expand "ashlsi3" ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
[(parallel [(set (match_operand:SI 0 "arith_reg_operand" "") ;; HImode shift left
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "nonmemory_operand" "")))
(clobber (reg:SI T_REG))])]
""
{
if (TARGET_SHMEDIA)
{
emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
DONE;
}
if (CONST_INT_P (operands[2])
&& sh_dynamicalize_shift_p (operands[2]))
operands[2] = force_reg (SImode, operands[2]);
if (TARGET_SH3 || TARGET_SH2A)
{
emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
DONE;
}
if (! immediate_operand (operands[2], GET_MODE (operands[2])))
FAIL;
})
(define_expand "ashlhi3" (define_expand "ashlhi3"
[(parallel [(set (match_operand:HI 0 "arith_reg_operand" "") [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
...@@ -3611,6 +3624,16 @@ label: ...@@ -3611,6 +3624,16 @@ label:
operands[1] = copy_to_mode_reg (HImode, operands[1]); operands[1] = copy_to_mode_reg (HImode, operands[1]);
}) })
(define_insn "ashlhi3_k"
[(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
(match_operand:HI 2 "const_int_operand" "M,P27")))]
"TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
"@
add %0,%0
shll%O2 %0"
[(set_attr "type" "arith")])
(define_insn_and_split "*ashlhi3_n" (define_insn_and_split "*ashlhi3_n"
[(set (match_operand:HI 0 "arith_reg_dest" "=r") [(set (match_operand:HI 0 "arith_reg_dest" "=r")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0") (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
...@@ -3623,18 +3646,115 @@ label: ...@@ -3623,18 +3646,115 @@ label:
{ {
gen_shifty_hi_op (ASHIFT, operands); gen_shifty_hi_op (ASHIFT, operands);
DONE; DONE;
} })
[(set (attr "length")
(cond [(match_test "shift_insns_rtx (insn)") ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(const_string "2") ;; DImode shift left
(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
(const_string "4")] (define_expand "ashldi3"
(const_string "6"))) [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:SI T_REG))])]
""
{
if (TARGET_SHMEDIA)
{
emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
DONE;
}
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
{
emit_insn (gen_ashldi3_k (operands[0], operands[1]));
DONE;
}
else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
{
emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
DONE;
}
else
FAIL;
})
;; Expander for DImode shift left with SImode operations.
(define_expand "ashldi3_std"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")))]
"TARGET_SH1 && INTVAL (operands[2]) < 32"
{
rtx low_src = gen_lowpart (SImode, operands[1]);
rtx high_src = gen_highpart (SImode, operands[1]);
rtx dst = gen_reg_rtx (DImode);
rtx low_dst = gen_lowpart (SImode, dst);
rtx high_dst = gen_highpart (SImode, dst);
rtx tmp0 = gen_reg_rtx (SImode);
rtx tmp1 = gen_reg_rtx (SImode);
emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
emit_move_insn (operands[0], dst);
DONE;
})
;; This should be an define_insn_and_split.
(define_insn "ashldi3_k"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
(const_int 1)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"shll %R0\;rotcl %S0"
[(set_attr "length" "4")
(set_attr "type" "arith")]) (set_attr "type" "arith")])
(define_insn "ashldi3_media"
[(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
(match_operand:DI 2 "shift_count_operand" "r,n")))]
"TARGET_SHMEDIA"
"@
shlld %1, %2, %0
shlli %1, %2, %0"
[(set_attr "type" "arith_media")])
(define_insn "*ashldisi3_media"
[(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")))]
"TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
"shlli.l %1, %2, %0"
[(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")])
;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
;; SImode arithmetic shift right
;; ;;
;; arithmetic shift right ;; We can't do HImode right shifts correctly unless we start out with an
;; ;; explicit zero / sign extension; doing that would result in worse overall
;; code, so just let the machine independent code widen the mode.
;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
(define_expand "ashrsi3"
[(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "nonmemory_operand" "")))
(clobber (reg:SI T_REG))])]
""
{
if (TARGET_SHMEDIA)
{
emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
DONE;
}
if (expand_ashiftrt (operands))
DONE;
else
FAIL;
})
(define_insn "ashrsi3_k" (define_insn "ashrsi3_k"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
...@@ -3645,14 +3765,6 @@ label: ...@@ -3645,14 +3765,6 @@ label:
"shar %0" "shar %0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
;; We can't do HImode right shifts correctly unless we start out with an
;; explicit zero / sign extension; doing that would result in worse overall
;; code, so just let the machine independent code widen the mode.
;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
;; ??? This should be a define expand.
(define_insn_and_split "ashrsi2_16" (define_insn_and_split "ashrsi2_16"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r") (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
...@@ -3666,8 +3778,6 @@ label: ...@@ -3666,8 +3778,6 @@ label:
operands[2] = gen_lowpart (HImode, operands[0]); operands[2] = gen_lowpart (HImode, operands[0]);
}) })
;; ??? This should be a define expand.
(define_insn_and_split "ashrsi2_31" (define_insn_and_split "ashrsi2_31"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
...@@ -3683,36 +3793,6 @@ label: ...@@ -3683,36 +3793,6 @@ label:
DONE; DONE;
}) })
(define_peephole2
[(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
(set (reg:SI T_REG)
(gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
"TARGET_SH1
&& peep2_reg_dead_p (2, operands[0])
&& peep2_reg_dead_p (2, operands[1])"
[(const_int 0)]
{
emit_insn (gen_ashlsi_c (operands[1], operands[1]));
DONE;
})
(define_insn "ashlsi_c"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
(set (reg:SI T_REG)
(lt:SI (match_dup 1) (const_int 0)))]
"TARGET_SH1"
"shll %0"
[(set_attr "type" "arith")])
(define_insn "*ashlsi_c_void"
[(set (reg:SI T_REG)
(lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
(clobber (match_scratch:SI 1 "=0"))]
"TARGET_SH1 && cse_not_expected"
"shll %0"
[(set_attr "type" "arith")])
(define_insn "ashrsi3_d" (define_insn "ashrsi3_d"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
...@@ -3744,25 +3824,105 @@ label: ...@@ -3744,25 +3824,105 @@ label:
[(set_attr "type" "arith_media") [(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")]) (set_attr "highpart" "ignore")])
(define_expand "ashrsi3" ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
[(parallel [(set (match_operand:SI 0 "arith_reg_dest" "") ;; DImode arithmetic shift right
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "nonmemory_operand" ""))) (define_expand "ashrdi3"
(clobber (reg:SI T_REG))])] [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
"" (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:SI T_REG))])]
""
{ {
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
{ {
emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2])); emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
DONE; DONE;
} }
if (expand_ashiftrt (operands)) if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
DONE;
else
FAIL; FAIL;
}) })
;; logical shift right ;; This should be a define_insn_and_split
(define_insn "ashrdi3_k"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
(const_int 1)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"shar %S0\;rotcr %R0"
[(set_attr "length" "4")
(set_attr "type" "arith")])
(define_insn "ashrdi3_media"
[(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
(match_operand:DI 2 "shift_count_operand" "r,n")))]
"TARGET_SHMEDIA
&& (arith_reg_dest (operands[0], DImode)
|| (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
"@
shard %1, %2, %0
shari %1, %2, %0"
[(set_attr "type" "arith_media")])
(define_insn "*ashrdisi3_media"
[(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")))]
"TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
"shari.l %1, %2, %0"
[(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")])
(define_insn "ashrdisi3_media_high"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(truncate:SI
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n"))))]
"TARGET_SHMEDIA && INTVAL (operands[2]) >= 32"
"shari %1, %2, %0"
[(set_attr "type" "arith_media")])
(define_insn "ashrdisi3_media_opaque"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")]
UNSPEC_ASHIFTRT))]
"TARGET_SHMEDIA"
"shari %1, %2, %0"
[(set_attr "type" "arith_media")])
;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
;; SImode logical shift right
;; Only the single bit shift clobbers the T bit.
(define_expand "lshrsi3"
[(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "nonmemory_operand" "")))
(clobber (reg:SI T_REG))])]
""
{
if (TARGET_SHMEDIA)
{
emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
DONE;
}
if (CONST_INT_P (operands[2])
&& sh_dynamicalize_shift_p (operands[2]))
operands[2] = force_reg (SImode, operands[2]);
if ((TARGET_SH3 || TARGET_SH2A)
&& arith_reg_operand (operands[2], GET_MODE (operands[2])))
{
rtx count = copy_to_mode_reg (SImode, operands[2]);
emit_insn (gen_negsi2 (count, count));
emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
DONE;
}
if (! immediate_operand (operands[2], GET_MODE (operands[2])))
FAIL;
})
(define_insn "lshrsi3_d" (define_insn "lshrsi3_d"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
...@@ -3772,8 +3932,6 @@ label: ...@@ -3772,8 +3932,6 @@ label:
"shld %2,%0" "shld %2,%0"
[(set_attr "type" "dyn_shift")]) [(set_attr "type" "dyn_shift")])
;; Only the single bit shift clobbers the T bit.
(define_insn "lshrsi3_m" (define_insn "lshrsi3_m"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
...@@ -3804,16 +3962,7 @@ label: ...@@ -3804,16 +3962,7 @@ label:
{ {
gen_shifty_op (LSHIFTRT, operands); gen_shifty_op (LSHIFTRT, operands);
DONE; DONE;
} })
[(set (attr "length")
(cond [(match_test "shift_insns_rtx (insn)")
(const_string "2")
(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
(const_string "4")
(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
(const_string "6")]
(const_string "8")))
(set_attr "type" "arith")])
(define_insn "lshrsi3_media" (define_insn "lshrsi3_media"
[(set (match_operand:SI 0 "arith_reg_dest" "=r,r") [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
...@@ -3826,116 +3975,26 @@ label: ...@@ -3826,116 +3975,26 @@ label:
[(set_attr "type" "arith_media") [(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")]) (set_attr "highpart" "ignore")])
(define_expand "lshrsi3" ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
[(parallel [(set (match_operand:SI 0 "arith_reg_dest" "") ;; DImode logical shift right
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "nonmemory_operand" "")))
(clobber (reg:SI T_REG))])]
""
{
if (TARGET_SHMEDIA)
{
emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
DONE;
}
if (CONST_INT_P (operands[2])
&& sh_dynamicalize_shift_p (operands[2]))
operands[2] = force_reg (SImode, operands[2]);
if ((TARGET_SH3 || TARGET_SH2A)
&& arith_reg_operand (operands[2], GET_MODE (operands[2])))
{
rtx count = copy_to_mode_reg (SImode, operands[2]);
emit_insn (gen_negsi2 (count, count));
emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
DONE;
}
if (! immediate_operand (operands[2], GET_MODE (operands[2])))
FAIL;
})
;; ??? This should be a define expand.
(define_insn "ashldi3_k"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
(const_int 1)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"shll %R0\;rotcl %S0"
[(set_attr "length" "4")
(set_attr "type" "arith")])
;; Expander for DImode shift left with SImode operations.
(define_expand "ashldi3_std"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")))]
"TARGET_SH1 && INTVAL (operands[2]) < 32"
{
rtx low_src = gen_lowpart (SImode, operands[1]);
rtx high_src = gen_highpart (SImode, operands[1]);
rtx dst = gen_reg_rtx (DImode);
rtx low_dst = gen_lowpart (SImode, dst);
rtx high_dst = gen_highpart (SImode, dst);
rtx tmp0 = gen_reg_rtx (SImode);
rtx tmp1 = gen_reg_rtx (SImode);
emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
emit_move_insn (operands[0], dst);
DONE;
})
(define_insn "ashldi3_media"
[(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
(match_operand:DI 2 "shift_count_operand" "r,n")))]
"TARGET_SHMEDIA"
"@
shlld %1, %2, %0
shlli %1, %2, %0"
[(set_attr "type" "arith_media")])
(define_insn "*ashldisi3_media" (define_expand "lshrdi3"
[(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")))]
"TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
"shlli.l %1, %2, %0"
[(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")])
(define_expand "ashldi3"
[(parallel [(set (match_operand:DI 0 "arith_reg_operand" "") [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "") (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:DI 2 "immediate_operand" ""))) (match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:SI T_REG))])] (clobber (reg:SI T_REG))])]
"" ""
{ {
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
{ {
emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2])); emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
DONE;
}
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
{
emit_insn (gen_ashldi3_k (operands[0], operands[1]));
DONE;
}
else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
{
emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
DONE; DONE;
} }
else if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
FAIL; FAIL;
}) })
;; ??? This should be a define expand. ;; This should be a define_insn_and_split
(define_insn "lshrdi3_k" (define_insn "lshrdi3_k"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0") (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
...@@ -3967,90 +4026,8 @@ label: ...@@ -3967,90 +4026,8 @@ label:
[(set_attr "type" "arith_media") [(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")]) (set_attr "highpart" "ignore")])
(define_expand "lshrdi3" ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
[(parallel [(set (match_operand:DI 0 "arith_reg_operand" "") ;; Combined left/right shifts
(lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:SI T_REG))])]
""
{
if (TARGET_SHMEDIA)
{
emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
DONE;
}
if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
FAIL;
})
;; ??? This should be a define expand.
(define_insn "ashrdi3_k"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
(const_int 1)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"shar %S0\;rotcr %R0"
[(set_attr "length" "4")
(set_attr "type" "arith")])
(define_insn "ashrdi3_media"
[(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
(match_operand:DI 2 "shift_count_operand" "r,n")))]
"TARGET_SHMEDIA
&& (arith_reg_dest (operands[0], DImode)
|| (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
"@
shard %1, %2, %0
shari %1, %2, %0"
[(set_attr "type" "arith_media")])
(define_insn "*ashrdisi3_media"
[(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")))]
"TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
"shari.l %1, %2, %0"
[(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")])
(define_insn "ashrdisi3_media_high"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(truncate:SI
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n"))))]
"TARGET_SHMEDIA && INTVAL (operands[2]) >= 32"
"shari %1, %2, %0"
[(set_attr "type" "arith_media")])
(define_insn "ashrdisi3_media_opaque"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")]
UNSPEC_ASHIFTRT))]
"TARGET_SHMEDIA"
"shari %1, %2, %0"
[(set_attr "type" "arith_media")])
(define_expand "ashrdi3"
[(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:SI T_REG))])]
""
{
if (TARGET_SHMEDIA)
{
emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
DONE;
}
if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
FAIL;
})
;; combined left/right shift
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
......
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