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riscv-gcc-1
Commit 5660465a by Kazu Hirata Committed by Jeff Law
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h8300-protos.h (general_operand_dst_push): Remove. 


        * h8300-protos.h (general_operand_dst_push): Remove.
        * h8300.c (general_operand_dst_push): Likewise.
        * h8300.h (OK_FOR_T): Likewise.
        (EXTRA_CONSTRAINTS): Do not use OK_FOR_T.
        * h8300.md (pushqi_h8300): New.
        (pushqi_h8300hs): Likewise.
        (pushqi): Likewise.
        (pushhi_h8300): Likewise.
        (pushhi_h8300hs): Likewise.
        (pushhi): Likewise.

From-SVN: r45470
parent 7b9e1fcf
Showing with 89 additions and 45 deletions
gcc/ChangeLog
Fri Sep 7 11:52:30 2001 Kazu Hirata <kazu@hxi.com>
* h8300-protos.h (general_operand_dst_push): Remove.
* h8300.c (general_operand_dst_push): Likewise.
* h8300.h (OK_FOR_T): Likewise.
(EXTRA_CONSTRAINTS): Do not use OK_FOR_T.
* h8300.md (pushqi_h8300): New.
(pushqi_h8300hs): Likewise.
(pushqi): Likewise.
(pushhi_h8300): Likewise.
(pushhi_h8300hs): Likewise.
(pushhi): Likewise.
Fri Sep 7 12:56:26 2001 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
* genattrtab.c (attr_printf): First arg is unsigned.
......
gcc/config/h8300/h8300-protos.h
......@@ -46,7 +46,6 @@ extern void split_adds_subs PARAMS ((enum machine_mode, rtx[]));
extern int general_operand_src PARAMS ((rtx, enum machine_mode));
extern int general_operand_dst PARAMS ((rtx, enum machine_mode));
extern int general_operand_dst_push PARAMS ((rtx, enum machine_mode mode));
extern int o_operand PARAMS ((rtx, enum machine_mode));
extern int p_operand PARAMS ((rtx, enum machine_mode));
extern int call_insn_operand PARAMS ((rtx, enum machine_mode));
......
gcc/config/h8300/h8300.c
......@@ -538,7 +538,7 @@ general_operand_src (op, mode)
}
/* Return true if OP is a valid destination operand for an integer move
instruction, excluding those involving pre_modify. */
instruction. */
int
general_operand_dst (op, mode)
......@@ -550,20 +550,6 @@ general_operand_dst (op, mode)
return general_operand (op, mode);
}
/* Return true if OP is a valid destination operand for an integer move
instruction, including those involving pre_modify. */
int
general_operand_dst_push (op, mode)
rtx op;
enum machine_mode mode;
{
if (push_operand (op, mode))
return 1;
return general_operand_dst (op, mode);
}
/* Return true if OP is a const valid for a bit clear instruction. */
int
......
gcc/config/h8300/h8300.h
......@@ -871,16 +871,6 @@ struct cum_arg
(GET_CODE (X) == CONST_INT && TARGET_H8300H \
&& 0xffff00 <= INTVAL (X) && INTVAL (X) <= 0xffffff)
/* 'T' if valid for a push destination using pre_modify. */
#define OK_FOR_T(OP) \
(GET_CODE (OP) == MEM \
&& GET_CODE (XEXP (OP, 0)) == PRE_MODIFY \
&& GET_CODE (XEXP (XEXP (OP, 0), 1)) == PLUS \
&& XEXP (XEXP (XEXP (OP, 0), 1), 0) == XEXP (XEXP (OP, 0), 0) \
&& GET_CODE (XEXP (XEXP (XEXP (OP, 0), 1), 1)) == CONST_INT \
&& INTVAL (XEXP (XEXP (XEXP (OP, 0), 1), 1)) == - (int) STACK_BOUNDARY / 8 \
&& XEXP (XEXP (OP, 0), 0) == stack_pointer_rtx)
/* 'U' if valid for a bset destination;
i.e. a register, register indirect, or the eightbit memory region
(a SYMBOL_REF with an SYMBOL_REF_FLAG set).
......@@ -903,8 +893,7 @@ struct cum_arg
&& GET_CODE (XEXP (OP, 0)) == CONST_INT))
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'T' ? OK_FOR_T (OP) : \
(C) == 'U' ? OK_FOR_U (OP) : \
((C) == 'U' ? OK_FOR_U (OP) : \
0)
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
......
gcc/config/h8300/h8300.md
......@@ -106,9 +106,41 @@
;; movqi
(define_insn "pushqi1_h8300"
[(parallel [(set (reg:HI 7)
(plus:HI (reg:HI 7) (const_int -2)))
(set (mem:QI (plus:HI (reg:HI 7) (const_int -1)))
(match_operand:QI 0 "register_operand" "r"))])]
"TARGET_H8300"
"mov.w %T0,@-r7"
[(set_attr "length" "2")
(set_attr "cc" "clobber")])
(define_insn "pushqi1_h8300hs"
[(parallel [(set (reg:SI 7)
(plus:SI (reg:SI 7) (const_int -4)))
(set (mem:QI (plus:SI (reg:SI 7) (const_int -3)))
(match_operand:QI 0 "register_operand" "r"))])]
"TARGET_H8300H || TARGET_H8300S"
"mov.l %S0,@-er7"
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
(define_expand "pushqi1"
[(use (match_operand:QI 0 "register_operand" "r"))]
""
"
{
if (TARGET_H8300)
emit_insn (gen_pushqi1_h8300 (operands[0]));
else
emit_insn (gen_pushqi1_h8300hs (operands[0]));
DONE;
}")
(define_insn ""
[(set (match_operand:QI 0 "general_operand_dst_push" "=r,r ,<,T,r,r,m")
(match_operand:QI 1 "general_operand_src" " I,r>,r,r,n,m,r"))]
[(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
(match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
"TARGET_H8300
&& (register_operand (operands[0],QImode)
|| register_operand (operands[1], QImode))"
......@@ -116,16 +148,15 @@
sub.b %X0,%X0
mov.b %R1,%X0
mov.b %X1,%R0
mov.w %T1,@-r7
mov.b %R1,%X0
mov.b %R1,%X0
mov.b %X1,%R0"
[(set_attr "length" "2,2,2,2,2,4,4")
(set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
[(set_attr "length" "2,2,2,2,4,4")
(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
(define_insn ""
[(set (match_operand:QI 0 "general_operand_dst_push" "=r,r ,<,r,T,r,m")
(match_operand:QI 1 "general_operand_src" " I,r>,r,n,r,m,r"))]
[(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
(match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
"(TARGET_H8300H || TARGET_H8300S)
&& (register_operand (operands[0],QImode)
|| register_operand (operands[1], QImode))"
......@@ -134,14 +165,13 @@
mov.b %R1,%X0
mov.b %X1,%R0
mov.b %R1,%X0
mov.l %S1,@-er7
mov.b %R1,%X0
mov.b %X1,%R0"
[(set_attr "length" "2,2,2,2,4,8,8")
(set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
[(set_attr "length" "2,2,2,2,8,8")
(set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand_dst_push" "")
[(set (match_operand:QI 0 "general_operand_dst" "")
(match_operand:QI 1 "general_operand_src" ""))]
""
"
......@@ -170,6 +200,34 @@
;; movhi
(define_expand "pushhi1_h8300"
[(set (mem:QI (pre_dec:HI (reg:HI 7)))
(match_operand:QI 0 "register_operand" "r"))]
"TARGET_H8300"
"")
(define_insn "pushhi1_h8300hs"
[(parallel [(set (reg:SI 7)
(plus:SI (reg:SI 7) (const_int -4)))
(set (mem:HI (plus:SI (reg:SI 7) (const_int -2)))
(match_operand:HI 0 "register_operand" "r"))])]
"TARGET_H8300H || TARGET_H8300S"
"mov.l %S0,@-er7"
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
(define_expand "pushhi1"
[(use (match_operand:QI 0 "register_operand" "r"))]
""
"
{
if (TARGET_H8300)
emit_insn (gen_pushhi1_h8300 (operands[0]));
else
emit_insn (gen_pushhi1_h8300hs (operands[0]));
DONE;
}")
(define_insn ""
[(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
(match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
......@@ -192,8 +250,8 @@
(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
(define_insn ""
[(set (match_operand:HI 0 "general_operand_dst_push" "=r,r,<,T,r,r,m")
(match_operand:HI 1 "general_operand_src" "I,r>,r,r,i,m,r"))]
[(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
(match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
"(TARGET_H8300H || TARGET_H8300S)
&& (register_operand (operands[0],HImode)
|| register_operand (operands[1], HImode))"
......@@ -201,15 +259,14 @@
sub.w %T0,%T0
mov.w %T1,%T0
mov.w %T1,%T0
mov.l %S1,@-er7
mov.w %T1,%T0
mov.w %T1,%T0
mov.w %T1,%T0"
[(set_attr "length" "2,2,2,4,4,8,8")
(set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
[(set_attr "length" "2,2,2,4,8,8")
(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand_dst_push" "")
[(set (match_operand:HI 0 "general_operand_dst" "")
(match_operand:HI 1 "general_operand_src" ""))]
""
"
......
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