sparc.c (INIT_TARGET_OPTABS): If ARCH64, set the 32-bit ABI libfuncs to NULL.

2002-06-24  David S. Miller  <davem@redhat.com>

	* config/sparc/sparc.c (INIT_TARGET_OPTABS): If ARCH64, set the
	32-bit ABI libfuncs to NULL.

From-SVN: r54952

gcc/ChangeLog

@@ -3,7 +3,8 @@
 	* config/sparc/sparc.c (INIT_TARGET_OPTABS): If ARCH64, set the
 	32-bit ABI libfuncs to NULL.
 
-	* config/sparc/sparc.md: Use define_insn_and_split.
+	* config/sparc/sparc.md: Use define_insn_and_split.  Use braced
+	strings instead of quoted strings for code blocks.
 
 	* expmed.c (expand_divmod): Do not set optab1/optab2 to the shift
 	optabs if op1 is const0_rtx.

gcc/config/sparc/sparc.md

@@ -289,24 +289,22 @@
 	(compare:CC (match_operand:SI 0 "register_operand" "")
 		    (match_operand:SI 1 "arith_operand" "")))]
   ""
-  "
 {
   sparc_compare_op0 = operands[0];
   sparc_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpdi"
   [(set (reg:CCX 100)
 	(compare:CCX (match_operand:DI 0 "register_operand" "")
 		     (match_operand:DI 1 "arith_double_operand" "")))]
   "TARGET_ARCH64"
-  "
 {
   sparc_compare_op0 = operands[0];
   sparc_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpsf"
   ;; The 96 here isn't ever used by anyone.
@@ -314,12 +312,11 @@
 	(compare:CCFP (match_operand:SF 0 "register_operand" "")
 		      (match_operand:SF 1 "register_operand" "")))]
   "TARGET_FPU"
-  "
 {
   sparc_compare_op0 = operands[0];
   sparc_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpdf"
   ;; The 96 here isn't ever used by anyone.
@@ -327,12 +324,11 @@
 	(compare:CCFP (match_operand:DF 0 "register_operand" "")
 		      (match_operand:DF 1 "register_operand" "")))]
   "TARGET_FPU"
-  "
 {
   sparc_compare_op0 = operands[0];
   sparc_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmptf"
   ;; The 96 here isn't ever used by anyone.
@@ -340,12 +336,11 @@
 	(compare:CCFP (match_operand:TF 0 "register_operand" "")
 		      (match_operand:TF 1 "register_operand" "")))]
   "TARGET_FPU"
-  "
 {
   sparc_compare_op0 = operands[0];
   sparc_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 ;; Now the compare DEFINE_INSNs.
 
@@ -370,12 +365,11 @@
 	(compare:CCFPE (match_operand:SF 1 "register_operand" "f")
 		       (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_FPU"
-  "*
 {
   if (TARGET_V9)
-    return \"fcmpes\\t%0, %1, %2\";
-  return \"fcmpes\\t%1, %2\";
-}"
+    return "fcmpes\\t%0, %1, %2";
+  return "fcmpes\\t%1, %2";
+}
   [(set_attr "type" "fpcmp")])
 
 (define_insn "*cmpdf_fpe"
@@ -383,12 +377,11 @@
 	(compare:CCFPE (match_operand:DF 1 "register_operand" "e")
 		       (match_operand:DF 2 "register_operand" "e")))]
   "TARGET_FPU"
-  "*
 {
   if (TARGET_V9)
-    return \"fcmped\\t%0, %1, %2\";
-  return \"fcmped\\t%1, %2\";
-}"
+    return "fcmped\\t%0, %1, %2";
+  return "fcmped\\t%1, %2";
+}
   [(set_attr "type" "fpcmp")
    (set_attr "fptype" "double")])
 
@@ -397,12 +390,11 @@
 	(compare:CCFPE (match_operand:TF 1 "register_operand" "e")
 		       (match_operand:TF 2 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
-  "*
 {
   if (TARGET_V9)
-    return \"fcmpeq\\t%0, %1, %2\";
-  return \"fcmpeq\\t%1, %2\";
-}"
+    return "fcmpeq\\t%0, %1, %2";
+  return "fcmpeq\\t%1, %2";
+}
   [(set_attr "type" "fpcmp")])
 
 (define_insn "*cmpsf_fp"
@@ -410,12 +402,11 @@
 	(compare:CCFP (match_operand:SF 1 "register_operand" "f")
 		      (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_FPU"
-  "*
 {
   if (TARGET_V9)
-    return \"fcmps\\t%0, %1, %2\";
-  return \"fcmps\\t%1, %2\";
-}"
+    return "fcmps\\t%0, %1, %2";
+  return "fcmps\\t%1, %2";
+}
   [(set_attr "type" "fpcmp")])
 
 (define_insn "*cmpdf_fp"
@@ -423,12 +414,11 @@
 	(compare:CCFP (match_operand:DF 1 "register_operand" "e")
 		      (match_operand:DF 2 "register_operand" "e")))]
   "TARGET_FPU"
-  "*
 {
   if (TARGET_V9)
-    return \"fcmpd\\t%0, %1, %2\";
-  return \"fcmpd\\t%1, %2\";
-}"
+    return "fcmpd\\t%0, %1, %2";
+  return "fcmpd\\t%1, %2";
+}
   [(set_attr "type" "fpcmp")
    (set_attr "fptype" "double")])
 
@@ -437,12 +427,11 @@
 	(compare:CCFP (match_operand:TF 1 "register_operand" "e")
 		      (match_operand:TF 2 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
-  "*
 {
   if (TARGET_V9)
-    return \"fcmpq\\t%0, %1, %2\";
-  return \"fcmpq\\t%1, %2\";
-}"
+    return "fcmpq\\t%0, %1, %2";
+  return "fcmpq\\t%1, %2";
+}
   [(set_attr "type" "fpcmp")])
 
 ;; Next come the scc insns.  For seq, sne, sgeu, and sltu, we can do this
@@ -463,7 +452,7 @@
 		   (eq:SI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
   ""
-  "{ operands[3] = gen_reg_rtx (SImode); }")
+  { operands[3] = gen_reg_rtx (SImode); })
 
 (define_expand "seqdi_special"
   [(set (match_dup 3)
@@ -472,7 +461,7 @@
    (set (match_operand:DI 0 "register_operand" "")
 	(eq:DI (match_dup 3) (const_int 0)))]
   "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (DImode); }")
+  { operands[3] = gen_reg_rtx (DImode); })
 
 (define_expand "snesi_special"
   [(set (match_dup 3)
@@ -482,7 +471,7 @@
 		   (ne:SI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
   ""
-  "{ operands[3] = gen_reg_rtx (SImode); }")
+  { operands[3] = gen_reg_rtx (SImode); })
 
 (define_expand "snedi_special"
   [(set (match_dup 3)
@@ -491,7 +480,7 @@
    (set (match_operand:DI 0 "register_operand" "")
 	(ne:DI (match_dup 3) (const_int 0)))]
   "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (DImode); }")
+  { operands[3] = gen_reg_rtx (DImode); })
 
 (define_expand "seqdi_special_trunc"
   [(set (match_dup 3)
@@ -500,7 +489,7 @@
    (set (match_operand:SI 0 "register_operand" "")
 	(eq:SI (match_dup 3) (const_int 0)))]
   "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (DImode); }")
+  { operands[3] = gen_reg_rtx (DImode); })
 
 (define_expand "snedi_special_trunc"
   [(set (match_dup 3)
@@ -509,7 +498,7 @@
    (set (match_operand:SI 0 "register_operand" "")
 	(ne:SI (match_dup 3) (const_int 0)))]
   "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (DImode); }")
+  { operands[3] = gen_reg_rtx (DImode); })
 
 (define_expand "seqsi_special_extend"
   [(set (match_dup 3)
@@ -519,7 +508,7 @@
 		   (eq:DI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
   "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (SImode); }")
+  { operands[3] = gen_reg_rtx (SImode); })
 
 (define_expand "snesi_special_extend"
   [(set (match_dup 3)
@@ -529,7 +518,7 @@
 		   (ne:DI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
   "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (SImode); }")
+  { operands[3] = gen_reg_rtx (SImode); })
 
 ;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
 ;; However, the code handles both SImode and DImode.
@@ -537,7 +526,6 @@
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(eq:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == SImode)
     {
@@ -582,7 +570,7 @@
       /* fall through */
     }
   FAIL;
-}")
+})
 
 ;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
 ;; However, the code handles both SImode and DImode.
@@ -590,7 +578,6 @@
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(ne:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == SImode)
     {
@@ -635,13 +622,12 @@
       /* fall through */
     }
   FAIL;
-}")
+})
 
 (define_expand "sgt"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(gt:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -656,13 +642,12 @@
       /* fall through */
     }
   FAIL;
-}")
+})
 
 (define_expand "slt"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(lt:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -677,13 +662,12 @@
       /* fall through */
     }
   FAIL;
-}")
+})
 
 (define_expand "sge"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(ge:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -698,13 +682,12 @@
       /* fall through */
     }
   FAIL;
-}")
+})
 
 (define_expand "sle"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(le:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -719,13 +702,12 @@
       /* fall through */
     }
   FAIL;
-}")
+})
 
 (define_expand "sgtu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(gtu:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (! TARGET_V9)
     {
@@ -754,13 +736,12 @@
 	DONE;
     }
   FAIL;
-}")
+})
 
 (define_expand "sltu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(ltu:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (TARGET_V9)
     {
@@ -768,13 +749,12 @@
 	DONE;
     }
   operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "sgeu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(geu:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (TARGET_V9)
     {
@@ -782,13 +762,12 @@
 	DONE;
     }
   operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "sleu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(leu:SI (match_dup 1) (const_int 0)))]
   ""
-  "
 {
   if (! TARGET_V9)
     {
@@ -817,7 +796,7 @@
 	DONE;
     }
   FAIL;
-}")
+})
 
 ;; Now the DEFINE_INSNs for the scc cases.
 
@@ -1218,7 +1197,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
       && GET_CODE (sparc_compare_op0) == REG
@@ -1234,7 +1212,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (EQ, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bne"
   [(set (pc)
@@ -1242,7 +1220,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
       && GET_CODE (sparc_compare_op0) == REG
@@ -1258,7 +1235,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (NE, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bgt"
   [(set (pc)
@@ -1266,7 +1243,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
       && GET_CODE (sparc_compare_op0) == REG
@@ -1282,7 +1258,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (GT, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bgtu"
   [(set (pc)
@@ -1290,9 +1266,9 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{ operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1);
-}")
+{
+  operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1);
+})
 
 (define_expand "blt"
   [(set (pc)
@@ -1300,7 +1276,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
       && GET_CODE (sparc_compare_op0) == REG
@@ -1316,7 +1291,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (LT, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bltu"
   [(set (pc)
@@ -1324,9 +1299,9 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{ operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
-}")
+{
+  operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
+})
 
 (define_expand "bge"
   [(set (pc)
@@ -1334,7 +1309,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
       && GET_CODE (sparc_compare_op0) == REG
@@ -1350,7 +1324,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (GE, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bgeu"
   [(set (pc)
@@ -1358,9 +1332,9 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{ operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
-}")
+{
+  operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
+})
 
 (define_expand "ble"
   [(set (pc)
@@ -1368,7 +1342,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
       && GET_CODE (sparc_compare_op0) == REG
@@ -1384,7 +1357,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (LE, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bleu"
   [(set (pc)
@@ -1392,9 +1365,9 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{ operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1);
-}")
+{
+  operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1);
+})
 
 (define_expand "bunordered"
   [(set (pc)
@@ -1402,7 +1375,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -1413,7 +1385,7 @@
     }
   operands[1] = gen_compare_reg (UNORDERED, sparc_compare_op0,
 				 sparc_compare_op1);
-}")
+})
 
 (define_expand "bordered"
   [(set (pc)
@@ -1421,7 +1393,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -1431,7 +1402,7 @@
     }
   operands[1] = gen_compare_reg (ORDERED, sparc_compare_op0,
 				 sparc_compare_op1);
-}")
+})
 
 (define_expand "bungt"
   [(set (pc)
@@ -1439,7 +1410,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -1448,7 +1418,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (UNGT, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bunlt"
   [(set (pc)
@@ -1456,7 +1426,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -1465,7 +1434,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (UNLT, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "buneq"
   [(set (pc)
@@ -1473,7 +1442,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -1482,7 +1450,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (UNEQ, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bunge"
   [(set (pc)
@@ -1490,7 +1458,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -1499,7 +1466,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (UNGE, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bunle"
   [(set (pc)
@@ -1507,7 +1474,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -1516,7 +1482,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (UNLE, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 (define_expand "bltgt"
   [(set (pc)
@@ -1524,7 +1490,6 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
     {
@@ -1533,7 +1498,7 @@
       DONE;
     }
   operands[1] = gen_compare_reg (LTGT, sparc_compare_op0, sparc_compare_op1);
-}")
+})
 
 ;; Now match both normal and inverted jump.
 
@@ -1545,12 +1510,11 @@
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
   ""
-  "*
 {
   return output_cbranch (operands[0], operands[1], 1, 0,
 			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
 			 ! final_sequence, insn);
-}"
+}
   [(set_attr "type" "branch")
    (set_attr "branch_type" "icc")])
 
@@ -1562,12 +1526,11 @@
 		      (pc)
 		      (label_ref (match_operand 1 "" ""))))]
   ""
-  "*
 {
   return output_cbranch (operands[0], operands[1], 1, 1,
 			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
 			 ! final_sequence, insn);
-}"
+}
   [(set_attr "type" "branch")
    (set_attr "branch_type" "icc")])
 
@@ -1580,12 +1543,11 @@
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
   ""
-  "*
 {
   return output_cbranch (operands[1], operands[2], 2, 0,
 			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
 			 ! final_sequence, insn);
-}"
+}
   [(set_attr "type" "branch")
    (set_attr "branch_type" "fcc")])
 
@@ -1598,12 +1560,11 @@
 		      (pc)
 		      (label_ref (match_operand 2 "" ""))))]
   ""
-  "*
 {
   return output_cbranch (operands[1], operands[2], 2, 1,
 			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
 			 ! final_sequence, insn);
-}"
+}
   [(set_attr "type" "branch")
    (set_attr "branch_type" "fcc")])
 
@@ -1616,12 +1577,11 @@
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
   ""
-  "*
 {
   return output_cbranch (operands[1], operands[2], 2, 0,
 			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
 			 ! final_sequence, insn);
-}"
+}
   [(set_attr "type" "branch")
    (set_attr "branch_type" "fcc")])
 
@@ -1634,12 +1594,11 @@
 		      (pc)
 		      (label_ref (match_operand 2 "" ""))))]
   ""
-  "*
 {
   return output_cbranch (operands[1], operands[2], 2, 1,
 			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
 			 ! final_sequence, insn);
-}"
+}
   [(set_attr "type" "branch")
    (set_attr "branch_type" "fcc")])
 
@@ -1657,12 +1616,11 @@
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
   "TARGET_ARCH64"
-  "*
 {
   return output_v9branch (operands[0], operands[2], 1, 2, 0,
 			  final_sequence && INSN_ANNULLED_BRANCH_P (insn),
 			  ! final_sequence, insn);
-}"
+}
   [(set_attr "type" "branch")
    (set_attr "branch_type" "reg")])
 
@@ -1675,12 +1633,11 @@
 		      (pc)
 		      (label_ref (match_operand 2 "" ""))))]
   "TARGET_ARCH64"
-  "*
 {
   return output_v9branch (operands[0], operands[2], 1, 2, 1,
 			  final_sequence && INSN_ANNULLED_BRANCH_P (insn),
 			  ! final_sequence, insn);
-}"
+}
   [(set_attr "type" "branch")
    (set_attr "branch_type" "reg")])
 
@@ -1702,7 +1659,6 @@
   [(set (match_operand:QI 0 "general_operand" "")
 	(match_operand:QI 1 "general_operand" ""))]
   ""
-  "
 {
   /* Working with CONST_INTs is easier, so convert
      a double if needed.  */
@@ -1747,7 +1703,7 @@
 
  movqi_is_ok:
   ;
-}")
+})
 
 (define_insn "*movqi_insn"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m")
@@ -1765,7 +1721,6 @@
   [(set (match_operand:HI 0 "general_operand" "")
 	(match_operand:HI 1 "general_operand" ""))]
   ""
-  "
 {
   /* Working with CONST_INTs is easier, so convert
      a double if needed.  */
@@ -1815,7 +1770,7 @@
     }
  movhi_is_ok:
   ;
-}")
+})
 
 (define_insn "*movhi_const64_special"
   [(set (match_operand:HI 0 "register_operand" "=r")
@@ -1848,7 +1803,6 @@
   [(set (match_operand:SI 0 "general_operand" "")
 	(match_operand:SI 1 "general_operand" ""))]
   ""
-  "
 {
   /* Working with CONST_INTs is easier, so convert
      a double if needed.  */
@@ -1914,7 +1868,7 @@
     }
  movsi_is_ok:
   ;
-}")
+})
 
 ;; This is needed to show CSE exactly which bits are set
 ;; in a 64-bit register by sethi instructions.
@@ -1978,10 +1932,9 @@
    (set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (match_dup 5) (match_dup 4)))]
   "flag_pic"
-  "
 {
   current_function_uses_pic_offset_table = 1;
-  operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
+  operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
   if (no_new_pseudos)
     {
       operands[3] = operands[0];
@@ -1993,7 +1946,7 @@
       operands[4] = gen_reg_rtx (SImode);
     }
   operands[5] = pic_offset_table_rtx;
-}")
+})
 
 (define_insn "*movsi_high_pic_label_ref"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2015,7 +1968,6 @@
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
 	(match_operand:DI 1 "general_operand" ""))]
   ""
-  "
 {
   /* Where possible, convert CONST_DOUBLE into a CONST_INT.  */
   if (GET_CODE (operands[1]) == CONST_DOUBLE
@@ -2094,7 +2046,7 @@
 
  movdi_is_ok:
   ;
-}")
+})
 
 ;; Be careful, fmovd does not exist when !arch64.
 ;; We match MEM moves directly when we have correct even
@@ -2218,10 +2170,9 @@
    (set (match_operand:DI 0 "register_operand" "=r")
         (minus:DI (match_dup 5) (match_dup 4)))]
   "TARGET_ARCH64 && flag_pic"
-  "
 {
   current_function_uses_pic_offset_table = 1;
-  operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
+  operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
   if (no_new_pseudos)
     {
       operands[3] = operands[0];
@@ -2233,7 +2184,7 @@
       operands[4] = gen_reg_rtx (DImode);
     }
   operands[5] = pic_offset_table_rtx;
-}")
+})
 
 (define_insn "*movdi_high_pic_label_ref"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -2385,11 +2336,10 @@
   "(TARGET_CM_MEDANY
     || TARGET_CM_EMBMEDANY)
    && ! flag_pic"
-  "
 {
   sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
   DONE;
-}")
+})
 
 (define_expand "reload_outdi"
   [(parallel [(match_operand:DI 0 "register_operand" "=r")
@@ -2398,11 +2348,10 @@
   "(TARGET_CM_MEDANY
     || TARGET_CM_EMBMEDANY)
    && ! flag_pic"
-  "
 {
   sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
   DONE;
-}")
+})
 
 ;; Split up putting CONSTs and REGs into DI regs when !arch64
 (define_split
@@ -2410,7 +2359,6 @@
         (match_operand:DI 1 "const_int_operand" ""))]
   "! TARGET_ARCH64 && reload_completed"
   [(clobber (const_int 0))]
-  "
 {
 #if HOST_BITS_PER_WIDE_INT == 32
   emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
@@ -2435,14 +2383,13 @@
     emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), GEN_INT (low)));
 #endif
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
         (match_operand:DI 1 "const_double_operand" ""))]
   "! TARGET_ARCH64 && reload_completed"
   [(clobber (const_int 0))]
-  "
 {
   emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
 			GEN_INT (CONST_DOUBLE_HIGH (operands[1]))));
@@ -2462,14 +2409,13 @@
 			    GEN_INT (CONST_DOUBLE_LOW (operands[1]))));
     }
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
         (match_operand:DI 1 "register_operand" ""))]
   "! TARGET_ARCH64 && reload_completed"
   [(clobber (const_int 0))]
-  "
 {
   rtx set_dest = operands[0];
   rtx set_src = operands[1];
@@ -2494,7 +2440,7 @@
       emit_insn (gen_movsi (dest2, src2));
     }
   DONE;
-}")
+})
 
 ;; Now handle the cases of memory moves from/to non-even
 ;; DI mode register pairs.
@@ -2505,7 +2451,6 @@
     && reload_completed
     && sparc_splitdi_legitimate (operands[0], operands[1]))"
   [(clobber (const_int 0))]
-  "
 {
   rtx word0 = adjust_address (operands[1], SImode, 0);
   rtx word1 = adjust_address (operands[1], SImode, 4);
@@ -2523,7 +2468,7 @@
       emit_insn (gen_movsi (low_part, word1));
     }
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
@@ -2532,14 +2477,13 @@
     && reload_completed
     && sparc_splitdi_legitimate (operands[1], operands[0]))"
   [(clobber (const_int 0))]
-  "
 {
   emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0),
 			gen_highpart (SImode, operands[1])));
   emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4),
 			gen_lowpart (SImode, operands[1])));
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
@@ -2550,12 +2494,11 @@
 	   && ! mem_min_alignment (operands[0], 8)))
    && offsettable_memref_p (operands[0])"
   [(clobber (const_int 0))]
-  "
 {
   emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx));
   emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx));
   DONE;
-}")
+})
 
 ;; Floating point move insns
 
@@ -2566,7 +2509,6 @@
    && (register_operand (operands[0], SFmode)
        || register_operand (operands[1], SFmode)
        || fp_zero_operand (operands[1], SFmode))"
-  "*
 {
   if (GET_CODE (operands[1]) == CONST_DOUBLE
       && (which_alternative == 2
@@ -2584,25 +2526,25 @@
   switch (which_alternative)
     {
     case 0:
-      return \"fmovs\\t%1, %0\";
+      return "fmovs\\t%1, %0";
     case 1:
-      return \"clr\\t%0\";
+      return "clr\\t%0";
     case 2:
-      return \"sethi\\t%%hi(%a1), %0\";
+      return "sethi\\t%%hi(%a1), %0";
     case 3:
-      return \"mov\\t%1, %0\";
+      return "mov\\t%1, %0";
     case 4:
-      return \"#\";
+      return "#";
     case 5:
     case 6:
-      return \"ld\\t%1, %0\";
+      return "ld\\t%1, %0";
     case 7:
     case 8:
-      return \"st\\t%r1, %0\";
+      return "st\\t%r1, %0";
     default:
       abort();
     }
-}"
+}
   [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")])
 
 (define_insn "*movsf_insn_vis"
@@ -2612,7 +2554,6 @@
    && (register_operand (operands[0], SFmode)
        || register_operand (operands[1], SFmode)
        || fp_zero_operand (operands[1], SFmode))"
-  "*
 {
   if (GET_CODE (operands[1]) == CONST_DOUBLE
       && (which_alternative == 3
@@ -2630,27 +2571,27 @@
   switch (which_alternative)
     {
     case 0:
-      return \"fmovs\\t%1, %0\";
+      return "fmovs\\t%1, %0";
     case 1:
-      return \"fzeros\\t%0\";
+      return "fzeros\\t%0";
     case 2:
-      return \"clr\\t%0\";
+      return "clr\\t%0";
     case 3:
-      return \"sethi\\t%%hi(%a1), %0\";
+      return "sethi\\t%%hi(%a1), %0";
     case 4:
-      return \"mov\\t%1, %0\";
+      return "mov\\t%1, %0";
     case 5:
-      return \"#\";
+      return "#";
     case 6:
     case 7:
-      return \"ld\\t%1, %0\";
+      return "ld\\t%1, %0";
     case 8:
     case 9:
-      return \"st\\t%r1, %0\";
+      return "st\\t%r1, %0";
     default:
       abort();
     }
-}"
+}
   [(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")])
 
 ;; Exactly the same as above, except that all `f' cases are deleted.
@@ -2664,7 +2605,6 @@
    && (register_operand (operands[0], SFmode)
        || register_operand (operands[1], SFmode)
        || fp_zero_operand (operands[1], SFmode))"
-  "*
 {
   if (GET_CODE (operands[1]) == CONST_DOUBLE
       && (which_alternative == 1
@@ -2682,21 +2622,21 @@
   switch (which_alternative)
     {
     case 0:
-      return \"clr\\t%0\";
+      return "clr\\t%0";
     case 1:
-      return \"sethi\\t%%hi(%a1), %0\";
+      return "sethi\\t%%hi(%a1), %0";
     case 2:
-      return \"mov\\t%1, %0\";
+      return "mov\\t%1, %0";
     case 3:
-      return \"#\";
+      return "#";
     case 4:
-      return \"ld\\t%1, %0\";
+      return "ld\\t%1, %0";
     case 5:
-      return \"st\\t%r1, %0\";
+      return "st\\t%r1, %0";
     default:
       abort();
     }
-}"
+}
   [(set_attr "type" "*,*,*,*,load,store")])
 
 (define_insn "*movsf_lo_sum"
@@ -2704,7 +2644,6 @@
         (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
                    (match_operand:SF 2 "const_double_operand" "S")))]
   "fp_high_losum_p (operands[2])"
-  "*
 {
   REAL_VALUE_TYPE r;
   long i;
@@ -2712,14 +2651,13 @@
   REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
   REAL_VALUE_TO_TARGET_SINGLE (r, i);
   operands[2] = GEN_INT (i);
-  return \"or\\t%1, %%lo(%a2), %0\";
-}")
+  return "or\\t%1, %%lo(%a2), %0";
+})
 
 (define_insn "*movsf_high"
   [(set (match_operand:SF 0 "register_operand" "=r")
         (high:SF (match_operand:SF 1 "const_double_operand" "S")))]
   "fp_high_losum_p (operands[1])"
-  "*
 {
   REAL_VALUE_TYPE r;
   long i;
@@ -2727,8 +2665,8 @@
   REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
   REAL_VALUE_TO_TARGET_SINGLE (r, i);
   operands[1] = GEN_INT (i);
-  return \"sethi\\t%%hi(%1), %0\";
-}")
+  return "sethi\\t%%hi(%1), %0";
+})
 
 (define_split
   [(set (match_operand:SF 0 "register_operand" "")
@@ -2743,7 +2681,6 @@
   [(set (match_operand:SF 0 "general_operand" "")
 	(match_operand:SF 1 "general_operand" ""))]
   ""
-  "
 {
   /* Force SFmode constants into memory.  */
   if (GET_CODE (operands[0]) == REG
@@ -2800,13 +2737,12 @@
 
  movsf_is_ok:
   ;
-}")
+})
 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "general_operand" "")
 	(match_operand:DF 1 "general_operand" ""))]
   ""
-  "
 {
   /* Force DFmode constants into memory.  */
   if (GET_CODE (operands[0]) == REG
@@ -2864,7 +2800,7 @@
 
  movdf_is_ok:
   ;
-}")
+})
 
 ;; Be careful, fmovd does not exist when !v9.
 (define_insn "*movdf_insn_sp32"
@@ -3047,7 +2983,6 @@
    && ! fp_zero_operand(operands[1], DFmode)
    && reload_completed"
   [(clobber (const_int 0))]
-  "
 {
   REAL_VALUE_TYPE r;
   long l[2];
@@ -3090,7 +3025,7 @@
         }
     }
   DONE;
-}")
+})
 
 ;; Ok, now the splits to handle all the multi insn and
 ;; mis-aligned memory address cases.
@@ -3109,7 +3044,6 @@
                 && REGNO (SUBREG_REG (operands[0])) < 32))))
    && reload_completed"
   [(clobber (const_int 0))]
-  "
 {
   rtx set_dest = operands[0];
   rtx set_src = operands[1];
@@ -3134,7 +3068,7 @@
       emit_insn (gen_movsf (dest2, src2));
     }
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:DF 0 "register_operand" "")
@@ -3145,7 +3079,6 @@
        || ! mem_min_alignment (operands[1], 8))
    && offsettable_memref_p (operands[1])"
   [(clobber (const_int 0))]
-  "
 {
   rtx word0 = adjust_address (operands[1], SFmode, 0);
   rtx word1 = adjust_address (operands[1], SFmode, 4);
@@ -3165,7 +3098,7 @@
 			    word1));
     }
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:DF 0 "memory_operand" "")
@@ -3176,7 +3109,6 @@
        || ! mem_min_alignment (operands[0], 8))
    && offsettable_memref_p (operands[0])"
   [(clobber (const_int 0))]
-  "
 {
   rtx word0 = adjust_address (operands[0], SFmode, 0);
   rtx word1 = adjust_address (operands[0], SFmode, 4);
@@ -3186,7 +3118,7 @@
   emit_insn (gen_movsf (word1,
 			gen_lowpart (SFmode, operands[1])));
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:DF 0 "memory_operand" "")
@@ -3197,7 +3129,6 @@
 	   && ! mem_min_alignment (operands[0], 8)))
    && offsettable_memref_p (operands[0])"
   [(clobber (const_int 0))]
-  "
 {
   rtx dest1, dest2;
 
@@ -3207,7 +3138,7 @@
   emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
   emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:DF 0 "register_operand" "")
@@ -3220,7 +3151,6 @@
 	   && GET_CODE (SUBREG_REG (operands[0])) == REG
 	   && REGNO (SUBREG_REG (operands[0])) < 32))"
   [(clobber (const_int 0))]
-  "
 {
   rtx set_dest = operands[0];
   rtx dest1, dest2;
@@ -3230,13 +3160,12 @@
   emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
   emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
   DONE;
-}")
+})
 
 (define_expand "movtf"
   [(set (match_operand:TF 0 "general_operand" "")
 	(match_operand:TF 1 "general_operand" ""))]
   ""
-  "
 {
   /* Force TFmode constants into memory.  */
   if (GET_CODE (operands[0]) == REG
@@ -3289,7 +3218,7 @@
 
  movtf_is_ok:
   ;
-}")
+})
 
 ;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so
 ;; we must split them all.  :-(
@@ -3422,7 +3351,6 @@
            && ! TARGET_HARD_QUAD)
        || ! fp_register_operand (operands[0], TFmode))"
   [(clobber (const_int 0))]
-  "
 {
   rtx set_dest = operands[0];
   rtx set_src = operands[1];
@@ -3447,14 +3375,13 @@
       emit_insn (gen_movdf (dest2, src2));
     }
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:TF 0 "nonimmediate_operand" "")
         (match_operand:TF 1 "fp_zero_operand" ""))]
   "reload_completed"
   [(clobber (const_int 0))]
-  "
 {
   rtx set_dest = operands[0];
   rtx dest1, dest2;
@@ -3476,7 +3403,7 @@
   emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode)));
   emit_insn (gen_movdf (dest2, CONST0_RTX (DFmode)));
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:TF 0 "register_operand" "")
@@ -3487,7 +3414,6 @@
 	|| ! TARGET_HARD_QUAD
 	|| ! fp_register_operand (operands[0], TFmode)))"
   [(clobber (const_int 0))]
-  "
 {
   rtx word0 = adjust_address (operands[1], DFmode, 0);
   rtx word1 = adjust_address (operands[1], DFmode, 8);
@@ -3512,7 +3438,7 @@
       emit_insn (gen_movdf (dest2, word1));
    }
   DONE;
-}")
+})
 
 (define_split
   [(set (match_operand:TF 0 "memory_operand" "")
@@ -3523,7 +3449,6 @@
 	|| ! TARGET_HARD_QUAD
 	|| ! fp_register_operand (operands[1], TFmode)))"
   [(clobber (const_int 0))]
-  "
 {
   rtx set_src = operands[1];
 
@@ -3532,7 +3457,7 @@
   emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 8),
 			gen_df_reg (set_src, 1)));
   DONE;
-}")
+})
 
 ;; Sparc V9 conditional move instructions.
 
@@ -3548,7 +3473,6 @@
 			 (match_operand:QI 2 "arith10_operand" "")
 			 (match_operand:QI 3 "arith10_operand" "")))]
   "TARGET_V9"
-  "
 {
   enum rtx_code code = GET_CODE (operands[1]);
 
@@ -3570,7 +3494,7 @@
 				    sparc_compare_op0, sparc_compare_op1);
       operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
     }
-}")
+})
 
 (define_expand "movhicc"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -3578,7 +3502,6 @@
 			 (match_operand:HI 2 "arith10_operand" "")
 			 (match_operand:HI 3 "arith10_operand" "")))]
   "TARGET_V9"
-  "
 {
   enum rtx_code code = GET_CODE (operands[1]);
 
@@ -3600,7 +3523,7 @@
 				    sparc_compare_op0, sparc_compare_op1);
       operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
     }
-}")
+})
 
 (define_expand "movsicc"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -3608,7 +3531,6 @@
 			 (match_operand:SI 2 "arith10_operand" "")
 			 (match_operand:SI 3 "arith10_operand" "")))]
   "TARGET_V9"
-  "
 {
   enum rtx_code code = GET_CODE (operands[1]);
   enum machine_mode op0_mode = GET_MODE (sparc_compare_op0);
@@ -3627,7 +3549,7 @@
       operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
 				    cc_reg, const0_rtx);
     }
-}")
+})
 
 (define_expand "movdicc"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -3635,7 +3557,6 @@
 			 (match_operand:DI 2 "arith10_double_operand" "")
 			 (match_operand:DI 3 "arith10_double_operand" "")))]
   "TARGET_ARCH64"
-  "
 {
   enum rtx_code code = GET_CODE (operands[1]);
 
@@ -3654,7 +3575,7 @@
       operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
 				    cc_reg, const0_rtx);
     }
-}")
+})
 
 (define_expand "movsfcc"
   [(set (match_operand:SF 0 "register_operand" "")
@@ -3662,7 +3583,6 @@
 			 (match_operand:SF 2 "register_operand" "")
 			 (match_operand:SF 3 "register_operand" "")))]
   "TARGET_V9 && TARGET_FPU"
-  "
 {
   enum rtx_code code = GET_CODE (operands[1]);
 
@@ -3684,7 +3604,7 @@
 				    sparc_compare_op0, sparc_compare_op1);
       operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
     }
-}")
+})
 
 (define_expand "movdfcc"
   [(set (match_operand:DF 0 "register_operand" "")
@@ -3692,7 +3612,6 @@
 			 (match_operand:DF 2 "register_operand" "")
 			 (match_operand:DF 3 "register_operand" "")))]
   "TARGET_V9 && TARGET_FPU"
-  "
 {
   enum rtx_code code = GET_CODE (operands[1]);
 
@@ -3714,7 +3633,7 @@
 				    sparc_compare_op0, sparc_compare_op1);
       operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
     }
-}")
+})
 
 (define_expand "movtfcc"
   [(set (match_operand:TF 0 "register_operand" "")
@@ -3722,7 +3641,6 @@
 			 (match_operand:TF 2 "register_operand" "")
 			 (match_operand:TF 3 "register_operand" "")))]
   "TARGET_V9 && TARGET_FPU"
-  "
 {
   enum rtx_code code = GET_CODE (operands[1]);
 
@@ -3744,7 +3662,7 @@
 				    sparc_compare_op0, sparc_compare_op1);
       operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
     }
-}")
+})
 
 ;; Conditional move define_insns.
 
@@ -3865,7 +3783,6 @@
   "#"
   "&& reload_completed"
   [(clobber (const_int 0))]
-  "
 {
   rtx set_dest = operands[0];
   rtx set_srca = operands[3];
@@ -3895,7 +3812,7 @@
       emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
     }
   DONE;
-}"
+}
   [(set_attr "length" "2")])
 
 (define_insn "*movqi_cc_reg_sp64"
@@ -4015,7 +3932,6 @@
   "#"
   "&& reload_completed"
   [(clobber (const_int 0))]
-  "
 {
   rtx set_dest = operands[0];
   rtx set_srca = operands[3];
@@ -4045,7 +3961,7 @@
       emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
     }
   DONE;
-}"
+}
   [(set_attr "length" "2")])
 
 
@@ -4059,7 +3975,6 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
   ""
-  "
 {
   rtx temp = gen_reg_rtx (SImode);
   rtx shift_16 = GEN_INT (16);
@@ -4077,7 +3992,7 @@
 			  shift_16));
   emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
   DONE;
-}")
+})
 
 (define_insn "*zero_extendhisi2_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -4139,7 +4054,6 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
   "TARGET_ARCH64"
-  "
 {
   rtx temp = gen_reg_rtx (DImode);
   rtx shift_48 = GEN_INT (48);
@@ -4157,7 +4071,7 @@
 			  shift_48));
   emit_insn (gen_lshrdi3 (operand0, temp, shift_48));
   DONE;
-}")
+})
 
 (define_insn "*zero_extendhidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -4193,7 +4107,6 @@
   "&& reload_completed"
   [(set (match_dup 2) (match_dup 3))
    (set (match_dup 4) (match_dup 5))]
-  "
 {
   rtx dest1, dest2;
 
@@ -4215,7 +4128,7 @@
       operands[4] = dest2;
       operands[5] = operands[1];
     }
-}"
+}
   [(set_attr "length" "2")])
 
 ;; Simplify comparisons of extended values.
@@ -4342,7 +4255,6 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
   ""
-  "
 {
   rtx temp = gen_reg_rtx (SImode);
   rtx shift_16 = GEN_INT (16);
@@ -4360,7 +4272,7 @@
 			  shift_16));
   emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
   DONE;
-}")
+})
 
 (define_insn "*sign_extendhisi2_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -4374,7 +4286,6 @@
   [(set (match_operand:HI 0 "register_operand" "")
 	(sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
   ""
-  "
 {
   rtx temp = gen_reg_rtx (SImode);
   rtx shift_24 = GEN_INT (24);
@@ -4401,7 +4312,7 @@
     operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subbyte);
   emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
   DONE;
-}")
+})
 
 (define_insn "*sign_extendqihi2_insn"
   [(set (match_operand:HI 0 "register_operand" "=r")
@@ -4415,7 +4326,6 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
   ""
-  "
 {
   rtx temp = gen_reg_rtx (SImode);
   rtx shift_24 = GEN_INT (24);
@@ -4433,7 +4343,7 @@
 			  shift_24));
   emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
   DONE;
-}")
+})
 
 (define_insn "*sign_extendqisi2_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -4447,7 +4357,6 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
   "TARGET_ARCH64"
-  "
 {
   rtx temp = gen_reg_rtx (DImode);
   rtx shift_56 = GEN_INT (56);
@@ -4465,7 +4374,7 @@
 			  shift_56));
   emit_insn (gen_ashrdi3 (operand0, temp, shift_56));
   DONE;
-}")
+})
 
 (define_insn "*sign_extendqidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -4479,7 +4388,6 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
   "TARGET_ARCH64"
-  "
 {
   rtx temp = gen_reg_rtx (DImode);
   rtx shift_48 = GEN_INT (48);
@@ -4497,7 +4405,7 @@
 			  shift_48));
   emit_insn (gen_ashrdi3 (operand0, temp, shift_48));
   DONE;
-}")
+})
 
 (define_insn "*sign_extendhidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -4537,7 +4445,6 @@
     && INTVAL (operands[2]) > 19)
    || (GET_CODE (operands[2]) == CONST_DOUBLE
        && CONST_DOUBLE_LOW (operands[2]) > 19)"
-  "*
 {
   int len = (GET_CODE (operands[1]) == CONST_INT
              ? INTVAL (operands[1])
@@ -4549,8 +4456,8 @@
   HOST_WIDE_INT mask = ((1 << len) - 1) << pos;
 
   operands[1] = GEN_INT (mask);
-  return \"andcc\\t%0, %1, %%g0\";
-}"
+  return "andcc\\t%0, %1, %%g0";
+}
   [(set_attr "type" "compare")])
 
 (define_insn "*cmp_zero_extract_sp64"
@@ -4565,7 +4472,6 @@
         && INTVAL (operands[2]) > 51)
        || (GET_CODE (operands[2]) == CONST_DOUBLE
            && CONST_DOUBLE_LOW (operands[2]) > 51))"
-  "*
 {
   int len = (GET_CODE (operands[1]) == CONST_INT
              ? INTVAL (operands[1])
@@ -4577,8 +4483,8 @@
   HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
 
   operands[1] = GEN_INT (mask);
-  return \"andcc\\t%0, %1, %%g0\";
-}"
+  return "andcc\\t%0, %1, %%g0";
+}
   [(set_attr "type" "compare")])
 
 ;; Conversions between float, double and long double.
@@ -4829,7 +4735,6 @@
 	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		 (match_operand:DI 2 "arith_double_add_operand" "rHI")))]
   ""
-  "
 {
   HOST_WIDE_INT i;
 
@@ -4858,7 +4763,7 @@
       emit_insn (gen_movdi (operands[0], GEN_INT (i + 4096)));
       DONE;
     }
-}")
+})
 
 (define_insn_and_split "adddi3_insn_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -4878,7 +4783,6 @@
 	(plus:SI (plus:SI (match_dup 7)
 			  (match_dup 8))
 		 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
-  "
 {
   operands[3] = gen_lowpart (SImode, operands[0]);
   operands[4] = gen_lowpart (SImode, operands[1]);
@@ -4896,7 +4800,7 @@
   else
 #endif
     operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
-}"
+}
   [(set_attr "length" "2")])
 
 (define_split
@@ -4915,7 +4819,6 @@
 	(minus:SI (minus:SI (match_dup 7)
 			    (match_dup 8))
 		  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
-  "
 {
   operands[3] = gen_lowpart (SImode, operands[0]);
   operands[4] = gen_lowpart (SImode, operands[1]);
@@ -4933,7 +4836,7 @@
   else
 #endif
     operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
-}")
+})
 
 ;; LTU here means "carry set"
 (define_insn "addx"
@@ -5036,7 +4939,6 @@
 	(plus:SI (match_operand:SI 1 "arith_operand" "%r,d")
 		 (match_operand:SI 2 "arith_add_operand" "rI,d")))]
   ""
-  "
 {
   if (arith_4096_operand(operands[2], SImode))
     {
@@ -5049,7 +4951,7 @@
 					       GEN_INT(-4096))));
       DONE;
     }
-}")
+})
 
 (define_insn "*addsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -5106,7 +5008,6 @@
 	(minus:DI (match_operand:DI 1 "register_operand" "r")
 		  (match_operand:DI 2 "arith_double_add_operand" "rHI")))]
   ""
-  "
 {
   if (! TARGET_ARCH64)
     {
@@ -5125,7 +5026,7 @@
 					    GEN_INT(-4096))));
       DONE;
     }
-}")
+})
 
 (define_insn_and_split "*subdi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -5138,7 +5039,6 @@
    && (GET_CODE (operands[2]) == CONST_INT
        || GET_CODE (operands[2]) == CONST_DOUBLE)"
   [(clobber (const_int 0))]
-  "
 {
   rtx highp, lowp;
 
@@ -5164,7 +5064,7 @@
                            highp));
     }
   DONE;
-}"
+}
   [(set_attr "length" "2")])
 
 (define_split
@@ -5175,7 +5075,6 @@
   "! TARGET_ARCH64
    && reload_completed"
   [(clobber (const_int 0))]
-  "
 {
   emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]),
                                    gen_lowpart (SImode, operands[1]),
@@ -5184,7 +5083,7 @@
                        gen_highpart (SImode, operands[1]),
                        gen_highpart (SImode, operands[2])));
   DONE;
-}")
+})
 
 (define_insn_and_split ""
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -5219,7 +5118,6 @@
 	(minus:SI (match_operand:SI 1 "register_operand" "r,d")
 		  (match_operand:SI 2 "arith_add_operand" "rI,d")))]
   ""
-  "
 {
   if (arith_4096_operand(operands[2], SImode))
     {
@@ -5228,7 +5126,7 @@
 					    GEN_INT(-4096))));
       DONE;
     }
-}")
+})
 
 (define_insn "*subsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -5298,14 +5196,13 @@
 	(mult:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
   "TARGET_ARCH64 || TARGET_V8PLUS"
-  "
 {
   if (TARGET_V8PLUS)
     {
       emit_insn (gen_muldi3_v8plus (operands[0], operands[1], operands[2]));
       DONE;
     }
-}")
+})
 
 (define_insn "*muldi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -5324,33 +5221,32 @@
    (clobber (match_scratch:SI 3 "=&h,X"))
    (clobber (match_scratch:SI 4 "=&h,X"))]
   "TARGET_V8PLUS"
-  "*
 {
   if (sparc_check_64 (operands[1], insn) <= 0)
-    output_asm_insn (\"srl\\t%L1, 0, %L1\", operands);
+    output_asm_insn ("srl\\t%L1, 0, %L1", operands);
   if (which_alternative == 1)
-    output_asm_insn (\"sllx\\t%H1, 32, %H1\", operands);
+    output_asm_insn ("sllx\\t%H1, 32, %H1", operands);
   if (GET_CODE (operands[2]) == CONST_INT)
     {
       if (which_alternative == 1)
-	return \"or\\t%L1, %H1, %H1\\n\\tmulx\\t%H1, %2, %L0\;srlx\\t%L0, 32, %H0\";
+	return "or\\t%L1, %H1, %H1\\n\\tmulx\\t%H1, %2, %L0\;srlx\\t%L0, 32, %H0";
       else
-	return \"sllx\\t%H1, 32, %3\\n\\tor\\t%L1, %3, %3\\n\\tmulx\\t%3, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\";
+	return "sllx\\t%H1, 32, %3\\n\\tor\\t%L1, %3, %3\\n\\tmulx\\t%3, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0";
     }
   else if (rtx_equal_p (operands[1], operands[2]))
     {
       if (which_alternative == 1)
-	return \"or\\t%L1, %H1, %H1\\n\\tmulx\\t%H1, %H1, %L0\;srlx\\t%L0, 32, %H0\";
+	return "or\\t%L1, %H1, %H1\\n\\tmulx\\t%H1, %H1, %L0\;srlx\\t%L0, 32, %H0";
       else
-	return \"sllx\\t%H1, 32, %3\\n\\tor\\t%L1, %3, %3\\n\\tmulx\\t%3, %3, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\";
+	return "sllx\\t%H1, 32, %3\\n\\tor\\t%L1, %3, %3\\n\\tmulx\\t%3, %3, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0";
     }
   if (sparc_check_64 (operands[2], insn) <= 0)
-    output_asm_insn (\"srl\\t%L2, 0, %L2\", operands);
+    output_asm_insn ("srl\\t%L2, 0, %L2", operands);
   if (which_alternative == 1)
-    return \"or\\t%L1, %H1, %H1\\n\\tsllx\\t%H2, 32, %L1\\n\\tor\\t%L2, %L1, %L1\\n\\tmulx\\t%H1, %L1, %L0\;srlx\\t%L0, 32, %H0\";
+    return "or\\t%L1, %H1, %H1\\n\\tsllx\\t%H2, 32, %L1\\n\\tor\\t%L2, %L1, %L1\\n\\tmulx\\t%H1, %L1, %L0\;srlx\\t%L0, 32, %H0";
   else
-    return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\";
-}"
+    return "sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0";
+}
   [(set_attr "type" "multi")
    (set_attr "length" "9,8")])
 
@@ -5370,7 +5266,6 @@
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
 		 (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))))]
   "TARGET_HARD_MUL"
-  "
 {
   if (CONSTANT_P (operands[2]))
     {
@@ -5387,7 +5282,7 @@
       emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2]));
       DONE;
     }
-}")
+})
 
 ;; V9 puts the 64 bit product in a 64 bit register.  Only out or global
 ;; registers can hold 64 bit values in the V8plus environment.
@@ -5423,10 +5318,11 @@
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
   "TARGET_HARD_MUL32"
-  "*
 {
-  return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
-}"
+  return TARGET_SPARCLET
+         ? "smuld\\t%1, %2, %L0"
+         : "smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0";
+}
   [(set (attr "type")
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_string "imul") (const_string "multi")))
@@ -5450,10 +5346,11 @@
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (match_operand:SI 2 "small_int" "I")))]
   "TARGET_HARD_MUL32"
-  "*
 {
-  return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
-}"
+  return TARGET_SPARCLET
+         ? "smuld\\t%1, %2, %L0"
+         : "smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0";
+}
   [(set (attr "type")
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_string "imul") (const_string "multi")))
@@ -5476,7 +5373,6 @@
 			       (sign_extend:DI (match_operand:SI 2 "arith_operand" "")))
 		      (const_int 32))))]
   "TARGET_HARD_MUL && TARGET_ARCH32"
-  "
 {
   if (CONSTANT_P (operands[2]))
     {
@@ -5497,7 +5393,7 @@
 					      operands[2], GEN_INT (32)));
       DONE;
     }
-}")
+})
 
 ;; XXX
 (define_insn "smulsi3_highpart_v8plus"
@@ -5576,7 +5472,6 @@
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
 		 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))]
   "TARGET_HARD_MUL"
-  "
 {
   if (CONSTANT_P (operands[2]))
     {
@@ -5593,7 +5488,7 @@
       emit_insn (gen_umulsidi3_v8plus (operands[0], operands[1], operands[2]));
       DONE;
     }
-}")
+})
 
 ;; XXX
 (define_insn "umulsidi3_v8plus"
@@ -5614,10 +5509,11 @@
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
   "TARGET_HARD_MUL32"
-  "*
 {
-  return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
-}"
+  return TARGET_SPARCLET
+         ? "umuld\\t%1, %2, %L0"
+         : "umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0";
+}
   [(set (attr "type")
         (if_then_else (eq_attr "isa" "sparclet")
                       (const_string "imul") (const_string "multi")))
@@ -5641,10 +5537,11 @@
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (match_operand:SI 2 "uns_small_int" "")))]
   "TARGET_HARD_MUL32"
-  "*
 {
-  return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
-}"
+  return TARGET_SPARCLET
+         ? "umuld\\t%1, %2, %L0"
+         : "umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0";
+}
   [(set (attr "type")
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_string "imul") (const_string "multi")))
@@ -5680,7 +5577,6 @@
 			       (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" "")))
 		      (const_int 32))))]
   "TARGET_HARD_MUL && TARGET_ARCH32"
-  "
 {
   if (CONSTANT_P (operands[2]))
     {
@@ -5701,7 +5597,7 @@
 					      operands[2], GEN_INT (32)));
       DONE;
     }
-}")
+})
 
 ;; XXX
 (define_insn "umulsi3_highpart_v8plus"
@@ -5766,7 +5662,6 @@
 			   (match_operand:SI 2 "input_operand" "rI,m")))
 	      (clobber (match_scratch:SI 3 "=&r,&r"))])]
   "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
-  "
 {
   if (TARGET_ARCH64)
     {
@@ -5776,7 +5671,7 @@
 				  operands[3]));
       DONE;
     }
-}")
+})
 
 (define_insn "divsi3_sp32"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -5785,19 +5680,18 @@
    (clobber (match_scratch:SI 3 "=&r,&r"))]
   "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS)
    && TARGET_ARCH32"
-  "*
 {
   if (which_alternative == 0)
     if (TARGET_V9)
-      return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdiv\\t%1, %2, %0\";
+      return "sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdiv\\t%1, %2, %0";
     else
-      return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %2, %0\";
+      return "sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %2, %0";
   else
     if (TARGET_V9)
-      return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tsdiv\\t%1, %3, %0\";
+      return "sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tsdiv\\t%1, %3, %0";
     else
-      return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\";
-}"
+      return "sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0";
+}
   [(set_attr "type" "multi")
    (set (attr "length")
 	(if_then_else (eq_attr "isa" "v9")
@@ -5830,13 +5724,12 @@
 	(div:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 3 "=&r"))]
   "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
-  "*
 {
   if (TARGET_V9)
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdivcc\\t%1, %2, %0\";
+    return "sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdivcc\\t%1, %2, %0";
   else
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\";
-}"
+    return "sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0";
+}
   [(set_attr "type" "multi")
    (set (attr "length")
 	(if_then_else (eq_attr "isa" "v9")
@@ -5857,19 +5750,18 @@
   "(TARGET_V8
     || TARGET_DEPRECATED_V8_INSNS)
    && TARGET_ARCH32"
-  "*
 {
-  output_asm_insn (\"wr\\t%%g0, %%g0, %%y\", operands);
+  output_asm_insn ("wr\\t%%g0, %%g0, %%y", operands);
   switch (which_alternative)
     {
     default:
-      return \"nop\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %2, %0\";
+      return "nop\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %2, %0";
     case 1:
-      return \"ld\\t%2, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %0, %0\";
+      return "ld\\t%2, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %0, %0";
     case 2:
-      return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\";
+      return "ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0";
     }
-}"
+}
   [(set_attr "type" "multi")
    (set_attr "length" "5")])
 
@@ -5899,13 +5791,12 @@
 	(udiv:SI (match_dup 1) (match_dup 2)))]
   "TARGET_V8
    || TARGET_DEPRECATED_V8_INSNS"
-  "*
 {
   if (TARGET_V9)
-    return \"wr\\t%%g0, %%g0, %%y\\n\\tudivcc\\t%1, %2, %0\";
+    return "wr\\t%%g0, %%g0, %%y\\n\\tudivcc\\t%1, %2, %0";
   else
-    return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\";
-}"
+    return "wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0";
+}
   [(set_attr "type" "multi")
    (set (attr "length")
 	(if_then_else (eq_attr "isa" "v9")
@@ -5998,10 +5889,9 @@
    && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
   [(set (match_dup 3) (match_dup 4))
    (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
-  "
 {
   operands[4] = GEN_INT (~INTVAL (operands[2]));
-}")
+})
 
 ;; Split DImode logical operations requiring two instructions.
 (define_split
@@ -6018,7 +5908,6 @@
            && REGNO (SUBREG_REG (operands[0])) < 32))"
   [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)]))
    (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
-  "
 {
   operands[4] = gen_highpart (SImode, operands[0]);
   operands[5] = gen_lowpart (SImode, operands[0]);
@@ -6036,7 +5925,7 @@
 #endif
     operands[8] = gen_highpart_mode (SImode, DImode, operands[3]);
   operands[9] = gen_lowpart (SImode, operands[3]);
-}")
+})
 
 (define_insn_and_split "*and_not_di_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r,b")
@@ -6135,10 +6024,9 @@
    && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
   [(set (match_dup 3) (match_dup 4))
    (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
-  "
 {
   operands[4] = GEN_INT (~INTVAL (operands[2]));
-}")
+})
 
 (define_insn_and_split "*or_not_di_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r,b")
@@ -6245,10 +6133,9 @@
    && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
   [(set (match_dup 3) (match_dup 4))
    (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
-  "
 {
   operands[4] = GEN_INT (~INTVAL (operands[2]));
-}")
+})
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -6260,10 +6147,9 @@
    && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
   [(set (match_dup 3) (match_dup 4))
    (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
-  "
 {
   operands[4] = GEN_INT (~INTVAL (operands[2]));
-}")
+})
 
 ;; xnor patterns.  Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).
 ;; Combine now canonicalizes to the rightmost expression.
@@ -6466,7 +6352,6 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(neg:DI (match_operand:DI 1 "register_operand" "r")))]
   ""
-  "
 {
   if (! TARGET_ARCH64)
     {
@@ -6480,7 +6365,7 @@
 							   SPARC_ICC_REG)))));
       DONE;
     }
-}")
+})
 
 (define_insn_and_split "*negdi2_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -7022,12 +6907,11 @@
 	(ashift:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:SI 2 "arith_operand" "rI")))]
   ""
-  "*
 {
   if (operands[2] == const1_rtx)
-    return \"add\\t%1, %1, %0\";
-  return \"sll\\t%1, %2, %0\";
-}"
+    return "add\\t%1, %1, %0";
+  return "sll\\t%1, %2, %0";
+}
   [(set (attr "type")
 	(if_then_else (match_operand 2 "const1_operand" "")
 		      (const_string "ialu") (const_string "shift")))])
@@ -7037,7 +6921,6 @@
 	(ashift:DI (match_operand:DI 1 "register_operand" "r")
 		   (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64 || TARGET_V8PLUS"
-  "
 {
   if (! TARGET_ARCH64)
     {
@@ -7046,19 +6929,18 @@
       emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2]));
       DONE;
     }
-}")
+})
 
 (define_insn "*ashldi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (match_operand:DI 1 "register_operand" "r")
 		   (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64"
-  "*
 {
   if (operands[2] == const1_rtx)
-    return \"add\\t%1, %1, %0\";
-  return \"sllx\\t%1, %2, %0\";
-}"
+    return "add\\t%1, %1, %0";
+  return "sllx\\t%1, %2, %0";
+}
   [(set (attr "type")
 	(if_then_else (match_operand 2 "const1_operand" "")
 		      (const_string "ialu") (const_string "shift")))])
@@ -7070,7 +6952,7 @@
 		   (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
    (clobber (match_scratch:SI 3 "=X,X,&h"))]
   "TARGET_V8PLUS"
-  "*return sparc_v8plus_shift (operands, insn, \"sllx\");"
+  { return sparc_v8plus_shift (operands, insn, "sllx"); }
   [(set_attr "type" "multi")
    (set_attr "length" "5,5,6")])
 
@@ -7083,12 +6965,11 @@
 ;			    (match_operand:SI 1 "arith_operand" "rI"))
 ;		 (const_int -1)))]
 ;  "0 && TARGET_V8PLUS"
-;  "*
 ;{
 ;  if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0]))
-;    return \"mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
-;  return \"mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
-;}"
+;    return "mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0";
+;  return "mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0";
+;}
 ;  [(set_attr "type" "multi")
 ;   (set_attr "length" "4")])
 
@@ -7117,10 +6998,7 @@
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   ""
-  "*
-{
-  return \"sra\\t%1, %2, %0\";
-}"
+  "sra\\t%1, %2, %0"
   [(set_attr "type" "shift")])
 
 (define_insn "*ashrsi3_extend"
@@ -7145,12 +7023,11 @@
 	   && !CONST_DOUBLE_HIGH (operands[2])
            && CONST_DOUBLE_LOW (operands[2]) >= 32
            && CONST_DOUBLE_LOW (operands[2]) < 64))"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
 
-  return \"sra\\t%1, %2, %0\";
-}"
+  return "sra\\t%1, %2, %0";
+}
   [(set_attr "type" "shift")])
 
 (define_expand "ashrdi3"
@@ -7158,7 +7035,6 @@
 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64 || TARGET_V8PLUS"
-  "
 {
   if (! TARGET_ARCH64)
     {
@@ -7167,17 +7043,14 @@
       emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2]));
       DONE;
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64"
-  "*
-{
-  return \"srax\\t%1, %2, %0\";
-}"
+  "srax\\t%1, %2, %0"
   [(set_attr "type" "shift")])
 
 ;; XXX
@@ -7187,7 +7060,7 @@
 		     (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
    (clobber (match_scratch:SI 3 "=X,X,&h"))]
   "TARGET_V8PLUS"
-  "*return sparc_v8plus_shift (operands, insn, \"srax\");"
+  { return sparc_v8plus_shift (operands, insn, "srax"); }
   [(set_attr "type" "multi")
    (set_attr "length" "5,5,6")])
 
@@ -7196,10 +7069,7 @@
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   ""
-  "*
-{
-  return \"srl\\t%1, %2, %0\";
-}"
+  "srl\\t%1, %2, %0"
   [(set_attr "type" "shift")])
 
 ;; This handles the case where
@@ -7234,12 +7104,11 @@
        || (GET_CODE (operands[2]) == CONST_DOUBLE
 	   && CONST_DOUBLE_HIGH (operands[2]) == 0
            && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
-  "*
 {
   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
 
-  return \"srl\\t%1, %2, %0\";
-}"
+  return "srl\\t%1, %2, %0";
+}
   [(set_attr "type" "shift")])
 
 (define_expand "lshrdi3"
@@ -7247,7 +7116,6 @@
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64 || TARGET_V8PLUS"
-  "
 {
   if (! TARGET_ARCH64)
     {
@@ -7256,17 +7124,14 @@
       emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2]));
       DONE;
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64"
-  "*
-{
-  return \"srlx\\t%1, %2, %0\";
-}"
+  "srlx\\t%1, %2, %0"
   [(set_attr "type" "shift")])
 
 ;; XXX
@@ -7276,7 +7141,7 @@
 		     (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
    (clobber (match_scratch:SI 3 "=X,X,&h"))]
   "TARGET_V8PLUS"
-  "*return sparc_v8plus_shift (operands, insn, \"srlx\");"
+  { return sparc_v8plus_shift (operands, insn, "srlx"); }
   [(set_attr "type" "multi")
    (set_attr "length" "5,5,6")])
 
@@ -7291,12 +7156,11 @@
        || (GET_CODE (operands[2]) == CONST_DOUBLE
 	   && !CONST_DOUBLE_HIGH (operands[2])
            && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
 
-  return \"srax\\t%1, %2, %0\";
-}"
+  return "srax\\t%1, %2, %0";
+}
   [(set_attr "type" "shift")])
 
 (define_insn ""
@@ -7310,12 +7174,11 @@
        || (GET_CODE (operands[2]) == CONST_DOUBLE
 	   && !CONST_DOUBLE_HIGH (operands[2])
            && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
 
-  return \"srlx\\t%1, %2, %0\";
-}"
+  return "srlx\\t%1, %2, %0";
+}
   [(set_attr "type" "shift")])
 
 (define_insn ""
@@ -7328,12 +7191,11 @@
    && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
    && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
    && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
 
-  return \"srax\\t%1, %2, %0\";
-}"
+  return "srax\\t%1, %2, %0";
+}
   [(set_attr "type" "shift")])
 
 (define_insn ""
@@ -7346,12 +7208,11 @@
    && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
    && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
    && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
 
-  return \"srlx\\t%1, %2, %0\";
-}"
+  return "srlx\\t%1, %2, %0";
+}
   [(set_attr "type" "shift")])
 
 ;; Unconditional and other jump instructions
@@ -7361,7 +7222,6 @@
 (define_insn "jump"
   [(set (pc) (label_ref (match_operand 0 "" "")))]
   ""
-  "*
 {
   /* TurboSparc is reported to have problems with
      with
@@ -7373,17 +7233,16 @@
   if (! TARGET_V9 && flag_delayed_branch
       && (INSN_ADDRESSES (INSN_UID (operands[0]))
 	  == INSN_ADDRESSES (INSN_UID (insn))))
-    return \"b\\t%l0%#\";
+    return "b\\t%l0%#";
   else
-    return TARGET_V9 ? \"ba,pt%*\\t%%xcc, %l0%(\" : \"b%*\\t%l0%(\";
-}"
+    return TARGET_V9 ? "ba,pt%*\\t%%xcc, %l0%(" : "b%*\\t%l0%(";
+}
   [(set_attr "type" "uncond_branch")])
 
 (define_expand "tablejump"
   [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
 	      (use (label_ref (match_operand 1 "" "")))])]
   ""
-  "
 {
   if (GET_MODE (operands[0]) != CASE_VECTOR_MODE)
     abort ();
@@ -7401,7 +7260,7 @@
       tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
       operands[0] = memory_address (Pmode, tmp);
     }
-}")
+})
 
 (define_insn "*tablejump_sp32"
   [(set (pc) (match_operand:SI 0 "address_operand" "p"))
@@ -7435,7 +7294,6 @@
   ;; operands[2] is next_arg_register
   ;; operands[3] is struct_value_size_rtx.
   ""
-  "
 {
   rtx fn_rtx, nregs_rtx;
 
@@ -7509,7 +7367,7 @@
 #endif
 
   DONE;
-}")
+})
 
 ;; We can't use the same pattern for these two insns, because then registers
 ;; in the address may not be properly reloaded.
@@ -7610,7 +7468,6 @@
   ;; operand 2 is stack_size_rtx
   ;; operand 3 is next_arg_register
   ""
-  "
 {
   rtx fn_rtx, nregs_rtx;
   rtvec vec;
@@ -7637,7 +7494,7 @@
   emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec));
 
   DONE;
-}")
+})
 
 (define_insn "*call_value_address_sp32"
   [(set (match_operand 0 "" "=rf")
@@ -7685,7 +7542,6 @@
 	      (match_operand 1 "" "")
 	      (match_operand 2 "" "")])]
   ""
-  "
 {
   int i;
 
@@ -7706,7 +7562,7 @@
   emit_insn (gen_blockage ());
 
   DONE;
-}")
+})
 
 ;;- tail calls
 (define_expand "sibcall"
@@ -7776,7 +7632,6 @@
   [(match_operand:BLK 0 "memory_operand" "")
    (match_operand 1 "" "")]
   ""
-  "
 {
   rtx valreg1 = gen_rtx_REG (DImode, 24);
   rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
@@ -7810,7 +7665,7 @@
   expand_null_return ();
 
   DONE;
-}")
+})
 
 ;; This is a bit of a hack.  We're incrementing a fixed register (%i7),
 ;; and parts of the compiler don't want to believe that the add is needed.
@@ -7852,7 +7707,6 @@
    (match_operand:SI 2 "general_operand" "")
    (match_operand:SI 3 "" "")]
   ""
-  "
 {
 #if 0
   rtx chain = operands[0];
@@ -7906,13 +7760,13 @@
   emit_jump_insn (gen_goto_handler_and_restore (labreg));
   emit_barrier ();
   DONE;
-}")
+})
 
 ;; Special trap insn to flush register windows.
 (define_insn "flush_register_windows"
   [(unspec_volatile [(const_int 0)] UNSPECV_FLUSHW)]
   ""
-  "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";"
+  { return TARGET_V9 ? "flushw" : "ta\\t3"; }
   [(set_attr "type" "flushw")])
 
 (define_insn "goto_handler_and_restore"
@@ -7950,34 +7804,32 @@
 (define_expand "builtin_setjmp_setup"
   [(match_operand 0 "register_operand" "r")]
   ""
-  "
 {
   emit_insn (gen_do_builtin_setjmp_setup ());
   DONE;
-}")
+})
 
 (define_insn "do_builtin_setjmp_setup"
   [(unspec_volatile [(const_int 0)] UNSPECV_SETJMP)]
   ""
-  "*
 {
   if (! current_function_calls_alloca)
-    return \"\";
+    return "";
   if (! TARGET_V9 || TARGET_FLAT)
-    return \"\tta\t3\n\";
-  fputs (\"\tflushw\n\", asm_out_file);
+    return "\tta\t3\n";
+  fputs ("\tflushw\n", asm_out_file);
   if (flag_pic)
-    fprintf (asm_out_file, \"\tst%c\t%%l7, [%%sp+%d]\n\",
+    fprintf (asm_out_file, "\tst%c\t%%l7, [%%sp+%d]\n",
 	     TARGET_ARCH64 ? 'x' : 'w',
 	     SPARC_STACK_BIAS + 7 * UNITS_PER_WORD);
-  fprintf (asm_out_file, \"\tst%c\t%%fp, [%%sp+%d]\n\",
+  fprintf (asm_out_file, "\tst%c\t%%fp, [%%sp+%d]\n",
 	   TARGET_ARCH64 ? 'x' : 'w',
 	   SPARC_STACK_BIAS + 14 * UNITS_PER_WORD);
-  fprintf (asm_out_file, \"\tst%c\t%%i7, [%%sp+%d]\n\",
+  fprintf (asm_out_file, "\tst%c\t%%i7, [%%sp+%d]\n",
 	   TARGET_ARCH64 ? 'x' : 'w',
 	   SPARC_STACK_BIAS + 15 * UNITS_PER_WORD);
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type" "multi")
    (set (attr "length")
         (cond [(eq_attr "current_function_calls_alloca" "false")
@@ -7995,28 +7847,25 @@
 (define_expand "setjmp"
   [(const_int 0)]
   ""
-  "
 {
   if (TARGET_ARCH64)
     emit_insn (gen_setjmp_64 ());
   else
     emit_insn (gen_setjmp_32 ());
   DONE;
-}")
+})
 
 (define_expand "setjmp_32"
   [(set (mem:SI (plus:SI (reg:SI 14) (const_int 56))) (match_dup 0))
    (set (mem:SI (plus:SI (reg:SI 14) (const_int 60))) (reg:SI 31))]
   ""
-  "
-{ operands[0] = frame_pointer_rtx; }")
+  { operands[0] = frame_pointer_rtx; })
 
 (define_expand "setjmp_64"
   [(set (mem:DI (plus:DI (reg:DI 14) (const_int 112))) (match_dup 0))
    (set (mem:DI (plus:DI (reg:DI 14) (const_int 120))) (reg:DI 31))]
   ""
-  "
-{ operands[0] = frame_pointer_rtx; }")
+  { operands[0] = frame_pointer_rtx; })
 
 ;; Special pattern for the FLUSH instruction.
 
@@ -8028,13 +7877,13 @@
 (define_insn "flush"
   [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
   ""
-  "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";"
+  { return TARGET_V9 ? "flush\\t%f0" : "iflush\\t%f0"; }
   [(set_attr "type" "iflush")])
 
 (define_insn "flushdi"
   [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
   ""
-  "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";"
+  { return TARGET_V9 ? "flush\\t%f0" : "iflush\\t%f0"; }
   [(set_attr "type" "iflush")])
 
 
@@ -8051,10 +7900,9 @@
 	(ffs:SI (match_operand:SI 1 "register_operand" "r")))
    (clobber (match_scratch:SI 2 "=&r"))]
   "TARGET_SPARCLITE || TARGET_SPARCLET"
-  "*
 {
-  return \"sub\\t%%g0, %1, %0\;and\\t%0, %1, %0\;scan\\t%0, 0, %0\;mov\\t32, %2\;sub\\t%2, %0, %0\;sra\\t%0, 31, %2\;and\\t%2, 31, %2\;add\\t%2, %0, %0\";
-}"
+  return "sub\\t%%g0, %1, %0\;and\\t%0, %1, %0\;scan\\t%0, 0, %0\;mov\\t32, %2\;sub\\t%2, %0, %0\;sra\\t%0, 31, %2\;and\\t%2, 31, %2\;add\\t%2, %0, %0";
+}
   [(set_attr "type" "multi")
    (set_attr "length" "8")])
 
@@ -8243,16 +8091,15 @@
 	(match_operand:QI 1 "arith_operand" "rI"))
    (return)]
   "sparc_emitting_epilogue"
-  "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\";
+    return "jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0";
   else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
 			 || IN_OR_GLOBAL_P (operands[1])))
-    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
+    return "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0";
   else
-    return \"ret\\n\\trestore %%g0, %1, %Y0\";
-}"
+    return "ret\\n\\trestore %%g0, %1, %Y0";
+}
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
@@ -8261,16 +8108,15 @@
 	(match_operand:HI 1 "arith_operand" "rI"))
    (return)]
   "sparc_emitting_epilogue"
-  "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\";
+    return "jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0";
   else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
 			 || IN_OR_GLOBAL_P (operands[1])))
-    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
+    return "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0";
   else
-    return \"ret\;restore %%g0, %1, %Y0\";
-}"
+    return "ret\;restore %%g0, %1, %Y0";
+}
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
@@ -8279,16 +8125,15 @@
 	(match_operand:SI 1 "arith_operand" "rI"))
    (return)]
   "sparc_emitting_epilogue"
-  "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\";
+    return "jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0";
   else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
 			 || IN_OR_GLOBAL_P (operands[1])))
-    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
+    return "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0";
   else
-    return \"ret\;restore %%g0, %1, %Y0\";
-}"
+    return "ret\;restore %%g0, %1, %Y0";
+}
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
@@ -8297,15 +8142,14 @@
 	(match_operand:SF 1 "register_operand" "r"))
    (return)]
   "sparc_emitting_epilogue"
-  "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\";
+    return "jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0";
   else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]))
-    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
+    return "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0";
   else
-    return \"ret\;restore %%g0, %1, %Y0\";
-}"
+    return "ret\;restore %%g0, %1, %Y0";
+}
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
@@ -8314,13 +8158,12 @@
 	(match_operand:DF 1 "register_operand" "r"))
    (return)]
   "sparc_emitting_epilogue && TARGET_ARCH64"
-  "*
 {
   if (IN_OR_GLOBAL_P (operands[1]))
-    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
+    return "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0";
   else
-    return \"ret\;restore %%g0, %1, %Y0\";
-}"
+    return "ret\;restore %%g0, %1, %Y0";
+}
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
@@ -8330,18 +8173,17 @@
 		 (match_operand:SI 2 "arith_operand" "rI")))
    (return)]
   "sparc_emitting_epilogue"
-  "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %r1, %2, %Y0\";
+    return "jmp\\t%%i7+12\\n\\trestore %r1, %2, %Y0";
   /* If operands are global or in registers, can use return */
   else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1])
 	   && (GET_CODE (operands[2]) == CONST_INT
 	       || IN_OR_GLOBAL_P (operands[2])))
-    return \"return\\t%%i7+8\\n\\tadd\\t%Y1, %Y2, %Y0\";
+    return "return\\t%%i7+8\\n\\tadd\\t%Y1, %Y2, %Y0";
   else
-    return \"ret\;restore %r1, %2, %Y0\";
-}"
+    return "ret\;restore %r1, %2, %Y0";
+}
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
@@ -8351,16 +8193,15 @@
 		   (match_operand:SI 2 "immediate_operand" "in")))
    (return)]
   "sparc_emitting_epilogue && ! TARGET_CM_MEDMID"
-  "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %r1, %%lo(%a2), %Y0\";
+    return "jmp\\t%%i7+12\\n\\trestore %r1, %%lo(%a2), %Y0";
   /* If operands are global or in registers, can use return */
   else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]))
-    return \"return\\t%%i7+8\\n\\tor\\t%Y1, %%lo(%a2), %Y0\";
+    return "return\\t%%i7+8\\n\\tor\\t%Y1, %%lo(%a2), %Y0";
   else
-    return \"ret\;restore %r1, %%lo(%a2), %Y0\";
-}"
+    return "ret\;restore %r1, %%lo(%a2), %Y0";
+}
   [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
@@ -8436,14 +8277,13 @@
    (match_operand 1 "const_int_operand" "")
    (match_operand 2 "const_int_operand" "")]
   "TARGET_V9"
-  "
 {
   if (TARGET_ARCH64)
     emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2]));
   else
     emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2]));
   DONE;
-}")
+})
 
 (define_insn "prefetch_64"
   [(prefetch (match_operand:DI 0 "address_operand" "p")
@@ -8502,11 +8342,10 @@
 (define_expand "prologue"
   [(const_int 1)]
   "flag_pic && current_function_uses_pic_offset_table"
-  "
 {
   load_pic_register ();
   DONE;
-}")
+})
 
 ;; We need to reload %l7 for -mflat -fpic,
 ;; otherwise %l7 should be preserved simply
@@ -8514,21 +8353,19 @@
 (define_expand "exception_receiver"
   [(const_int 0)]
   "TARGET_FLAT && flag_pic"
-  "
 {
   load_pic_register ();
   DONE;
-}")
+})
 
 ;; Likewise
 (define_expand "builtin_setjmp_receiver"
   [(label_ref (match_operand 0 "" ""))]
   "TARGET_FLAT && flag_pic"
-  "
 {
   load_pic_register ();
   DONE;
-}")
+})
 
 (define_insn "trap"
   [(trap_if (const_int 1) (const_int 5))]