({add,sub,mulsi}di3): Support both endian possibilities.

(negdi2): Likewise.

From-SVN: r10281

gcc/config/rs6000/rs6000.md

@@ -3540,7 +3540,12 @@
 	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
 		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
   "! TARGET_POWER && ! TARGET_POWERPC64"
-  "addc %L0,%L1,%L2\;adde %0,%1,%2"
+  "*
+{
+  return (WORDS_BIG_ENDIAN)
+  ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
+  : \"addc %0,%1,%2\;adde %L0,%L1,%L2\";
+}"
   [(set_attr "length" "8")])
 
 (define_expand "subdi3"
@@ -3570,7 +3575,12 @@
 	(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 		  (match_operand:DI 2 "gpc_reg_operand" "r")))]
   "! TARGET_POWER && ! TARGET_POWERPC64"
-  "subfc %L0,%L2,%L1\;subfe %0,%2,%1"
+  "*
+{
+  return (WORDS_BIG_ENDIAN)
+    ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
+    : \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\";
+}"
   [(set_attr "length" "8")])
 
 (define_expand "negdi2"
@@ -3583,7 +3593,12 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
   "! TARGET_POWERPC64"
-  "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1"
+  "*
+{
+  return (WORDS_BIG_ENDIAN)
+    ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
+    : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
+}"
   [(set_attr "length" "8")])
 
 (define_expand "mulsidi3"
@@ -3626,7 +3641,12 @@
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
   "TARGET_POWERPC && ! TARGET_POWERPC64"
-  "mulhw %0,%1,%2\;mullw %L0,%1,%2"
+  "*
+{
+  return (WORDS_BIG_ENDIAN)
+    ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
+    : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
+}"
   [(set_attr "type" "imul")
    (set_attr "length" "8")])