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Commit 4c54e4e4 by Ian Dall Committed by Richard Henderson
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ns32k update from Ian Dall and Hans-Peter Nilsson. 

Co-Authored-By: Hans-Peter Nilsson <hp@bitrange.com>

From-SVN: r31648
parent f85cedde
Showing with 546 additions and 497 deletions
gcc/ChangeLog
2000-01-27 Ian Dall <ian@sibyl.beware.dropbear.id.au>
Hans-Peter Nilsson <hp@bitrange.com>
* ns32k/xm-ns32k.h (memcpy, memset, memcmp): Delete.
Remove redundant include of xm-ns32k.h.
* ns32k/xm-genix.h (memcpy, memset, memcmp): Add definitions.
Remove redundant include of xm-ns32k.h.
* ns32k/xm-netbsd.h (memcpy, memset, memcmp): No longer undefine.
Remove redundant include of xm-ns32k.h.
* ns32k/netbsd.h (TARGET_DEFAULT): Enable multiply-add instructions.
* ns32k/ns32k.h: Update comment on multiply-add instructions.
(TARGET_SWITCHES): Add documentation strings.
(DWARF_FRAME_REGNUM): Override default definition.
(REG_CLASS_CONTENTS): Add comments.
(SUBSET_P): Format to reduce line length.
(SMALL_REGISTER_CLASSES): Make a run time option.
(GO_IF_NONINDEXED_ADDRESS): Reformat.
(GO_IF_LEGITIMATE_ADDRESS): Ensure that cfun is non NULL before
dereferencing it. Braces to avoid "ambiguous else" were misplaced.
(regclass_map): fix typo in comment.
* ns32k/ns32k.c: Add spaces before parentheses for consistant style.
Prefer gen_rtx_FOO(...) to gen_rtx(FOO,...).
(trace, reg_or_mem_operand): Delete, unused function.
(calc_address_cost): Small offsets are cheaper than large ones.
(expand_block_move): Generate more efficient code when bytes is a
known at compile time.
* ns32k/ns32k.md: Alternate constraints for multiply-add instructions.
(udivmodsi4, udivmodhi4, udivmodqi4): Use nonimmediate_operand
instead of reg_or_mem_operand. Use VOIDmode for load or push
effective address.
* ns32k/ns32k.md: Use nonimmediate_operand or stricter for outputs,
not general_operand. Similarly use "=rm" or stricter, not "=g".
For input operands, use stricter constraints than "g" if not
general_operand. Similarly use stricter predicate than
"general_operand" when stricter constraints than "g" are present,
except for matching constraints.
(movstrsi): Use "memory_operand" for operands 0 and 1.
(truncsiqi2, truncsihi2, trunchiqi2): Remove.
(udivmoddisi4_internal): Use nonimmediate_operand for operand 0,
not reg_or_mem_operand.
(udivmoddisi4): Ditto.
Use nonimmediate_operand for operand 1, not reg_or_mem_operand.
Use nonimmediate_operand for operand 3, not register_operand.
(udivmoddiqi4_internal): Use register_operand for operand 1, not
reg_or_mem_operand.
2000-01-27 Fred Fish <fnf@be.com>
* gthr-posix.h: Fix typo; compatibily -> compatibility.
......
gcc/config/ns32k/netbsd.h
......@@ -25,9 +25,10 @@ Boston, MA 02111-1307, USA.
/* Compile for the floating point unit & 32532 by default;
Don't assume SB is zero;
Don't use bitfield instructions;
FPU is 32381; */
FPU is 32381;
Use multiply-add instructions */
#define TARGET_DEFAULT (1 + 24 + 32 + 64 + 256)
#define TARGET_DEFAULT (1 + 24 + 32 + 64 + 256 + 512)
/* 32-bit alignment for efficiency */
......@@ -110,4 +111,3 @@ Boston, MA 02111-1307, USA.
/* Until they use ELF or something that handles dwarf2 unwinds
and initialization stuff better. */
#define DWARF2_UNWIND_INFO 0
gcc/config/ns32k/ns32k.c
......@@ -69,9 +69,9 @@ hard_regno_mode_ok (regno, mode)
int regno;
enum machine_mode mode;
{
int size = GET_MODE_UNIT_SIZE(mode);
int size = GET_MODE_UNIT_SIZE (mode);
if (FLOAT_MODE_P(mode))
if (FLOAT_MODE_P (mode))
{
if (size == UNITS_PER_WORD && regno < L1_REGNUM)
return 1;
......@@ -90,20 +90,20 @@ hard_regno_mode_ok (regno, mode)
return 0;
}
int register_move_cost(CLASS1, CLASS2)
int register_move_cost (CLASS1, CLASS2)
enum reg_class CLASS1;
enum reg_class CLASS2;
{
if (CLASS1 == NO_REGS || CLASS2 == NO_REGS)
return 2;
if((SUBSET_P(CLASS1, FP_REGS) && !SUBSET_P(CLASS2, FP_REGS))
|| (!SUBSET_P(CLASS1, FP_REGS) && SUBSET_P(CLASS2, FP_REGS)))
if ((SUBSET_P (CLASS1, FP_REGS) && !SUBSET_P (CLASS2, FP_REGS))
|| (!SUBSET_P (CLASS1, FP_REGS) && SUBSET_P (CLASS2, FP_REGS)))
return 8;
if (((CLASS1) == STACK_POINTER_REG && !SUBSET_P(CLASS2,GENERAL_REGS))
|| ((CLASS2) == STACK_POINTER_REG && !SUBSET_P(CLASS1,GENERAL_REGS)))
if (((CLASS1) == STACK_POINTER_REG && !SUBSET_P (CLASS2,GENERAL_REGS))
|| ((CLASS2) == STACK_POINTER_REG && !SUBSET_P (CLASS1,GENERAL_REGS)))
return 6;
if (((CLASS1) == FRAME_POINTER_REG && !SUBSET_P(CLASS2,GENERAL_REGS))
|| ((CLASS2) == FRAME_POINTER_REG && !SUBSET_P(CLASS1,GENERAL_REGS)))
if (((CLASS1) == FRAME_POINTER_REG && !SUBSET_P (CLASS2,GENERAL_REGS))
|| ((CLASS2) == FRAME_POINTER_REG && !SUBSET_P (CLASS1,GENERAL_REGS)))
return 6;
return 2;
}
......@@ -111,13 +111,13 @@ int register_move_cost(CLASS1, CLASS2)
#if 0
/* We made the insn definitions copy from floating point to general
registers via the stack. */
int secondary_memory_needed(CLASS1, CLASS2, M)
int secondary_memory_needed (CLASS1, CLASS2, M)
enum reg_class CLASS1;
enum reg_class CLASS2;
enum machine_mode M;
{
int ret = ((SUBSET_P(CLASS1, FP_REGS) && !SUBSET_P(CLASS2, FP_REGS))
|| (!SUBSET_P(CLASS1, FP_REGS) && SUBSET_P(CLASS2, FP_REGS)));
int ret = ((SUBSET_P (CLASS1, FP_REGS) && !SUBSET_P (CLASS2, FP_REGS))
|| (!SUBSET_P (CLASS1, FP_REGS) && SUBSET_P (CLASS2, FP_REGS)));
return ret;
}
#endif
......@@ -133,28 +133,34 @@ calc_address_cost (operand)
{
int i;
int cost = 0;
if (GET_CODE (operand) == MEM)
cost += 3;
if (GET_CODE (operand) == MULT)
cost += 2;
#if 0
if (GET_CODE (operand) == REG)
cost += 1; /* not really, but the documentation
says different amount of registers
shouldn't return the same costs */
#endif
switch (GET_CODE (operand))
{
case REG:
case CONST:
case CONST_INT:
case CONST_DOUBLE:
case SYMBOL_REF:
case LABEL_REF:
cost += 1;
break;
case POST_DEC:
case PRE_DEC:
break;
case CONST_INT:
if (INTVAL (operand) <= 7 && INTVAL (operand) >= -8)
break;
if (INTVAL (operand) < 0x2000 && INTVAL (operand) >= -0x2000)
{
cost +=1;
break;
}
case CONST:
case LABEL_REF:
case SYMBOL_REF:
cost +=3;
break;
case CONST_DOUBLE:
cost += 5;
break;
case MEM:
cost += calc_address_cost (XEXP (operand, 0));
break;
......@@ -196,6 +202,7 @@ secondary_reload_class (class, mode, in)
/* The expression to be build is BASE[INDEX:SCALE]. To recognize this,
scale must be converted from an exponent (from ASHIFT) to a
multiplier (for MULT). */
static rtx
gen_indexed_expr (base, index, scale)
rtx base, index, scale;
......@@ -212,20 +219,6 @@ gen_indexed_expr (base, index, scale)
return addr;
}
/* Return 1 if OP is a valid operand of mode MODE. This
predicate rejects operands which do not have a mode
(such as CONST_INT which are VOIDmode). */
int
reg_or_mem_operand (op, mode)
register rtx op;
enum machine_mode mode;
{
return (GET_MODE (op) == mode
&& (GET_CODE (op) == REG
|| GET_CODE (op) == SUBREG
|| GET_CODE (op) == MEM));
}
/* Split one or more DImode RTL references into pairs of SImode
references. The RTL can be REG, offsettable MEM, integer constant, or
......@@ -256,7 +249,7 @@ split_di (operands, num, lo_half, hi_half)
hi_half[num] = adj_offsettable_operand (operands[num], 4);
}
else
abort();
abort ();
}
}
......@@ -414,7 +407,7 @@ output_move_double (operands)
operands[3] is the alignment. */
static void
move_tail(operands, bytes, offset)
move_tail (operands, bytes, offset)
rtx operands[];
int bytes;
int offset;
......@@ -422,21 +415,21 @@ move_tail(operands, bytes, offset)
if (bytes & 2)
{
rtx src, dest;
dest = change_address(operands[0], HImode,
plus_constant(XEXP(operands[0], 0), offset));
src = change_address(operands[1], HImode,
plus_constant(XEXP(operands[1], 0), offset));
emit_move_insn(dest, src);
dest = change_address (operands[0], HImode,
plus_constant (XEXP (operands[0], 0), offset));
src = change_address (operands[1], HImode,
plus_constant (XEXP (operands[1], 0), offset));
emit_move_insn (dest, src);
offset += 2;
}
if (bytes & 1)
{
rtx src, dest;
dest = change_address(operands[0], QImode,
plus_constant(XEXP(operands[0], 0), offset));
src = change_address(operands[1], QImode,
plus_constant(XEXP(operands[1], 0), offset));
emit_move_insn(dest, src);
dest = change_address (operands[0], QImode,
plus_constant (XEXP (operands[0], 0), offset));
src = change_address (operands[1], QImode,
plus_constant (XEXP (operands[1], 0), offset));
emit_move_insn (dest, src);
}
}
......@@ -449,9 +442,9 @@ expand_block_move (operands)
int constp = (GET_CODE (bytes_rtx) == CONST_INT);
int bytes = (constp ? INTVAL (bytes_rtx) : 0);
int align = INTVAL (align_rtx);
rtx src_reg = gen_rtx(REG, Pmode, 1);
rtx dest_reg = gen_rtx(REG, Pmode, 2);
rtx count_reg = gen_rtx(REG, SImode, 0);
rtx src_reg = gen_rtx_REG (Pmode, 1);
rtx dest_reg = gen_rtx_REG (Pmode, 2);
rtx count_reg = gen_rtx_REG (SImode, 0);
if (constp && bytes <= 0)
return;
......@@ -460,34 +453,34 @@ expand_block_move (operands)
{
int words = bytes >> 2;
if (words)
{
if (words < 3 || flag_unroll_loops)
{
int offset = 0;
for (; words; words--, offset += 4)
{
rtx src, dest;
dest = change_address(operands[0], SImode,
plus_constant(XEXP(operands[0], 0), offset));
src = change_address(operands[1], SImode,
plus_constant(XEXP(operands[1], 0), offset));
emit_move_insn(dest, src);
}
}
else
{
/* Use movmd. It is slower than multiple movd's but more
compact. It is also slower than movsd for large copies
but causes less registers reloading so is better than movsd
for small copies. */
rtx src, dest;
dest = copy_addr_to_reg (XEXP(operands[0], 0));
src = copy_addr_to_reg (XEXP(operands[1], 0));
{
if (words < 3 || flag_unroll_loops)
{
int offset = 0;
for (; words; words--, offset += 4)
{
rtx src, dest;
dest = change_address (operands[0], SImode,
plus_constant (XEXP (operands[0], 0), offset));
src = change_address (operands[1], SImode,
plus_constant (XEXP (operands[1], 0), offset));
emit_move_insn (dest, src);
}
}
else
{
/* Use movmd. It is slower than multiple movd's but more
compact. It is also slower than movsd for large copies
but causes less registers reloading so is better than movsd
for small copies. */
rtx src, dest;
dest = copy_addr_to_reg (XEXP (operands[0], 0));
src = copy_addr_to_reg (XEXP (operands[1], 0));
emit_insn(gen_movstrsi2(dest, src, GEN_INT(words)));
}
}
move_tail(operands, bytes & 3, bytes & ~3);
emit_insn (gen_movstrsi2(dest, src, GEN_INT (words)));
}
}
move_tail (operands, bytes & 3, bytes & ~3);
return;
}
......@@ -495,11 +488,13 @@ expand_block_move (operands)
align = UNITS_PER_WORD;
/* Move the address into scratch registers. */
emit_insn(gen_rtx(CLOBBER, VOIDmode, dest_reg));
emit_move_insn(dest_reg, XEXP (operands[0], 0));
emit_insn(gen_rtx(CLOBBER, VOIDmode, src_reg));
emit_move_insn(src_reg, XEXP (operands[1], 0));
emit_insn(gen_rtx(CLOBBER, VOIDmode, count_reg));
emit_insn (gen_rtx_CLOBBER (VOIDmode, dest_reg));
emit_move_insn (dest_reg, XEXP (operands[0], 0));
operands[0] = gen_rtx_MEM (SImode, dest_reg);
emit_insn (gen_rtx_CLOBBER (VOIDmode, src_reg));
emit_move_insn (src_reg, XEXP (operands[1], 0));
operands[1] = gen_rtx_MEM (SImode, src_reg);
emit_insn (gen_rtx_CLOBBER (VOIDmode, count_reg));
if (constp && (align == UNITS_PER_WORD || bytes < MAX_UNALIGNED_COPY))
{
......@@ -508,20 +503,27 @@ expand_block_move (operands)
*/
if (bytes >> 2)
{
emit_move_insn(count_reg, GEN_INT(bytes >> 2));
emit_insn(gen_movstrsi1 (GEN_INT(4)));
emit_move_insn (count_reg, GEN_INT (bytes >> 2));
emit_insn (gen_movstrsi1 (GEN_INT (4)));
}
/* insns to copy rest */
move_tail(operands, bytes & 3, bytes & ~3);
move_tail (operands, bytes & 3, 0);
}
else if (align == UNITS_PER_WORD)
{
/* insns to copy by words */
emit_insn(gen_lshrsi3 (count_reg, bytes_rtx, GEN_INT(2)));
emit_insn(gen_movstrsi1 (GEN_INT(4)));
/* insns to copy rest */
emit_insn(gen_andsi3 (count_reg, bytes_rtx, GEN_INT(3)));
emit_insn(gen_movstrsi1 (const1_rtx));
emit_insn (gen_lshrsi3 (count_reg, bytes_rtx, GEN_INT (2)));
emit_insn (gen_movstrsi1 (GEN_INT (4)));
if (constp)
{
move_tail (operands, bytes & 3, 0);
}
else
{
/* insns to copy rest */
emit_insn (gen_andsi3 (count_reg, bytes_rtx, GEN_INT (3)));
emit_insn (gen_movstrsi1 (const1_rtx));
}
}
else
{
......@@ -531,32 +533,32 @@ expand_block_move (operands)
rtx aligned_label = gen_label_rtx ();
rtx bytes_reg;
bytes_reg = copy_to_mode_reg(SImode, bytes_rtx);
bytes_reg = copy_to_mode_reg (SImode, bytes_rtx);
if (!constp)
{
/* Emit insns to test and skip over the alignment if it is
* not worth it. This doubles as a test to ensure that the alignment
* operation can't copy too many bytes
*/
emit_insn(gen_cmpsi (bytes_reg, GEN_INT(MAX_UNALIGNED_COPY)));
emit_insn (gen_cmpsi (bytes_reg, GEN_INT (MAX_UNALIGNED_COPY)));
emit_jump_insn (gen_blt (aligned_label));
}
/* Emit insns to do alignment at run time */
emit_insn(gen_negsi2 (count_reg, src_reg));
emit_insn(gen_andsi3 (count_reg, count_reg, GEN_INT(3)));
emit_insn(gen_subsi3 (bytes_reg, bytes_reg, count_reg));
emit_insn(gen_movstrsi1 (const1_rtx));
emit_insn (gen_negsi2 (count_reg, src_reg));
emit_insn (gen_andsi3 (count_reg, count_reg, GEN_INT (3)));
emit_insn (gen_subsi3 (bytes_reg, bytes_reg, count_reg));
emit_insn (gen_movstrsi1 (const1_rtx));
if (!constp)
emit_label (aligned_label);
/* insns to copy by words */
emit_insn (gen_lshrsi3 (count_reg, bytes_reg, GEN_INT(2)));
emit_insn(gen_movstrsi1 (GEN_INT(4)));
emit_insn (gen_lshrsi3 (count_reg, bytes_reg, GEN_INT (2)));
emit_insn (gen_movstrsi1 (GEN_INT (4)));
/* insns to copy rest */
emit_insn (gen_andsi3 (count_reg, bytes_reg, GEN_INT(3)));
emit_insn(gen_movstrsi1 (const1_rtx));
emit_insn (gen_andsi3 (count_reg, bytes_reg, GEN_INT (3)));
emit_insn (gen_movstrsi1 (const1_rtx));
}
}
......@@ -759,7 +761,7 @@ print_operand (file, x, code)
{
union { double d; int i[2]; } u;
u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
PUT_IMMEDIATE_PREFIX(file);
PUT_IMMEDIATE_PREFIX (file);
#ifdef SEQUENT_ASM
/* Sequent likes its floating point constants as integers */
fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]);
......@@ -798,10 +800,10 @@ print_operand (file, x, code)
&& GET_CODE (x) == CONST
&& symbolic_reference_mentioned_p (x))
{
fprintf(stderr, "illegal constant for pic-mode: \n");
print_rtl(stderr, x);
fprintf(stderr, "\nGET_CODE (x) == %d, CONST == %d, symbolic_reference_mentioned_p (x) == %d\n",
GET_CODE (x), CONST, symbolic_reference_mentioned_p(x));
fprintf (stderr, "illegal constant for pic-mode: \n");
print_rtl (stderr, x);
fprintf (stderr, "\nGET_CODE (x) == %d, CONST == %d, symbolic_reference_mentioned_p (x) == %d\n",
GET_CODE (x), CONST, symbolic_reference_mentioned_p (x));
abort ();
}
else if (flag_pic
......@@ -1025,7 +1027,7 @@ print_operand_address (file, addr)
fprintf (file, "(sb))");
break;
case MEM:
addr = XEXP(base,0);
addr = XEXP (base,0);
base = NULL;
offset = NULL;
while (addr != NULL)
......@@ -1127,46 +1129,46 @@ output_shift_insn (operands)
if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) <= 3)
{
if (GET_CODE (operands[0]) == REG)
{
if (GET_CODE (operands[1]) == REG)
{
if (REGNO (operands[0]) == REGNO (operands[1]))
{
if (operands[2] == const1_rtx)
return "addd %0,%0";
else if (INTVAL (operands[2]) == 2)
return "addd %0,%0\n\taddd %0,%0";
}
if (operands[2] == const1_rtx)
return "movd %1,%0\n\taddd %0,%0";
{
if (GET_CODE (operands[0]) == REG)
{
if (GET_CODE (operands[1]) == REG)
{
if (REGNO (operands[0]) == REGNO (operands[1]))
{
if (operands[2] == const1_rtx)
return "addd %0,%0";
else if (INTVAL (operands[2]) == 2)
return "addd %0,%0\n\taddd %0,%0";
}
if (operands[2] == const1_rtx)
return "movd %1,%0\n\taddd %0,%0";
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
return "addr %a1,%0";
}
if (operands[2] == const1_rtx)
return "movd %1,%0\n\taddd %0,%0";
}
else if (GET_CODE (operands[1]) == REG)
{
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
return "addr %a1,%0";
}
else if (INTVAL (operands[2]) == 1
&& GET_CODE (operands[1]) == MEM
&& rtx_equal_p (operands [0], operands[1]))
{
rtx temp = XEXP (operands[1], 0);
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
return "addr %a1,%0";
}
if (operands[2] == const1_rtx)
return "movd %1,%0\n\taddd %0,%0";
}
else if (GET_CODE (operands[1]) == REG)
{
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
return "addr %a1,%0";
}
else if (INTVAL (operands[2]) == 1
&& GET_CODE (operands[1]) == MEM
&& rtx_equal_p (operands [0], operands[1]))
{
rtx temp = XEXP (operands[1], 0);
if (GET_CODE (temp) == REG
|| (GET_CODE (temp) == PLUS
&& GET_CODE (XEXP (temp, 0)) == REG
&& GET_CODE (XEXP (temp, 1)) == CONST_INT))
return "addd %0,%0";
}
else return "ashd %2,%0";
}
if (GET_CODE (temp) == REG
|| (GET_CODE (temp) == PLUS
&& GET_CODE (XEXP (temp, 0)) == REG
&& GET_CODE (XEXP (temp, 1)) == CONST_INT))
return "addd %0,%0";
}
else return "ashd %2,%0";
}
return "ashd %2,%0";
}
......
gcc/config/ns32k/ns32k.h
......@@ -66,13 +66,8 @@ extern int target_flags;
#define TARGET_32081 (target_flags & 1)
#define TARGET_32381 (target_flags & 256)
/* The use of multiply-add instructions is optional because it can
* cause an abort due to being unable to find a spill register. The
* main problem is that the multiply-add instructions require f0 and
* f0 is not available for spilling because it is "explicitly
* mentioned" in the rtl for function return values. This can be fixed
* by defining SMALL_REGISTER_CLASSES, but that causes worse code for
* the (more common) integer case. We really need better reload code.
/* The use of multiply-add instructions is optional because there may
* be cases where it produces worse code.
*/
#define TARGET_MULT_ADD (target_flags & 512)
......@@ -103,27 +98,29 @@ extern int target_flags;
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
{ { "32081", 1}, \
{ "soft-float", -257}, \
{ "rtd", 2}, \
{ "nortd", -2}, \
{ "regparm", 4}, \
{ "noregparm", -4}, \
{ "32532", 24}, \
{ "32332", -8}, \
{ "32332", 16}, \
{ "32032", -24}, \
{ "sb", -32}, \
{ "nosb", 32}, \
{ "bitfield", -64}, \
{ "nobitfield", 64}, \
{ "himem", 128}, \
{ "nohimem", -128}, \
{ "32381", 256}, \
{ "mult-add", 512}, \
{ "nomult-add", -512}, \
{ "", TARGET_DEFAULT}}
#define TARGET_SWITCHES \
{ { "32081", 1, "Use hardware fp"}, \
{ "soft-float", -257, "Don't use hardware fp"}, \
{ "rtd", 2, "Alternative calling convention"}, \
{ "nortd", -2, "Use normal calling convention"}, \
{ "regparm", 4, "Pass some arguments in registers"}, \
{ "noregparm", -4, "Pass all arguments on stack"}, \
{ "32532", 24, "Optimize for 32532 cpu"}, \
{ "32332", 16, "Optimize for 32332 cpu"}, \
{ "32332", -8, 0}, \
{ "32032", -24, "Optimize for 32032"}, \
{ "sb", -32, "Register sb is zero. Use for absolute addressing"}, \
{ "nosb", 32, "Do not use register sb"}, \
{ "bitfield", -64, "Do not use bitfield instructions"}, \
{ "nobitfield", 64, "Use bitfield instructions"}, \
{ "himem", 128, "Generate code for high memory"}, \
{ "nohimem", -128, "Generate code for low memory"}, \
{ "32381", 256, "32381 fpu"}, \
{ "mult-add", 512, "Use multiply-accumulate fp instructions"}, \
{ "nomult-add", -512, "Do not use multiply-accumulate fp instructions" }, \
{ "src", 1024, "\"Small register classes\" kludge"}, \
{ "nosrc", -1024, "No \"Small register classes\" kludge"}, \
{ "", TARGET_DEFAULT, 0}}
/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
......@@ -304,6 +301,11 @@ while (0)
: (REGNO) == FRAME_POINTER_REGNUM? 17 \
: 16)
/* dwarf2out.c can't understand the funny DBX register numbering.
* We use dwarf2out.c for exception handling even though we use DBX
* for debugging
*/
#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
......@@ -408,13 +410,23 @@ enum reg_class
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
#define REG_CLASS_CONTENTS {{0}, {0x00ff}, {0x100}, {0x300}, {0xff00}, \
{0xffff00}, {0xffffff}, {0x1000000}, {0x2000000}, \
{0x30000ff}, {0x3ffffff} }
#define SUBSET_P(CLASS1, CLASS2) \
((ns32k_reg_class_contents[CLASS1][0] & ~ns32k_reg_class_contents[CLASS2][0]) \
== 0)
#define REG_CLASS_CONTENTS \
{{0}, /* NO_REGS */ \
{0x00ff}, /* GENERAL_REGS */ \
{0x100}, /* FLOAT_REG0 */ \
{0x300}, /* LONG_FLOAT_REG0 */ \
{0xff00}, /* FLOAT_REGS */ \
{0xffff00}, /* FP_REGS */ \
{0xffffff}, /* GEN_AND_FP_REGS */ \
{0x1000000}, /* FRAME_POINTER_REG */ \
{0x2000000}, /* STACK_POINTER_REG */ \
{0x30000ff}, /* GEN_AND_MEM_REGS */ \
{0x3ffffff} /* ALL_REGS */ \
}
#define SUBSET_P(CLASS1, CLASS2) \
((ns32k_reg_class_contents[CLASS1][0] \
& ~ns32k_reg_class_contents[CLASS2][0]) == 0)
/* The same information, inverted:
Return the class number of the smallest class containing
......@@ -1036,10 +1048,10 @@ __transfer_from_trampoline () \
secondary_memory_needed(CLASS1, CLASS2, M)
#endif
/* SMALL_REGISTER_CLASSES is true only if we have said we are using the
* multiply-add instructions.
*/
#define SMALL_REGISTER_CLASSES (target_flags & 512)
/* SMALL_REGISTER_CLASSES is a run time option. This should no longer
be necessay and should go when we have confidence that we won't run
out of spill registers */
#define SMALL_REGISTER_CLASSES (target_flags & 1024)
/* A C expression whose value is nonzero if pseudos that have been
assigned to registers of class CLASS would likely be spilled
......@@ -1144,13 +1156,14 @@ __transfer_from_trampoline () \
/* Go to ADDR if X is a valid address not using indexing.
(This much is the easy part.) */
#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
{ if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; \
if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \
if (GET_CODE (X) == PLUS) \
if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1))) \
if (INDIRECTABLE_2_ADDRESS_P (XEXP (X, 0))) \
goto ADDR; \
#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
{ \
if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; \
if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \
if (GET_CODE (X) == PLUS) \
if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1))) \
if (INDIRECTABLE_2_ADDRESS_P (XEXP (X, 0))) \
goto ADDR; \
}
/* Go to ADDR if X is a valid address not using indexing.
......@@ -1189,11 +1202,11 @@ __transfer_from_trampoline () \
((xfoo2 < 4 && xfoo2 != 2) || xfoo2 == 7))
/* Note that xfoo0, xfoo1, xfoo2 are used in some of the submacros above. */
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ register rtx xfooy, xfoo0, xfoo1; \
unsigned xfoo2; \
xfooy = X; \
if (flag_pic && ! current_function_uses_pic_offset_table \
if (flag_pic && cfun && ! current_function_uses_pic_offset_table \
&& global_symbolic_reference_mentioned_p (X, 1)) \
current_function_uses_pic_offset_table = 1; \
GO_IF_NONINDEXED_ADDRESS (xfooy, ADDR); \
......@@ -1212,8 +1225,8 @@ __transfer_from_trampoline () \
else if (GET_CODE (xfooy) == PRE_DEC) \
{ \
if (REGNO (XEXP (xfooy, 0)) == STACK_POINTER_REGNUM) goto ADDR; \
else abort (); \
} \
else abort (); \
}
/* Try machine-dependent ways of modifying an illegitimate address
......@@ -1679,7 +1692,7 @@ do { \
extern unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1];
extern const char *const ns32k_out_reg_names[];
extern enum reg_class regclass_map[]; /* smalled class containing REGNO */
extern enum reg_class regclass_map[]; /* smallest class containing REGNO */
/*
Local variables:
......
gcc/config/ns32k/ns32k.md
......@@ -53,6 +53,13 @@
;; but with the proper definition of LEGITIMATE_PIC_OPERAND (ns32k.h)
;; this is unnecessary.
;;
;; It seems that in current CVS (2000-01-11), at least with
;; libgcc2.a, that register allocation gets worse when changing
;; "general_operand" "0" to "nonimmediate_operand" "0" (and
;; similar "0"-containing constraints), if operand 0 is (e.g.)
;; "nonimmediate_operand" "=rm". Revisit and test later.
(define_insn "tstsi"
[(set (cc0)
(match_operand:SI 0 "nonimmediate_operand" "rm"))]
......@@ -64,7 +71,7 @@
(define_insn "tsthi"
[(set (cc0)
(match_operand:HI 0 "nonimmediate_operand" "g"))]
(match_operand:HI 0 "nonimmediate_operand" "rm"))]
""
"*
{ cc_status.flags |= CC_REVERSED;
......@@ -73,7 +80,7 @@
(define_insn "tstqi"
[(set (cc0)
(match_operand:QI 0 "nonimmediate_operand" "g"))]
(match_operand:QI 0 "nonimmediate_operand" "rm"))]
""
"*
{ cc_status.flags |= CC_REVERSED;
......@@ -209,7 +216,7 @@
;; in practice, though the stack slots used are not available for
;; optimization.
(define_insn "movdf"
[(set (match_operand:DF 0 "general_operand" "=lg<")
[(set (match_operand:DF 0 "nonimmediate_operand" "=lrm<")
(match_operand:DF 1 "general_operand" "lFg"))]
""
"*
......@@ -243,7 +250,7 @@
}")
(define_insn "movsf"
[(set (match_operand:SF 0 "general_operand" "=fg<")
[(set (match_operand:SF 0 "nonimmediate_operand" "=frm<")
(match_operand:SF 1 "general_operand" "fFg"))]
""
"*
......@@ -292,7 +299,7 @@
"movmd %1,%0,4")
(define_insn "movdi"
[(set (match_operand:DI 0 "general_operand" "=g<,*f,g")
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm<,*f,rm")
(match_operand:DI 1 "general_operand" "gF,g,*f"))]
""
"*
......@@ -333,7 +340,7 @@
"lprd sp,%0")
(define_insn "movsi"
[(set (match_operand:SI 0 "general_operand" "=g<,g<,*f,g,x")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<,rm<,*f,rm,x")
(match_operand:SI 1 "general_operand" "g,?xy,g,*f,rmn"))]
""
"*
......@@ -425,7 +432,7 @@
}")
(define_insn "movhi"
[(set (match_operand:HI 0 "general_operand" "=g<,*f,g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<,*f,rm")
(match_operand:HI 1 "general_operand" "g,g,*f"))]
""
"*
......@@ -459,7 +466,7 @@
}")
(define_insn "movstricthi"
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
(match_operand:HI 1 "general_operand" "g"))]
""
"*
......@@ -471,7 +478,7 @@
}")
(define_insn "movqi"
[(set (match_operand:QI 0 "general_operand" "=g<,*f,g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<,*f,rm")
(match_operand:QI 1 "general_operand" "g,g,*f"))]
""
"*
......@@ -504,7 +511,7 @@
}")
(define_insn "movstrictqi"
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
(match_operand:QI 1 "general_operand" "g"))]
""
"*
......@@ -527,8 +534,8 @@
;; which can be used to generate more complex code.
(define_expand "movstrsi"
[(parallel [(set (match_operand:BLK 0 "general_operand" "")
(match_operand:BLK 1 "general_operand" ""))
[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" ""))
(use (match_operand:SI 2 "general_operand" ""))
(use (match_operand:SI 3 "const_int_operand" ""))])]
""
......@@ -566,8 +573,8 @@
}")
(define_insn "movstrsi2"
[(set (mem:BLK (match_operand:SI 0 "address_operand" "g"))
(mem:BLK (match_operand:SI 1 "address_operand" "g")))
[(set (mem:BLK (match_operand:SI 0 "address_operand" "p"))
(mem:BLK (match_operand:SI 1 "address_operand" "p")))
(use (match_operand 2 "immediate_operand" "i"))]
""
"movmd %a1,%a0,%2")
......@@ -577,69 +584,51 @@
;; Those for integer source operand
;; are ordered widest source type first.
(define_insn "truncsiqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
(truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
""
"movb %1,%0")
(define_insn "truncsihi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
(truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
""
"movw %1,%0")
(define_insn "trunchiqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
(truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
""
"movb %1,%0")
(define_insn "extendhisi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
""
"movxwd %1,%0")
(define_insn "extendqihi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
""
"movxbw %1,%0")
(define_insn "extendqisi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
""
"movxbd %1,%0")
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "general_operand" "=lm<")
[(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
(float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
"movfl %1,%0")
(define_insn "truncdfsf2"
[(set (match_operand:SF 0 "general_operand" "=fm<")
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
(float_truncate:SF (match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
"movlf %1,%0")
(define_insn "zero_extendhisi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
""
"movzwd %1,%0")
(define_insn "zero_extendqihi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
""
"movzbw %1,%0")
(define_insn "zero_extendqisi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
""
"movzbd %1,%0")
......@@ -655,40 +644,40 @@
;; A register must be used to perform the conversion.
(define_insn "floatsisf2"
[(set (match_operand:SF 0 "general_operand" "=fm<")
(float:SF (match_operand:SI 1 "general_operand" "rm")))]
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
"TARGET_32081"
"movdf %1,%0")
(define_insn "floatsidf2"
[(set (match_operand:DF 0 "general_operand" "=lm<")
(float:DF (match_operand:SI 1 "general_operand" "rm")))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
"TARGET_32081"
"movdl %1,%0")
(define_insn "floathisf2"
[(set (match_operand:SF 0 "general_operand" "=fm<")
(float:SF (match_operand:HI 1 "general_operand" "rm")))]
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
(float:SF (match_operand:HI 1 "nonimmediate_operand" "rm")))]
"TARGET_32081"
"movwf %1,%0")
(define_insn "floathidf2"
[(set (match_operand:DF 0 "general_operand" "=lm<")
(float:DF (match_operand:HI 1 "general_operand" "rm")))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
(float:DF (match_operand:HI 1 "nonimmediate_operand" "rm")))]
"TARGET_32081"
"movwl %1,%0")
(define_insn "floatqisf2"
[(set (match_operand:SF 0 "general_operand" "=fm<")
(float:SF (match_operand:QI 1 "general_operand" "rm")))]
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
(float:SF (match_operand:QI 1 "nonimmediate_operand" "rm")))]
"TARGET_32081"
"movbf %1,%0")
; Some assemblers warn that this insn doesn't work.
; Maybe they know something we don't.
;(define_insn "floatqidf2"
; [(set (match_operand:DF 0 "general_operand" "=lm<")
; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
; [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
; (float:DF (match_operand:QI 1 "nonimmediate_operand" "rm")))]
; "TARGET_32081"
; "movbl %1,%0")
......@@ -696,161 +685,165 @@
;; The sequent compiler always generates "trunc" insns.
(define_insn "fixsfqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
(fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(fix:QI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
"TARGET_32081"
"truncfb %1,%0")
(define_insn "fixsfhi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
(fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(fix:HI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
"TARGET_32081"
"truncfw %1,%0")
(define_insn "fixsfsi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(fix:SI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
"TARGET_32081"
"truncfd %1,%0")
(define_insn "fixdfqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
(fix:QI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(fix:QI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
"TARGET_32081"
"trunclb %1,%0")
(define_insn "fixdfhi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
(fix:HI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(fix:HI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
"TARGET_32081"
"trunclw %1,%0")
(define_insn "fixdfsi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(fix:SI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
"TARGET_32081"
"truncld %1,%0")
;; Unsigned
(define_insn "fixunssfqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
(unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(unsigned_fix:QI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
"TARGET_32081"
"truncfb %1,%0")
(define_insn "fixunssfhi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
(unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(unsigned_fix:HI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
"TARGET_32081"
"truncfw %1,%0")
(define_insn "fixunssfsi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(unsigned_fix:SI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
"TARGET_32081"
"truncfd %1,%0")
(define_insn "fixunsdfqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
(unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(unsigned_fix:QI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
"TARGET_32081"
"trunclb %1,%0")
(define_insn "fixunsdfhi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
(unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(unsigned_fix:HI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
"TARGET_32081"
"trunclw %1,%0")
(define_insn "fixunsdfsi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(unsigned_fix:SI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
"TARGET_32081"
"truncld %1,%0")
;;; These are not yet used by GCC
(define_insn "fix_truncsfqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
(fix:QI (match_operand:SF 1 "general_operand" "fm")))]
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(fix:QI (match_operand:SF 1 "nonimmediate_operand" "fm")))]
"TARGET_32081"
"truncfb %1,%0")
(define_insn "fix_truncsfhi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
(fix:HI (match_operand:SF 1 "general_operand" "fm")))]
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(fix:HI (match_operand:SF 1 "nonimmediate_operand" "fm")))]
"TARGET_32081"
"truncfw %1,%0")
(define_insn "fix_truncsfsi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(fix:SI (match_operand:SF 1 "general_operand" "fm")))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "fm")))]
"TARGET_32081"
"truncfd %1,%0")
(define_insn "fix_truncdfqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
(fix:QI (match_operand:DF 1 "general_operand" "lm")))]
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(fix:QI (match_operand:DF 1 "nonimmediate_operand" "lm")))]
"TARGET_32081"
"trunclb %1,%0")
(define_insn "fix_truncdfhi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
(fix:HI (match_operand:DF 1 "general_operand" "lm")))]
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(fix:HI (match_operand:DF 1 "nonimmediate_operand" "lm")))]
"TARGET_32081"
"trunclw %1,%0")
(define_insn "fix_truncdfsi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
(fix:SI (match_operand:DF 1 "general_operand" "lm")))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "lm")))]
"TARGET_32081"
"truncld %1,%0")
;; Multiply-add instructions
(define_insn ""
[(set (match_operand:DF 0 "general_operand" "=v,v")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF")))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
"TARGET_MULT_ADD"
"@
dotl %1,%2
polyl %2,%3")
polyl %2,%3
mull %2,%0\;addl %3,%0")
(define_insn ""
[(set (match_operand:SF 0 "general_operand" "=u,u")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF")))]
[(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
"TARGET_MULT_ADD"
"@
dotf %1,%2
polyf %2,%3")
polyf %2,%3
mulf %2,%0\;addf %3,%0")
;; Multiply-sub instructions
(define_insn ""
[(set (match_operand:DF 0 "general_operand" "=v")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF")
(match_operand:DF 2 "general_operand" "lmF"))
(match_operand:DF 3 "general_operand" "0")))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=v,lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "lmF,lmF")))]
"TARGET_MULT_ADD"
"@
negl %0,%0\;dotl %1,%2")
negl %3,%0\;dotl %1,%2
mull %2,%0\;subl %3,%0")
(define_insn ""
[(set (match_operand:SF 0 "general_operand" "=u")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF")
(match_operand:SF 2 "general_operand" "fmF"))
(match_operand:SF 3 "general_operand" "0")))]
[(set (match_operand:SF 0 "nonimmediate_operand" "=u,fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "fmF,fmF")))]
"TARGET_MULT_ADD"
"@
negf %0,%0\;dotf %1,%2")
negf %3,%0\;dotf %1,%2
mulf %2,%0\;subf %3,%0")
;;- All kinds of add instructions.
(define_insn "adddf3"
[(set (match_operand:DF 0 "general_operand" "=lm")
[(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
(plus:DF (match_operand:DF 1 "general_operand" "%0")
(match_operand:DF 2 "general_operand" "lmF")))]
"TARGET_32081"
......@@ -858,7 +851,7 @@
(define_insn "addsf3"
[(set (match_operand:SF 0 "general_operand" "=fm")
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
(plus:SF (match_operand:SF 1 "general_operand" "%0")
(match_operand:SF 2 "general_operand" "fmF")))]
"TARGET_32081"
......@@ -890,21 +883,21 @@
}")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(plus:SI (reg:SI 24)
(match_operand:SI 1 "immediate_operand" "i")))]
"GET_CODE (operands[1]) == CONST_INT"
"addr %c1(fp),%0")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(plus:SI (reg:SI 25)
(match_operand:SI 1 "immediate_operand" "i")))]
"GET_CODE (operands[1]) == CONST_INT"
"addr %c1(sp),%0")
(define_insn "adddi3"
[(set (match_operand:DI 0 "general_operand" "=ro")
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
(plus:DI (match_operand:DI 1 "general_operand" "%0")
(match_operand:DI 2 "general_operand" "ron")))]
""
......@@ -946,7 +939,7 @@
;; See Note 1
(define_insn "addsi3"
[(set (match_operand:SI 0 "general_operand" "=g,=g&<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm&<")
(plus:SI (match_operand:SI 1 "general_operand" "%0,r")
(match_operand:SI 2 "general_operand" "g,i")))]
""
......@@ -984,7 +977,7 @@
}")
(define_insn "addhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(plus:HI (match_operand:HI 1 "general_operand" "%0")
(match_operand:HI 2 "general_operand" "g")))]
""
......@@ -999,7 +992,7 @@
}")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
[(set (strict_low_part (match_operand:HI 0 "register_operand" "=r"))
(plus:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:HI 2 "general_operand" "g")))]
""
......@@ -1012,7 +1005,7 @@
}")
(define_insn "addqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(plus:QI (match_operand:QI 1 "general_operand" "%0")
(match_operand:QI 2 "general_operand" "g")))]
""
......@@ -1027,7 +1020,7 @@
}")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
[(set (strict_low_part (match_operand:QI 0 "register_operand" "=r"))
(plus:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
......@@ -1042,14 +1035,14 @@
;;- All kinds of subtract instructions.
(define_insn "subdf3"
[(set (match_operand:DF 0 "general_operand" "=lm")
[(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
(minus:DF (match_operand:DF 1 "general_operand" "0")
(match_operand:DF 2 "general_operand" "lmF")))]
"TARGET_32081"
"subl %2,%0")
(define_insn "subsf3"
[(set (match_operand:SF 0 "general_operand" "=fm")
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
(minus:SF (match_operand:SF 1 "general_operand" "0")
(match_operand:SF 2 "general_operand" "fmF")))]
"TARGET_32081"
......@@ -1069,7 +1062,7 @@
}")
(define_insn "subdi3"
[(set (match_operand:DI 0 "general_operand" "=ro")
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
(minus:DI (match_operand:DI 1 "general_operand" "0")
(match_operand:DI 2 "general_operand" "ron")))]
""
......@@ -1110,7 +1103,7 @@
}")
(define_insn "subsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(minus:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1126,7 +1119,7 @@
}")
(define_insn "subhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(minus:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:HI 2 "general_operand" "g")))]
""
......@@ -1142,7 +1135,7 @@
}")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
[(set (strict_low_part (match_operand:HI 0 "register_operand" "=r"))
(minus:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:HI 2 "general_operand" "g")))]
""
......@@ -1155,7 +1148,7 @@
}")
(define_insn "subqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(minus:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
......@@ -1171,7 +1164,7 @@
}")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
[(set (strict_low_part (match_operand:QI 0 "register_operand" "=r"))
(minus:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
......@@ -1186,14 +1179,14 @@
;;- Multiply instructions.
(define_insn "muldf3"
[(set (match_operand:DF 0 "general_operand" "=lm")
[(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
(mult:DF (match_operand:DF 1 "general_operand" "%0")
(match_operand:DF 2 "general_operand" "lmF")))]
"TARGET_32081"
"mull %2,%0")
(define_insn "mulsf3"
[(set (match_operand:SF 0 "general_operand" "=fm")
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
(mult:SF (match_operand:SF 1 "general_operand" "%0")
(match_operand:SF 2 "general_operand" "fmF")))]
"TARGET_32081"
......@@ -1201,42 +1194,42 @@
;; See note 1
(define_insn "mulsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(mult:SI (match_operand:SI 1 "general_operand" "%0")
(match_operand:SI 2 "general_operand" "g")))]
""
"muld %2,%0")
(define_insn "mulhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(mult:HI (match_operand:HI 1 "general_operand" "%0")
(match_operand:HI 2 "general_operand" "g")))]
""
"mulw %2,%0")
(define_insn "mulqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(mult:QI (match_operand:QI 1 "general_operand" "%0")
(match_operand:QI 2 "general_operand" "g")))]
""
"mulb %2,%0")
(define_insn "umulsidi3"
[(set (match_operand:DI 0 "general_operand" "=g")
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(mult:DI (zero_extend:DI
(match_operand:SI 1 "nonimmediate_operand" "0"))
(zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "g"))))]
(match_operand:SI 2 "nonimmediate_operand" "rm"))))]
""
"meid %2,%0")
;; divmod insns: We can only do the unsigned case.
(define_expand "udivmodsi4"
[(parallel
[(set (match_operand:SI 0 "reg_or_mem_operand" "")
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))
(set (match_operand:SI 3 "reg_or_mem_operand" "")
(set (match_operand:SI 3 "nonimmediate_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])]
""
"
......@@ -1272,8 +1265,8 @@
;; below. This udivmoddisi4_internal never matches anything and is only
;; ever used when explicitly emitted by a define_expand.
(define_insn "udivmoddisi4_internal"
[(set (match_operand:DI 0 "reg_or_mem_operand" "=rm")
(unspec:DI [(match_operand:DI 1 "reg_or_mem_operand" "0")
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(unspec:DI [(match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:SI 2 "general_operand" "g")] 0))]
""
"deid %2,%0")
......@@ -1281,10 +1274,10 @@
;; Retain this insn which *does* have a pattern indicating what it does,
;; just in case the compiler is smart enough to recognize a substitution.
(define_insn "udivmoddisi4"
[(set (subreg:SI (match_operand:DI 0 "register_operand" "=rm") 1)
(truncate:SI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
(zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "g")))))
(set (subreg:SI (match_operand:DI 3 "register_operand" "=0") 0)
[(set (subreg:SI (match_operand:DI 0 "nonimmediate_operand" "=rm") 1)
(truncate:SI (udiv:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))))
(set (subreg:SI (match_operand:DI 3 "nonimmediate_operand" "=0") 0)
(truncate:SI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
""
"deid %2,%0")
......@@ -1297,10 +1290,10 @@
(define_expand "udivmodhi4"
[(parallel
[(set (match_operand:HI 0 "reg_or_mem_operand" "")
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(udiv:HI (match_operand:HI 1 "general_operand" "")
(match_operand:HI 2 "general_operand" "")))
(set (match_operand:HI 3 "reg_or_mem_operand" "")
(set (match_operand:HI 3 "nonimmediate_operand" "")
(umod:HI (match_dup 1) (match_dup 2)))])]
""
"
......@@ -1345,8 +1338,8 @@
(define_insn "udivmoddihi4"
[(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 1)
(truncate:HI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
(zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "g")))))
(truncate:HI (udiv:DI (match_operand:DI 1 "register_operand" "0")
(zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "rm")))))
(set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0)
(truncate:HI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
""
......@@ -1354,10 +1347,10 @@
(define_expand "udivmodqi4"
[(parallel
[(set (match_operand:QI 0 "reg_or_mem_operand" "")
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(udiv:QI (match_operand:QI 1 "general_operand" "")
(match_operand:QI 2 "general_operand" "")))
(set (match_operand:QI 3 "reg_or_mem_operand" "")
(set (match_operand:QI 3 "nonimmediate_operand" "")
(umod:QI (match_dup 1) (match_dup 2)))])]
""
"
......@@ -1395,15 +1388,15 @@
;; way to do this, so just restrict operand 0 and 1 to be in registers.
(define_insn "udivmoddiqi4_internal"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "reg_or_mem_operand" "0")
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "g")] 0))]
""
"deib %2,%0")
(define_insn "udivmoddiqi4"
[(set (subreg:QI (match_operand:DI 0 "register_operand" "=r") 1)
(truncate:QI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
(zero_extend:DI (match_operand:QI 2 "nonimmediate_operand" "g")))))
(truncate:QI (udiv:DI (match_operand:DI 1 "register_operand" "0")
(zero_extend:DI (match_operand:QI 2 "nonimmediate_operand" "rm")))))
(set (subreg:QI (match_operand:DI 3 "register_operand" "=0") 0)
(truncate:QI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
""
......@@ -1412,14 +1405,14 @@
;;- Divide instructions.
(define_insn "divdf3"
[(set (match_operand:DF 0 "general_operand" "=lm")
[(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
(div:DF (match_operand:DF 1 "general_operand" "0")
(match_operand:DF 2 "general_operand" "lmF")))]
"TARGET_32081"
"divl %2,%0")
(define_insn "divsf3"
[(set (match_operand:SF 0 "general_operand" "=fm")
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
(div:SF (match_operand:SF 1 "general_operand" "0")
(match_operand:SF 2 "general_operand" "fmF")))]
"TARGET_32081"
......@@ -1427,21 +1420,21 @@
;; See note 1
(define_insn "divsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(div:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "g")))]
""
"quod %2,%0")
(define_insn "divhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(div:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:HI 2 "general_operand" "g")))]
""
"quow %2,%0")
(define_insn "divqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(div:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
......@@ -1451,21 +1444,21 @@
;; See note 1
(define_insn "modsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(mod:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "g")))]
""
"remd %2,%0")
(define_insn "modhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(mod:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:HI 2 "general_operand" "g")))]
""
"remw %2,%0")
(define_insn "modqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(mod:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
......@@ -1476,7 +1469,7 @@
;; See note 1
(define_insn "andsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(and:SI (match_operand:SI 1 "general_operand" "%0")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1509,7 +1502,7 @@
}")
(define_insn "andhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(and:HI (match_operand:HI 1 "general_operand" "%0")
(match_operand:HI 2 "general_operand" "g")))]
""
......@@ -1530,7 +1523,7 @@
}")
(define_insn "andqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(and:QI (match_operand:QI 1 "general_operand" "%0")
(match_operand:QI 2 "general_operand" "g")))]
""
......@@ -1538,21 +1531,21 @@
;; See note 1
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
(match_operand:SI 2 "general_operand" "0")))]
""
"bicd %1,%0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
(match_operand:HI 2 "general_operand" "0")))]
""
"bicw %1,%0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
(match_operand:QI 2 "general_operand" "0")))]
""
......@@ -1562,7 +1555,7 @@
;; See note 1
(define_insn "iorsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ior:SI (match_operand:SI 1 "general_operand" "%0")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1578,7 +1571,7 @@
}")
(define_insn "iorhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ior:HI (match_operand:HI 1 "general_operand" "%0")
(match_operand:HI 2 "general_operand" "g")))]
""
......@@ -1591,7 +1584,7 @@
}")
(define_insn "iorqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(ior:QI (match_operand:QI 1 "general_operand" "%0")
(match_operand:QI 2 "general_operand" "g")))]
""
......@@ -1601,7 +1594,7 @@
;; See note 1
(define_insn "xorsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(xor:SI (match_operand:SI 1 "general_operand" "%0")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1617,7 +1610,7 @@
}")
(define_insn "xorhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(xor:HI (match_operand:HI 1 "general_operand" "%0")
(match_operand:HI 2 "general_operand" "g")))]
""
......@@ -1630,27 +1623,27 @@
}")
(define_insn "xorqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(xor:QI (match_operand:QI 1 "general_operand" "%0")
(match_operand:QI 2 "general_operand" "g")))]
""
"xorb %2,%0")
(define_insn "negdf2"
[(set (match_operand:DF 0 "general_operand" "=lm<")
[(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
(neg:DF (match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
"negl %1,%0")
(define_insn "negsf2"
[(set (match_operand:SF 0 "general_operand" "=fm<")
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
(neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
"negf %1,%0")
(define_insn "negdi2"
[(set (match_operand:DI 0 "general_operand" "=ro")
(neg:DI (match_operand:DI 1 "general_operand" "ro")))]
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
(neg:DI (match_operand:DI 1 "nonimmediate_operand" "ro")))]
""
"*
{
......@@ -1678,38 +1671,38 @@
;; See note 1
(define_insn "negsi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(neg:SI (match_operand:SI 1 "general_operand" "g")))]
""
"negd %1,%0")
(define_insn "neghi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(neg:HI (match_operand:HI 1 "general_operand" "g")))]
""
"negw %1,%0")
(define_insn "negqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(neg:QI (match_operand:QI 1 "general_operand" "g")))]
""
"negb %1,%0")
;; See note 1
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(not:SI (match_operand:SI 1 "general_operand" "g")))]
""
"comd %1,%0")
(define_insn "one_cmplhi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(not:HI (match_operand:HI 1 "general_operand" "g")))]
""
"comw %1,%0")
(define_insn "one_cmplqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(not:QI (match_operand:QI 1 "general_operand" "g")))]
""
"comb %1,%0")
......@@ -1723,7 +1716,7 @@
;; alternative 0 never matches on the 32532
;; See note 1
(define_insn "ashlsi3"
[(set (match_operand:SI 0 "general_operand" "=g,g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(ashift:SI (match_operand:SI 1 "general_operand" "r,0")
(match_operand:SI 2 "general_operand" "I,g")))]
""
......@@ -1735,7 +1728,7 @@
}")
(define_insn "ashlhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashift:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1754,7 +1747,7 @@
}")
(define_insn "ashlqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(ashift:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1774,7 +1767,7 @@
;; Arithmetic right shift on the 32k works by negating the shift count.
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1785,21 +1778,21 @@
}")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"ashd %n2,%0")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
""
"ashd %2,%0")
(define_expand "ashrhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1810,21 +1803,21 @@
}")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"ashw %n2,%0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
""
"ashw %2,%0")
(define_expand "ashrqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1835,16 +1828,16 @@
}")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"ashb %n2,%0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
""
"ashb %2,%0")
......@@ -1852,7 +1845,7 @@
;; Logical right shift on the 32k works by negating the shift count.
(define_expand "lshrsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1863,21 +1856,21 @@
}")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"lshd %n2,%0")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
""
"lshd %2,%0")
(define_expand "lshrhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1888,21 +1881,21 @@
}")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"lshw %n2,%0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
""
"lshw %2,%0")
(define_expand "lshrqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1913,16 +1906,16 @@
}")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"lshb %n2,%0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
""
"lshb %2,%0")
......@@ -1930,21 +1923,21 @@
;; See note 1
(define_insn "rotlsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(rotate:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "g")))]
""
"rotd %2,%0")
(define_insn "rotlhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(rotate:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "g")))]
""
"rotw %2,%0")
(define_insn "rotlqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(rotate:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1952,7 +1945,7 @@
;; Right rotate on the 32k works by negating the shift count.
(define_expand "rotrsi3"
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(rotatert:SI (match_operand:SI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1963,21 +1956,21 @@
}")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(rotatert:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"rotd %n2,%0")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(rotatert:SI (match_operand:SI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
""
"rotd %2,%0")
(define_expand "rotrhi3"
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(rotatert:HI (match_operand:HI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -1988,21 +1981,21 @@
}")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(rotatert:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"rotw %n2,%0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(rotatert:HI (match_operand:HI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
""
"rotw %2,%0")
(define_expand "rotrqi3"
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(rotatert:QI (match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "general_operand" "g")))]
""
......@@ -2013,16 +2006,16 @@
}")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(rotatert:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"rotb %n2,%0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(rotatert:QI (match_operand:QI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "general_operand" "r"))))]
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
""
"rotb %2,%0")
......@@ -2031,7 +2024,7 @@
;; because we don't want pushl $1 turned into pushad 1.
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(match_operand:QI 1 "address_operand" "p"))]
""
"*
......@@ -2075,7 +2068,7 @@
;; See note 1
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
(const_int 1)
(match_operand:SI 1 "general_operand" "g"))
(const_int 1))]
......@@ -2084,7 +2077,7 @@
;; See note 1
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
(const_int 1)
(match_operand:SI 1 "general_operand" "g"))
(const_int 0))]
......@@ -2093,7 +2086,7 @@
;; See note 1
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "+g")
[(set (match_operand:SI 0 "nonimmediate_operand" "+rm")
(xor:SI (ashift:SI (const_int 1)
(match_operand:SI 1 "general_operand" "g"))
(match_dup 0)))]
......@@ -2102,7 +2095,7 @@
;; See note 1
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(xor:QI (subreg:QI
(ashift:SI (const_int 1)
(match_operand:QI 1 "general_operand" "g")) 0)
......@@ -2114,7 +2107,7 @@
(define_insn ""
[(set (cc0)
(zero_extract (match_operand:SI 0 "general_operand" "rm")
(zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm")
(const_int 1)
(match_operand:SI 1 "general_operand" "g")))]
""
......@@ -2137,7 +2130,7 @@
;; enough on the 32532 that such hacks are not needed.
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=ro")
[(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "const_int_operand" "i")))]
......@@ -2189,10 +2182,10 @@
;; to allow/disallow the use of these instructions.
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(zero_extract:SI (match_operand:SI 1 "register_operand" "g")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "general_operand" "rK")))]
(match_operand:SI 3 "nonmemory_operand" "rK")))]
"TARGET_BITFIELD"
"*
{ if (GET_CODE (operands[3]) == CONST_INT)
......@@ -2201,10 +2194,10 @@
}")
(define_insn "extzv"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(zero_extract:SI (match_operand:QI 1 "general_operand" "g")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "general_operand" "rK")))]
(match_operand:SI 3 "nonmemory_operand" "rK")))]
"TARGET_BITFIELD"
"*
{ if (GET_CODE (operands[3]) == CONST_INT)
......@@ -2215,8 +2208,8 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "general_operand" "rn"))
(match_operand:SI 3 "general_operand" "rm"))]
(match_operand:SI 2 "nonmemory_operand" "rn"))
(match_operand:SI 3 "nonimmediate_operand" "rm"))]
"TARGET_BITFIELD"
"*
{ if (GET_CODE (operands[2]) == CONST_INT)
......@@ -2240,12 +2233,12 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "general_operand" "rK"))
(match_operand:SI 3 "general_operand" "rm"))]
(match_operand:SI 2 "nonmemory_operand" "rK"))
(match_operand:SI 3 "nonimmediate_operand" "rm"))]
"TARGET_BITFIELD"
"*
{ if (GET_CODE (operands[2]) == CONST_INT)
{
{
if (INTVAL (operands[1]) <= 8)
return \"inssb %3,%0,%2,%1\";
else if (INTVAL (operands[1]) <= 16)
......@@ -2257,10 +2250,10 @@
}")
(define_insn "insv"
[(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+rm")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "general_operand" "rK"))
(match_operand:SI 3 "general_operand" "rm"))]
(match_operand:SI 2 "nonmemory_operand" "rK"))
(match_operand:SI 3 "nonimmediate_operand" "rm"))]
"TARGET_BITFIELD"
"*
{ if (GET_CODE (operands[2]) == CONST_INT)
......@@ -2492,7 +2485,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(ne (match_operand:SI 0 "general_operand" "+g")
(ne (match_operand:SI 0 "nonimmediate_operand" "+rm")
(match_operand:SI 1 "const_int_operand" "i"))
(label_ref (match_operand 2 "" ""))
(pc)))
......@@ -2505,7 +2498,7 @@
(define_insn ""
[(set (pc)
(if_then_else
(ne (match_operand:SI 0 "general_operand" "+g")
(ne (match_operand:SI 0 "nonimmediate_operand" "+rm")
(match_operand:SI 1 "const_int_operand" "i"))
(label_ref (match_operand 2 "" ""))
(pc)))
......@@ -2636,32 +2629,32 @@
"ret 0")
(define_insn "abssf2"
[(set (match_operand:SF 0 "general_operand" "=fm<")
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
(abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
"absf %1,%0")
(define_insn "absdf2"
[(set (match_operand:DF 0 "general_operand" "=lm<")
[(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
(abs:DF (match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
"absl %1,%0")
;; See note 1
(define_insn "abssi2"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(abs:SI (match_operand:SI 1 "general_operand" "g")))]
""
"absd %1,%0")
(define_insn "abshi2"
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(abs:HI (match_operand:HI 1 "general_operand" "g")))]
""
"absw %1,%0")
(define_insn "absqi2"
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(abs:QI (match_operand:QI 1 "general_operand" "g")))]
""
"absb %1,%0")
......@@ -2690,7 +2683,7 @@
;; Scondi instructions
(define_insn "seq"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(eq:SI (cc0) (const_int 0)))]
""
"*
......@@ -2702,7 +2695,7 @@
}")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(eq:HI (cc0) (const_int 0)))]
""
"*
......@@ -2714,7 +2707,7 @@
}")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(eq:QI (cc0) (const_int 0)))]
""
"*
......@@ -2726,7 +2719,7 @@
}")
(define_insn "sne"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(ne:SI (cc0) (const_int 0)))]
""
"*
......@@ -2738,7 +2731,7 @@
}")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(ne:HI (cc0) (const_int 0)))]
""
"*
......@@ -2750,7 +2743,7 @@
}")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(ne:QI (cc0) (const_int 0)))]
""
"*
......@@ -2762,145 +2755,145 @@
}")
(define_insn "sgt"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(gt:SI (cc0) (const_int 0)))]
""
"sgtd %0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(gt:HI (cc0) (const_int 0)))]
""
"sgtw %0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(gt:QI (cc0) (const_int 0)))]
""
"sgtb %0")
(define_insn "sgtu"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(gtu:SI (cc0) (const_int 0)))]
""
"shid %0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(gtu:HI (cc0) (const_int 0)))]
""
"shiw %0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(gtu:QI (cc0) (const_int 0)))]
""
"shib %0")
(define_insn "slt"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(lt:SI (cc0) (const_int 0)))]
""
"sltd %0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(lt:HI (cc0) (const_int 0)))]
""
"sltw %0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(lt:QI (cc0) (const_int 0)))]
""
"sltb %0")
(define_insn "sltu"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(ltu:SI (cc0) (const_int 0)))]
""
"slod %0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(ltu:HI (cc0) (const_int 0)))]
""
"slow %0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(ltu:QI (cc0) (const_int 0)))]
""
"slob %0")
(define_insn "sge"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(ge:SI (cc0) (const_int 0)))]
""
"sged %0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(ge:HI (cc0) (const_int 0)))]
""
"sgew %0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(ge:QI (cc0) (const_int 0)))]
""
"sgeb %0")
(define_insn "sgeu"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(geu:SI (cc0) (const_int 0)))]
""
"shsd %0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(geu:HI (cc0) (const_int 0)))]
""
"shsw %0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(geu:QI (cc0) (const_int 0)))]
""
"shsb %0")
(define_insn "sle"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(le:SI (cc0) (const_int 0)))]
""
"sled %0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(le:HI (cc0) (const_int 0)))]
""
"slew %0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(le:QI (cc0) (const_int 0)))]
""
"sleb %0")
(define_insn "sleu"
[(set (match_operand:SI 0 "general_operand" "=g<")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(leu:SI (cc0) (const_int 0)))]
""
"slsd %0")
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=g<")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
(leu:HI (cc0) (const_int 0)))]
""
"slsw %0")
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=g<")
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
(leu:QI (cc0) (const_int 0)))]
""
"slsb %0")
......@@ -2908,7 +2901,7 @@
;; ffs instructions
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=ro")
[(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
(minus:SI
(plus:SI (ffs:SI (zero_extract:SI
(match_operand:SI 1 "general_operand" "g")
......@@ -2920,7 +2913,7 @@
"ffsd %1,%0; bfc 1f; addqd %$-1,%0; 1:")
(define_expand "ffssi2"
[(set (match_operand:SI 0 "general_operand" "=g") (const_int 0))
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (const_int 0))
(set (match_dup 0)
(minus:SI
(plus:SI (ffs:SI (zero_extract:SI
......
gcc/config/ns32k/xm-genix.h
/* Config file for ns32k running system V. */
#include "ns32k/xm-ns32k.h"
#define memcpy(src,dst,len) bcopy ((dst),(src),(len))
#define memset gcc_memset
#define memcmp(left,right,len) bcmp ((left),(right),(len))
#define USG
gcc/config/ns32k/xm-netbsd.h
/* Configuration for GCC for ns32k running NetBSD as host. */
#include <ns32k/xm-ns32k.h>
/* ns32k/xm-ns32k.h defines these macros, but we don't need them */
#undef memcmp
#undef memcpy
#undef memset
/* Nothing needs to be done */
gcc/config/ns32k/xm-ns32k.h
......@@ -36,7 +36,3 @@ Boston, MA 02111-1307, USA. */
/* Arguments to use with `exit'. */
#define SUCCESS_EXIT_CODE 0
#define FATAL_EXIT_CODE 33
#define memcpy(src,dst,len) bcopy ((dst),(src),(len))
#define memset gcc_memset
#define memcmp(left,right,len) bcmp ((left),(right),(len))
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