config.gcc: Add stormy16-*-elf case.

	* config.gcc: Add stormy16-*-elf case.
	* config/stormy16/stormy-abi: New file.
	* config/stormy16/stormy16-lib2.c: New file.
	* config/stormy16/stormy16-protos.h: New file.
	* config/stormy16/stormy16.c: New file.
	* config/stormy16/stormy16.h: New file.
	* config/stormy16/stormy16.md: New file.
	* config/stormy16/t-stormy16: New file.

From-SVN: r45173

gcc/ChangeLog

+2001-08-22  Geoffrey Keating  <geoffk@redhat.com>
+
+	* config.gcc: Add stormy16-*-elf case.
+	* config/stormy16/stormy-abi: New file.
+	* config/stormy16/stormy16-lib2.c: New file.
+	* config/stormy16/stormy16-protos.h: New file.
+	* config/stormy16/stormy16.c: New file.
+	* config/stormy16/stormy16.h: New file.
+	* config/stormy16/stormy16.md: New file.
+	* config/stormy16/t-stormy16: New file.
+
 Sat Aug 25 15:46:51 CEST 2001  Jan Hubicka  <jh@suse.cz>
 
 	* i386.h (no-accumulate-outgoing-args): Use proper mask.

gcc/config.gcc

@@ -3099,6 +3099,10 @@ sparc64-*-linux*)		# 64-bit Sparc's running GNU/Linux
 	fi
 	float_format=sparc
 	;;
+stormy16-*-elf)
+	tmake_file="stormy16/t-stormy16"
+	extra_parts="crtbegin.o crtend.o"
+	;;
 strongarm-*-elf*)
 	tm_file=arm/strongarm-elf.h
 	tmake_file=arm/t-strongarm-elf

gcc/config/stormy16/stormy-abi

+Stormy16 ABI
+************
+
+!!!!! NOTE !!!!!
+This document is a draft and is subject to change.
+!!!!! NOTE !!!!!
+
+This part of the file describes the conventions required to write
+ELF object files that are link-compatible with the ones produced
+by the GNU toolchains.
+
+Bit and Byte Ordering
+=====================
+
+This implementation is little-endian.   Bits are numbered starting 
+from 0 being the LSB.
+
+In this document, 'word' means 16 bits.
+
+Calling Sequence
+================
+
+The registers are allocated as follows:
+
+Register	Purpose
+-------------------------------------------------------------------
+r0, r1		Call-volatile.  May be changed during the execution
+		of a call instruction.
+r2 through r9	Argument passing; call-clobbered.
+r10 through r13	Call-saved.
+r14		Program status word.
+r15		Stack pointer.
+
+
+The return value of a procedure is returned in r2-r9 if it fits,
+otherwise a pointer is passed as a `hidden' first argument
+and the return value is placed there.
+
+Arguments are passed in registers starting in r2, then on the stack.
+Arguments of size not a multiple of a word are padded to whole words.
+If an argument would otherwise be passed partially in registers, and
+partially on the stack, the whole of it is passed on the stack.  The
+last argument is pushed on the stack first.
+
+After a procedure's arguments are pushed on the stack,
+the return address is pushed on the stack, as if by the call
+instruction.  The return address is on the top of the stack when
+a procedure is called.
+
+Objects whose size is a multiple of 16 bits are aligned to a 16-bit
+boundary.
+
+Pointers are 16 bits, referencing addresses between 0 and 0xFFFF.
+
+Procedure pointers are also implemented as 16-bit pointers.
+
+Variable Argument Functions
+===========================
+
+The C type 'va_list' is implemented as a structure, as follows:
+
+struct {
+  char *base;
+  unsigned count;
+}
+
+Both fields are 16 bits.  An argument of size N bytes
+(N will be even) is accessed as if by the following code:
+
+char *result;
+if (count + N > 16)
+  {
+    if (count < 16)
+      count = 16;
+    result = base - (count + N - 16 + 4);
+  }
+else
+  {
+    result = base + count;
+  }
+count += N;
+/* The argument is at `*result'.  */
+
+
+One implementation of this is if a variadic function first
+pushes registers 2 through 9 in sequence at entry, and
+sets 'base' to the address of the first word pushed, 
+producing a stack that appears like:
+
+SP ->
+	[other data]
+	r9
+	r8
+	r7
+	r6
+	r5
+	r4
+	r3
+count-> r2
+	Return address (two words)
+	9th procedure parameter word
+	10th procedure parameter word
+	...
+	last procedure parameter word
+
+and initialises 'count' to be the number of bytes of non-variable
+arguments to the function.
+
+ELF File Format
+===============
+
+ELF file header
+---------------
+
+Stormy16 ELF files are distinguished by the value EM_STORMY16 in
+the e_machine field of the ELF file header:
+
+#define EM_STORMY16	        0xad45
+
+DWARF Register Number Mapping
+-----------------------------
+
+Registers r0 through r15 are mapped to numbers 0 through 15.
+
+Relocations
+-----------
+
+RELA relocs are used exclusively.  The relocation types defined are:
+
+Name			Value	Field	Calculation	Overflow
+----------------------------------------------------------------
+R_STORMY16_NONE		0	none	none		none
+R_STORMY16_32		1	32	S + A		none
+R_STORMY16_16		2	16	S + A		unsigned
+R_STORMY16_8		3	8	S + A		unsigned
+R_STORMY16_PC32		4	32	S + A - P	none
+R_STORMY16_PC16		5	16	S + A - P	signed
+R_STORMY16_PC8		6	8	S + A - P	signed
+R_STORMY16_REL_12	7	16:12:0	S + A - P	signed
+R_STORMY16_24		8	32:23:1	(S + A) >> 1	unsigned
+R_STORMY16_GNU_VTINHERIT 9	n/a	n/a		n/a
+R_STORMY16_GNU_VTENTRY	10	n/a	n/a		n/a
+
+In the 'Calculation' column, 'S' is the value of the symbol to which
+the reloc refers, 'A' is the addend, and 'P' represents the place of
+the storage unit being relocated.
+
+In the 'Field' column, the first number indicates whether the
+relocation refers to a byte, word or doubleword.  The second number,
+if any, indicates the size of the bitfield into which the relocation
+is to occur (and also the size for overflow checking).  The third
+number indicates the first bit of the bitfield in the word or
+doubleword, counting the LSB as bit 0.

gcc/config/stormy16/stormy16-lib2.c

+typedef		 int HItype		__attribute__ ((mode (HI)));
+typedef		 int SItype		__attribute__ ((mode (SI)));
+typedef unsigned int USItype		__attribute__ ((mode (SI)));
+
+typedef int word_type			__attribute__ ((mode (__word__)));
+
+USItype
+udivmodsi4(USItype num, USItype den, word_type modwanted)
+{
+  USItype bit = 1;
+  USItype res = 0;
+
+  while (den < num && bit && !(den & (1L<<31)))
+    {
+      den <<=1;
+      bit <<=1;
+    }
+  while (bit)
+    {
+      if (num >= den)
+	{
+	  num -= den;
+	  res |= bit;
+	}
+      bit >>=1;
+      den >>=1;
+    }
+  if (modwanted) return num;
+  return res;
+}
+
+
+
+SItype
+__divsi3 (SItype a, SItype b)
+{
+  word_type neg = 0;
+  SItype res;
+
+  if (a < 0)
+    {
+      a = -a;
+      neg = !neg;
+    }
+
+  if (b < 0)
+    {
+      b = -b;
+      neg = !neg;
+    }
+
+  res = udivmodsi4 (a, b, 0);
+
+  if (neg)
+    res = -res;
+
+  return res;
+}
+
+
+
+SItype
+__modsi3 (SItype a, SItype b)
+{
+  word_type neg = 0;
+  SItype res;
+
+  if (a < 0)
+    {
+      a = -a;
+      neg = 1;
+    }
+
+  if (b < 0)
+    b = -b;
+
+  res = udivmodsi4 (a, b, 1);
+
+  if (neg)
+    res = -res;
+
+  return res;
+}
+
+
+
+
+SItype
+__udivsi3 (SItype a, SItype b)
+{
+  return udivmodsi4 (a, b, 0);
+}
+
+
+
+SItype
+__umodsi3 (SItype a, SItype b)
+{
+  return udivmodsi4 (a, b, 1);
+}
+
+SItype
+__ashlsi3 (SItype a, SItype b)
+{
+  word_type i;
+  
+  if (b & 16)
+    a <<= 16;
+  if (b & 8)
+    a <<= 8;
+  for (i = (b & 0x7); i > 0; --i)
+    a <<= 1;
+  return a;
+}
+
+SItype
+__ashrsi3 (SItype a, SItype b)
+{
+  word_type i;
+  
+  if (b & 16)
+    a >>= 16;
+  if (b & 8)
+    a >>= 8;
+  for (i = (b & 0x7); i > 0; --i)
+    a >>= 1;
+  return a;
+}
+
+USItype
+__lshrsi3 (USItype a, USItype b)
+{
+  word_type i;
+  
+  if (b & 16)
+    a >>= 16;
+  if (b & 8)
+    a >>= 8;
+  for (i = (b & 0x7); i > 0; --i)
+    a >>= 1;
+  return a;
+}

gcc/config/stormy16/stormy16-protos.h

+/* Prototypes for exported functions defined in stormy16.c
+   Copyright (C) 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+
+extern struct stormy16_stack_layout 
+		    stormy16_compute_stack_layout PARAMS((void));
+extern void         stormy16_expand_prologue      PARAMS ((void));
+extern void         stormy16_expand_epilogue      PARAMS ((void));
+extern int	stormy16_initial_elimination_offset PARAMS ((int, int));
+extern int	direct_return PARAMS ((void));
+extern int	stormy16_interrupt_function_p PARAMS ((void));
+extern int	stormy16_epilogue_uses PARAMS ((int));
+
+#if defined (TREE_CODE)
+#  if defined (HAVE_MACHINE_MODES)
+extern CUMULATIVE_ARGS stormy16_function_arg_advance 
+  PARAMS ((CUMULATIVE_ARGS, enum machine_mode, tree, int));
+#  endif
+extern void    stormy16_setup_incoming_varargs 
+  PARAMS ((CUMULATIVE_ARGS, int, tree, int *));
+extern tree    stormy16_build_va_list PARAMS ((void));
+extern void    stormy16_encode_section_info PARAMS ((tree));
+#endif
+
+#if defined (TREE_CODE) && defined (RTX_CODE)
+extern void    stormy16_expand_builtin_va_start PARAMS ((int, tree, rtx));
+extern rtx     stormy16_expand_builtin_va_arg PARAMS ((tree, tree));
+extern void    stormy16_initialize_trampoline PARAMS ((rtx, rtx, rtx));
+extern rtx     stormy16_function_value PARAMS ((tree, tree));
+#endif
+
+#ifdef RTX_CODE
+extern void stormy16_emit_cbranch PARAMS ((enum rtx_code, rtx));
+extern char * stormy16_output_cbranch_hi PARAMS ((rtx, const char *, int, 
+						  rtx));
+extern char * stormy16_output_cbranch_si PARAMS ((rtx, const char *, int, 
+						  rtx));
+extern int stormy16_mode_dependent_address_p PARAMS ((rtx));
+extern int stormy16_extra_constraint_p PARAMS ((rtx, int));
+
+extern void stormy16_print_operand          PARAMS ((FILE *, rtx, int));
+extern void stormy16_print_operand_address  PARAMS ((FILE *, rtx));
+
+extern void stormy16_expand_casesi PARAMS ((rtx, rtx, rtx, rtx, rtx));
+extern void stormy16_output_addr_vec PARAMS ((FILE *, rtx, rtx));
+extern void stormy16_expand_call PARAMS ((rtx, rtx, rtx));
+#endif
+
+#if defined (HAVE_MACHINE_MODES) && defined (RTX_CODE)
+extern int stormy16_ineqsi_operator PARAMS ((rtx, enum machine_mode));
+extern int equality_operator PARAMS ((rtx, enum machine_mode));
+extern int inequality_operator PARAMS ((rtx, enum machine_mode));
+extern void stormy16_split_cbranch PARAMS ((enum machine_mode, 
+					   rtx, rtx, rtx, rtx));
+extern int  short_memory_operand PARAMS ((rtx, enum machine_mode));
+extern enum reg_class stormy16_secondary_reload_class 
+  PARAMS ((enum reg_class, enum machine_mode, rtx));
+extern int  stormy16_carry_plus_operand PARAMS ((rtx, enum machine_mode));
+extern enum reg_class stormy16_preferred_reload_class 
+  PARAMS ((rtx, enum reg_class));
+extern int stormy16_legitimate_address_p 
+   PARAMS ((enum machine_mode, rtx, int));
+extern void stormy16_split_move PARAMS ((enum machine_mode, rtx, rtx));
+extern void stormy16_expand_move PARAMS ((enum machine_mode, rtx, rtx));
+extern void stormy16_expand_arith PARAMS ((enum machine_mode, enum rtx_code, 
+					   rtx, rtx, rtx, rtx));
+extern int  shift_operator PARAMS ((rtx, enum machine_mode));
+extern const char * stormy16_output_shift PARAMS ((enum machine_mode, 
+						   enum rtx_code, 
+						   rtx, rtx, rtx));
+#endif
+

gcc/config/stormy16/stormy16.c

+/* Stormy16 target functions.
+   Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#include "config.h"
+#include "system.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "recog.h"
+#include "toplev.h"
+#include "obstack.h"
+#include "tree.h"
+#include "expr.h"
+#include "optabs.h"
+#include "output.h"
+#include "except.h"
+#include "function.h"
+#include "target.h"
+#include "target-def.h"
+#include "tm_p.h"
+
+static rtx emit_addhi3_postreload PARAMS ((rtx, rtx, rtx));
+
+/* Define the information needed to generate branch and scc insns.  This is
+   stored from the compare operation.  */
+struct rtx_def * stormy16_compare_op0;
+struct rtx_def * stormy16_compare_op1;
+
+/* Return 1 if this is a LT, GE, LTU, or GEU operator.  */
+
+int
+stormy16_ineqsi_operator (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  enum rtx_code code = GET_CODE (op);
+  
+  return ((mode == VOIDmode || GET_MODE (op) == mode)
+	  && (code == LT || code == GE || code == LTU || code == GEU));
+}
+
+/* Return 1 if this is an EQ or NE operator.  */
+
+int
+equality_operator (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  return ((mode == VOIDmode || GET_MODE (op) == mode)
+	  && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
+}
+
+/* Return 1 if this is a comparison operator but not an EQ or NE operator.  */
+
+int
+inequality_operator (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  return comparison_operator (op, mode) && ! equality_operator (op, mode);
+}
+
+/* Branches are handled as follows:
+
+   1. HImode compare-and-branches.  The machine supports these
+      natively, so the appropriate pattern is emitted directly.
+
+   2. SImode EQ and NE.  These are emitted as pairs of HImode
+      compare-and-branches.      
+
+   3. SImode LT, GE, LTU and GEU.  These are emitted as a sequence
+      of a SImode subtract followed by a branch (not a compare-and-branch),
+      like this:
+      sub
+      sbc
+      blt
+
+   4. SImode GT, LE, GTU, LEU.  These are emitted as a sequence like:
+      sub
+      sbc
+      blt
+      or
+      bne
+*/
+
+/* Emit a branch of kind CODE to location LOC.  */
+
+void
+stormy16_emit_cbranch (code, loc)
+     enum rtx_code code;
+     rtx loc;
+{
+  rtx op0 = stormy16_compare_op0;
+  rtx op1 = stormy16_compare_op1;
+  rtx condition_rtx, loc_ref, branch, cy_clobber;
+  rtvec vec;
+  enum machine_mode mode;
+  
+  mode = GET_MODE (op0);
+  if (mode != HImode && mode != SImode)
+    abort ();
+
+  if (mode == SImode
+      && (code == GT || code == LE || code == GTU || code == LEU))
+    {
+      int unsigned_p = (code == GTU || code == LEU);
+      int gt_p = (code == GT || code == GTU);
+      rtx lab;
+      
+      if (gt_p)
+	lab = gen_label_rtx ();
+      stormy16_emit_cbranch (unsigned_p ? LTU : LT, gt_p ? lab : loc);
+      /* This should be generated as a comparison against the temporary
+	 created by the previous insn, but reload can't handle that.  */
+      stormy16_emit_cbranch (gt_p ? NE : EQ, loc);
+      if (gt_p)
+	emit_label (lab);
+      return;
+    }
+  else if (mode == SImode 
+	   && (code == NE || code == EQ)
+	   && op1 != const0_rtx)
+    {
+      rtx lab;
+      int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD;
+      int i;
+      
+      if (code == EQ)
+	lab = gen_label_rtx ();
+      
+      for (i = 0; i < num_words - 1; i++)
+	{
+	  stormy16_compare_op0 = simplify_gen_subreg (word_mode, op0, mode, 
+						      i * UNITS_PER_WORD);
+	  stormy16_compare_op1 = simplify_gen_subreg (word_mode, op1, mode, 
+						      i * UNITS_PER_WORD);
+	  stormy16_emit_cbranch (NE, code == EQ ? lab : loc);
+	}
+      stormy16_compare_op0 = simplify_gen_subreg (word_mode, op0, mode, 
+						  i * UNITS_PER_WORD);
+      stormy16_compare_op1 = simplify_gen_subreg (word_mode, op1, mode, 
+						  i * UNITS_PER_WORD);
+      stormy16_emit_cbranch (code, loc);
+
+      if (code == EQ)
+	emit_label (lab);
+      return;
+    }
+
+  /* We can't allow reload to try to generate any reload after a branch,
+     so when some register must match we must make the temporary ourselves.  */
+  if (mode != HImode)
+    {
+      rtx tmp;
+      tmp = gen_reg_rtx (mode);
+      emit_move_insn (tmp, op0);
+      op0 = tmp;
+    }
+
+  condition_rtx = gen_rtx (code, mode, op0, op1);
+  loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
+  branch = gen_rtx_SET (VOIDmode, pc_rtx,
+			gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
+					      loc_ref, pc_rtx));
+
+  cy_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (BImode));
+
+  if (mode == HImode)
+    vec = gen_rtvec (2, branch, cy_clobber);
+  else if (code == NE || code == EQ)
+    vec = gen_rtvec (2, branch, gen_rtx_CLOBBER (VOIDmode, op0));
+  else
+    {
+      rtx sub;
+#if 0
+      sub = gen_rtx_SET (VOIDmode, op0, gen_rtx_MINUS (SImode, op0, op1));
+#else
+      sub = gen_rtx_CLOBBER (SImode, op0);
+#endif
+      vec = gen_rtvec (3, branch, sub, cy_clobber);
+    }
+
+  emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
+}
+
+/* Take a SImode conditional branch, one of GT/LE/GTU/LEU, and split
+   the arithmetic operation.  Most of the work is done by
+   stormy16_expand_arith.  */
+
+void
+stormy16_split_cbranch (mode, label, comparison, dest, carry)
+     enum machine_mode mode;
+     rtx label;
+     rtx comparison;
+     rtx dest;
+     rtx carry;
+{
+  rtx op0 = XEXP (comparison, 0);
+  rtx op1 = XEXP (comparison, 1);
+  rtx seq;
+  rtx compare;
+  
+  start_sequence ();
+  stormy16_expand_arith (mode, COMPARE, dest, op0, op1, carry);
+  seq = gen_sequence ();
+  end_sequence ();
+  compare = SET_SRC (XVECEXP (PATTERN (XVECEXP (seq, 0, XVECLEN (seq, 0) - 1)),
+			      0, 0));
+  PUT_CODE (XEXP (compare, 0), GET_CODE (comparison));
+  XEXP (compare, 1) = gen_rtx_LABEL_REF (VOIDmode, label);
+  emit_insn (seq);
+}
+
+
+/* Return the string to output a conditional branch to LABEL, which is
+   the operand number of the label.
+
+   OP is the conditional expression, or NULL for branch-always.
+
+   REVERSED is non-zero if we should reverse the sense of the comparison.
+
+   INSN is the insn.  */
+
+char *
+stormy16_output_cbranch_hi (op, label, reversed, insn)
+     rtx op;
+     const char * label;
+     int reversed;
+     rtx insn;
+{
+  static char string[64];
+  int need_longbranch = (op != NULL_RTX
+			 ? get_attr_length (insn) == 8
+			 : get_attr_length (insn) == 4);
+  int really_reversed = reversed ^ need_longbranch;
+  const char *ccode;
+  const char *template;
+  const char *operands;
+  enum rtx_code code;
+  
+  if (! op)
+    {
+      if (need_longbranch)
+	ccode = "jmpf";
+      else
+	ccode = "br";
+      sprintf (string, "%s %s", ccode, label);
+      return string;
+    }
+
+  code = GET_CODE (op);
+
+  if (GET_CODE (XEXP (op, 0)) != REG)
+    {
+      code = swap_condition (code);
+      operands = "%3,%2";
+    }
+  else
+      operands = "%2,%3";
+
+  /* Work out which way this really branches.  */
+  if (really_reversed)
+    code = reverse_condition (code);
+
+  switch (code)
+    {
+    case EQ:   ccode = "z";   break;
+    case NE:   ccode = "nz";  break;
+    case GE:   ccode = "ge";  break;
+    case LT:   ccode = "lt";  break;
+    case GT:   ccode = "gt";  break;
+    case LE:   ccode = "le";  break;
+    case GEU:  ccode = "nc";  break;
+    case LTU:  ccode = "c";   break;
+    case GTU:  ccode = "hi";  break;
+    case LEU:  ccode = "ls";  break;
+      
+    default:
+      abort ();
+    }
+
+  if (need_longbranch)
+    template = "b%s %s,.+8 | jmpf %s";
+  else
+    template = "b%s %s,%s";
+  sprintf (string, template, ccode, operands, label);
+  
+  return string;
+}
+
+/* Return the string to output a conditional branch to LABEL, which is
+   the operand number of the label, but suitable for the tail of a
+   SImode branch.
+
+   OP is the conditional expression (OP is never NULL_RTX).
+
+   REVERSED is non-zero if we should reverse the sense of the comparison.
+
+   INSN is the insn.  */
+
+char *
+stormy16_output_cbranch_si (op, label, reversed, insn)
+     rtx op;
+     const char * label;
+     int reversed;
+     rtx insn;
+{
+  static char string[64];
+  int need_longbranch = get_attr_length (insn) >= 8;
+  int really_reversed = reversed ^ need_longbranch;
+  const char *ccode;
+  const char *template;
+  char prevop[16];
+  enum rtx_code code;
+  
+  code = GET_CODE (op);
+
+  /* Work out which way this really branches.  */
+  if (really_reversed)
+    code = reverse_condition (code);
+
+  switch (code)
+    {
+    case EQ:   ccode = "z";   break;
+    case NE:   ccode = "nz";  break;
+    case GE:   ccode = "ge";  break;
+    case LT:   ccode = "lt";  break;
+    case GEU:  ccode = "nc";  break;
+    case LTU:  ccode = "c";   break;
+
+      /* The missing codes above should never be generated.  */
+    default:
+      abort ();
+    }
+
+  switch (code)
+    {
+    case EQ: case NE:
+      {
+	int regnum;
+	
+	if (GET_CODE (XEXP (op, 0)) != REG)
+	  abort ();
+      
+	regnum = REGNO (XEXP (op, 0));
+	sprintf (prevop, "or %s,%s", reg_names[regnum], reg_names[regnum+1]);
+      }
+      break;
+
+    case GE: case LT: case GEU: case LTU:
+      strcpy (prevop, "sbc %2,%3");
+      break;
+
+    default:
+      abort ();
+    }
+
+  if (need_longbranch)
+    template = "%s | b%s .+6 | jmpf %s";
+  else
+    template = "%s | b%s %s";
+  sprintf (string, template, prevop, ccode, label);
+  
+  return string;
+}
+
+/* Many machines have some registers that cannot be copied directly to or from
+   memory or even from other types of registers.  An example is the `MQ'
+   register, which on most machines, can only be copied to or from general
+   registers, but not memory.  Some machines allow copying all registers to and
+   from memory, but require a scratch register for stores to some memory
+   locations (e.g., those with symbolic address on the RT, and those with
+   certain symbolic address on the Sparc when compiling PIC).  In some cases,
+   both an intermediate and a scratch register are required.
+
+   You should define these macros to indicate to the reload phase that it may
+   need to allocate at least one register for a reload in addition to the
+   register to contain the data.  Specifically, if copying X to a register
+   CLASS in MODE requires an intermediate register, you should define
+   `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
+   whose registers can be used as intermediate registers or scratch registers.
+
+   If copying a register CLASS in MODE to X requires an intermediate or scratch
+   register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
+   largest register class required.  If the requirements for input and output
+   reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
+   instead of defining both macros identically.
+
+   The values returned by these macros are often `GENERAL_REGS'.  Return
+   `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
+   to or from a register of CLASS in MODE without requiring a scratch register.
+   Do not define this macro if it would always return `NO_REGS'.
+
+   If a scratch register is required (either with or without an intermediate
+   register), you should define patterns for `reload_inM' or `reload_outM', as
+   required..  These patterns, which will normally be implemented with a
+   `define_expand', should be similar to the `movM' patterns, except that
+   operand 2 is the scratch register.
+
+   Define constraints for the reload register and scratch register that contain
+   a single register class.  If the original reload register (whose class is
+   CLASS) can meet the constraint given in the pattern, the value returned by
+   these macros is used for the class of the scratch register.  Otherwise, two
+   additional reload registers are required.  Their classes are obtained from
+   the constraints in the insn pattern.
+
+   X might be a pseudo-register or a `subreg' of a pseudo-register, which could
+   either be in a hard register or in memory.  Use `true_regnum' to find out;
+   it will return -1 if the pseudo is in memory and the hard register number if
+   it is in a register.
+
+   These macros should not be used in the case where a particular class of
+   registers can only be copied to memory and not to another class of
+   registers.  In that case, secondary reload registers are not needed and
+   would not be helpful.  Instead, a stack location must be used to perform the
+   copy and the `movM' pattern should use memory as a intermediate storage.
+   This case often occurs between floating-point and general registers.  */
+
+enum reg_class
+stormy16_secondary_reload_class (class, mode, x)
+     enum reg_class class;
+     enum machine_mode mode;
+     rtx x;
+{
+  /* This chip has the interesting property that only the first eight
+     registers can be moved to/from memory.  */
+  if ((GET_CODE (x) == MEM
+       || ((GET_CODE (x) == SUBREG || GET_CODE (x) == REG)
+	   && (true_regnum (x) == -1
+	       || true_regnum (x) >= FIRST_PSEUDO_REGISTER)))
+      && ! reg_class_subset_p (class, EIGHT_REGS))
+    return EIGHT_REGS;
+
+  /* When reloading a PLUS, the carry register will be required
+     unless the inc or dec instructions can be used.  */
+  if (stormy16_carry_plus_operand (x, mode))
+    return CARRY_REGS;
+
+  return NO_REGS;
+}
+
+/* Recognise a PLUS that needs the carry register.  */
+int
+stormy16_carry_plus_operand (x, mode)
+     rtx x;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return (GET_CODE (x) == PLUS
+	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && (INTVAL (XEXP (x, 1)) < -4 || INTVAL (XEXP (x, 1)) > 4));
+}
+
+
+enum reg_class
+stormy16_preferred_reload_class (x, class)
+     enum reg_class class;
+     rtx x;
+{
+  if (class == GENERAL_REGS
+      && GET_CODE (x) == MEM)
+    return EIGHT_REGS;
+
+  return class;
+}
+
+#define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET)				\
+ (GET_CODE (X) == CONST_INT						\
+  && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 2048) < 4096)
+
+#define LEGITIMATE_ADDRESS_CONST_INT_P(X, OFFSET)			 \
+ (GET_CODE (X) == CONST_INT						 \
+  && INTVAL (X) + (OFFSET) >= 0						 \
+  && INTVAL (X) + (OFFSET) < 0x8000					 \
+  && (INTVAL (X) + (OFFSET) < 0x100 || INTVAL (X) + (OFFSET) >= 0x7F00))
+
+int
+stormy16_legitimate_address_p (mode, x, strict)
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+     rtx x;
+     int strict;
+{
+  if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0))
+    return 1;
+
+  if (GET_CODE (x) == PLUS
+      && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0))
+    x = XEXP (x, 0);
+  
+  if (GET_CODE (x) == POST_INC
+      || GET_CODE (x) == PRE_DEC)
+    x = XEXP (x, 0);
+  
+  if (GET_CODE (x) == REG && REGNO_OK_FOR_BASE_P (REGNO (x))
+      && (! strict || REGNO (x) < FIRST_PSEUDO_REGISTER))
+    return 1;
+  
+  return 0;
+}
+
+/* Return nonzero if memory address X (an RTX) can have different
+   meanings depending on the machine mode of the memory reference it
+   is used for or if the address is valid for some modes but not
+   others.
+
+   Autoincrement and autodecrement addresses typically have mode-dependent
+   effects because the amount of the increment or decrement is the size of the
+   operand being addressed.  Some machines have other mode-dependent addresses.
+   Many RISC machines have no mode-dependent addresses.
+
+   You may assume that ADDR is a valid address for the machine.  
+   
+   On this chip, this is true if the address is valid with an offset
+   of 0 but not of 6, because in that case it cannot be used as an
+   address for DImode or DFmode, or if the address is a post-increment
+   or pre-decrement address.  */
+int
+stormy16_mode_dependent_address_p (x)
+     rtx x;
+{
+  if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0)
+      && ! LEGITIMATE_ADDRESS_CONST_INT_P (x, 6))
+    return 1;
+  
+  if (GET_CODE (x) == PLUS
+      && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0)
+      && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 6))
+    return 1;
+
+  if (GET_CODE (x) == PLUS)
+    x = XEXP (x, 0);
+
+  if (GET_CODE (x) == POST_INC
+      || GET_CODE (x) == PRE_DEC)
+    return 1;
+
+  return 0;
+}
+
+/* A C expression that defines the optional machine-dependent constraint
+   letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
+   types of operands, usually memory references, for the target machine.
+   Normally this macro will not be defined.  If it is required for a particular
+   target machine, it should return 1 if VALUE corresponds to the operand type
+   represented by the constraint letter C.  If C is not defined as an extra
+   constraint, the value returned should be 0 regardless of VALUE.  */
+int
+stormy16_extra_constraint_p (x, c)
+     rtx x;
+     int c;
+{
+  switch (c)
+    {
+      /* 'Q' is for pushes.  */
+    case 'Q':
+      return (GET_CODE (x) == MEM
+	      && GET_CODE (XEXP (x, 0)) == POST_INC
+	      && XEXP (XEXP (x, 0), 0) == stack_pointer_rtx);
+
+      /* 'R' is for pops.  */
+    case 'R':
+      return (GET_CODE (x) == MEM
+	      && GET_CODE (XEXP (x, 0)) == PRE_DEC
+	      && XEXP (XEXP (x, 0), 0) == stack_pointer_rtx);
+
+      /* 'S' is for immediate memory addresses.  */
+    case 'S':
+      return (GET_CODE (x) == MEM
+	      && GET_CODE (XEXP (x, 0)) == CONST_INT
+	      && stormy16_legitimate_address_p (VOIDmode, XEXP (x, 0), 0));
+
+      /* 'T' is for Rx.  */
+    case 'T':
+      /* Not implemented yet.  */
+      return 0;
+
+      /* 'U' is for CONST_INT values not between 2 and 15 inclusive,
+	 for allocating a scratch register for 32-bit shifts.  */
+    case 'U':
+      return (GET_CODE (x) == CONST_INT
+	      && (INTVAL (x) < 2 || INTVAL (x) > 15));
+
+    default:
+      return 0;
+    }
+}
+
+int
+short_memory_operand (x, mode)
+     rtx x;
+     enum machine_mode mode;
+{
+  if (! memory_operand (x, mode))
+    return 0;
+  return (GET_CODE (XEXP (x, 0)) != PLUS);
+}
+
+/* Splitter for the 'move' patterns, for modes not directly implemeted
+   by hardware.  Emit insns to copy a value of mode MODE from SRC to
+   DEST.
+
+   This function is only called when reload_completed.
+   */
+
+void 
+stormy16_split_move (mode, dest, src)
+     enum machine_mode mode;
+     rtx dest;
+     rtx src;
+{
+  int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD;
+  int direction, end, i;
+  int src_modifies = 0;
+  int dest_modifies = 0;
+  int src_volatile = 0;
+  int dest_volatile = 0;
+  rtx mem_operand;
+  
+  /* Check initial conditions.  */
+  if (! reload_completed
+      || mode == QImode || mode == HImode
+      || ! nonimmediate_operand (dest, mode)
+      || ! general_operand (src, mode))
+    abort ();
+
+  /* This case is not supported below, and shouldn't be generated.  */
+  if (GET_CODE (dest) == MEM
+      && GET_CODE (src) == MEM)
+    abort ();
+
+  /* This case is very very bad after reload, so trap it now.  */
+  if (GET_CODE (dest) == SUBREG
+      || GET_CODE (src) == SUBREG)
+    abort ();
+
+  /* The general idea is to copy by words, offsetting the source and
+     destination.  Normally the least-significant word will be copied
+     first, but for pre-dec operations it's better to copy the 
+     most-significant word first.  Only one operand can be a pre-dec
+     or post-inc operand.  
+
+     It's also possible that the copy overlaps so that the direction
+     must be reversed.  */
+  direction = 1;
+  
+  if (GET_CODE (dest) == MEM)
+    {
+      mem_operand = XEXP (dest, 0);
+      dest_modifies = side_effects_p (mem_operand);
+      dest_volatile = MEM_VOLATILE_P (dest);
+      if (dest_volatile)
+	{
+	  dest = copy_rtx (dest);
+	  MEM_VOLATILE_P (dest) = 0;
+	}
+    }
+  else if (GET_CODE (src) == MEM)
+    {
+      mem_operand = XEXP (src, 0);
+      src_modifies = side_effects_p (mem_operand);
+      src_volatile = MEM_VOLATILE_P (src);
+      if (src_volatile)
+	{
+	  src = copy_rtx (src);
+	  MEM_VOLATILE_P (src) = 0;
+	}
+    }
+  else
+    mem_operand = NULL_RTX;
+
+  if (mem_operand == NULL_RTX)
+    {
+      if (GET_CODE (src) == REG
+	  && GET_CODE (dest) == REG
+	  && reg_overlap_mentioned_p (dest, src)
+	  && REGNO (dest) > REGNO (src))
+	direction = -1;
+    }
+  else if (GET_CODE (mem_operand) == PRE_DEC
+      || (GET_CODE (mem_operand) == PLUS 
+	  && GET_CODE (XEXP (mem_operand, 0)) == PRE_DEC))
+    direction = -1;
+  else if (GET_CODE (src) == MEM
+	   && reg_overlap_mentioned_p (dest, src))
+    {
+      int regno;
+      if (GET_CODE (dest) != REG)
+	abort ();
+      regno = REGNO (dest);
+      
+      if (! refers_to_regno_p (regno, regno + num_words, mem_operand, 0))
+	abort ();
+      
+      if (refers_to_regno_p (regno, regno + 1, mem_operand, 0))
+	direction = -1;
+      else if (refers_to_regno_p (regno + num_words - 1, regno + num_words,
+				  mem_operand, 0))
+	direction = 1;
+      else
+	/* This means something like
+	   (set (reg:DI r0) (mem:DI (reg:HI r1)))
+	   which we'd need to support by doing the set of the second word
+	   last.  */
+	abort ();
+    }
+
+  end = direction < 0 ? -1 : num_words;
+  for (i = direction < 0 ? num_words - 1 : 0; i != end; i += direction)
+    {
+      rtx w_src, w_dest;
+      if (src_modifies)
+	w_src = gen_rtx_MEM (word_mode, mem_operand);
+      else
+	w_src = simplify_gen_subreg (word_mode, src, mode, i * UNITS_PER_WORD);
+      if (src_volatile)
+	MEM_VOLATILE_P (w_src) = 1;
+      if (dest_modifies)
+	w_dest = gen_rtx_MEM (word_mode, mem_operand);
+      else
+	w_dest = simplify_gen_subreg (word_mode, dest, mode, 
+				      i * UNITS_PER_WORD);
+      if (dest_volatile)
+	MEM_VOLATILE_P (w_dest) = 1;
+      
+      /* The simplify_subreg calls must always be able to simplify.  */
+      if (GET_CODE (w_src) == SUBREG
+	  || GET_CODE (w_dest) == SUBREG)
+	abort ();
+      
+      emit_insn (gen_rtx_SET (VOIDmode, w_dest, w_src));
+    }
+}
+
+/* Expander for the 'move' patterns.  Emit insns to copy a value of
+   mode MODE from SRC to DEST.  */
+
+void 
+stormy16_expand_move (mode, dest, src)
+     enum machine_mode mode;
+     rtx dest;
+     rtx src;
+{
+  /* There are only limited immediate-to-memory move instructions.  */
+  if (! reload_in_progress
+      && ! reload_completed
+      && GET_CODE (dest) == MEM
+      && (GET_CODE (XEXP (dest, 0)) != CONST_INT
+	  || ! stormy16_legitimate_address_p (mode, XEXP (dest, 0), 0))
+      && GET_CODE (src) != REG
+      && GET_CODE (src) != SUBREG)
+    src = copy_to_mode_reg (mode, src);
+
+  /* Don't emit something we would immediately split.  */
+  if (reload_completed
+      && mode != HImode && mode != QImode)
+    {
+      stormy16_split_move (mode, dest, src);
+      return;
+    }
+  
+  emit_insn (gen_rtx_SET (VOIDmode, dest, src));
+}
+
+
+/* Stack Layout:
+
+   The stack is laid out as follows:
+
+SP->
+FP->	Local variables
+	Register save area (up to 4 words)
+	Argument register save area for stdarg (NUM_ARGUMENT_REGISTERS words)
+
+AP->	Return address (two words)
+	9th procedure parameter word
+	10th procedure parameter word
+	...
+	last procedure parameter word
+
+  The frame pointer location is tuned to make it most likely that all
+  parameters and local variables can be accessed using a load-indexed
+  instruction.  */
+
+/* A structure to describe the layout.  */
+struct stormy16_stack_layout
+{
+  /* Size of the topmost three items on the stack.  */
+  int locals_size;
+  int register_save_size;
+  int stdarg_save_size;
+  /* Sum of the above items.  */
+  int frame_size;
+  /* Various offsets.  */
+  int first_local_minus_ap;
+  int sp_minus_fp;
+  int fp_minus_ap;
+};
+
+/* Does REGNO need to be saved?  */
+#define REG_NEEDS_SAVE(REGNUM, IFUN)					\
+  ((regs_ever_live[REGNUM] && ! call_used_regs[REGNUM])			\
+   || (IFUN && ! fixed_regs[REGNUM] && call_used_regs[REGNUM]		\
+       && (regs_ever_live[REGNUM] || ! current_function_is_leaf)))
+
+/* Compute the stack layout.  */
+struct stormy16_stack_layout 
+stormy16_compute_stack_layout ()
+{
+  struct stormy16_stack_layout layout;
+  int regno;
+  const int ifun = stormy16_interrupt_function_p ();
+
+  layout.locals_size = get_frame_size ();
+  
+  layout.register_save_size = 0;
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+    if (REG_NEEDS_SAVE (regno, ifun))
+      layout.register_save_size += UNITS_PER_WORD;
+  
+  if (current_function_varargs || current_function_stdarg)
+    layout.stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD;
+  else
+    layout.stdarg_save_size = 0;
+  
+  layout.frame_size = (layout.locals_size 
+		       + layout.register_save_size 
+		       + layout.stdarg_save_size);
+  
+  if (current_function_args_size <= 2048 && current_function_args_size != -1)
+    {
+      if (layout.frame_size + INCOMING_FRAME_SP_OFFSET 
+	  + current_function_args_size <= 2048)
+	layout.fp_minus_ap = layout.frame_size + INCOMING_FRAME_SP_OFFSET;
+      else
+	layout.fp_minus_ap = 2048 - current_function_args_size;
+    }
+  else
+    layout.fp_minus_ap = (layout.stdarg_save_size 
+			  + layout.register_save_size
+			  + INCOMING_FRAME_SP_OFFSET);
+  layout.sp_minus_fp = (layout.frame_size + INCOMING_FRAME_SP_OFFSET 
+			- layout.fp_minus_ap);
+  layout.first_local_minus_ap = layout.sp_minus_fp - layout.locals_size;
+  return layout;
+}
+
+/* Determine how all the special registers get eliminated.  */
+int
+stormy16_initial_elimination_offset (from, to)
+     int from, to;
+{
+  struct stormy16_stack_layout layout;
+  int result;
+  
+  layout = stormy16_compute_stack_layout ();
+
+  if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
+    result = layout.sp_minus_fp - layout.locals_size;
+  else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    result = -layout.locals_size;
+  else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
+    result = -layout.fp_minus_ap;
+  else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    result = -(layout.sp_minus_fp + layout.fp_minus_ap);
+  else
+    abort ();
+
+  return result;
+}
+
+static rtx
+emit_addhi3_postreload (dest, src0, src1)
+     rtx dest;
+     rtx src0;
+     rtx src1;
+{
+  rtx set, clobber, insn;
+  
+  set = gen_rtx_SET (VOIDmode, dest, gen_rtx_PLUS (HImode, src0, src1));
+  clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, 16));
+  insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
+  return insn;
+}
+
+/* Called after register allocation to add any instructions needed for the
+   prologue.  Using a prologue insn is favored compared to putting all of the
+   instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
+   to intermix instructions with the saves of the caller saved registers.  In
+   some cases, it might be necessary to emit a barrier instruction as the last
+   insn to prevent such scheduling.
+
+   Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
+   so that the debug info generation code can handle them properly.  */
+void
+stormy16_expand_prologue ()
+{
+  struct stormy16_stack_layout layout;
+  int regno;
+  rtx insn;
+  rtx mem_push_rtx;
+  rtx mem_fake_push_rtx;
+  const int ifun = stormy16_interrupt_function_p ();
+  
+  mem_push_rtx = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
+  mem_push_rtx = gen_rtx_MEM (HImode, mem_push_rtx);
+  mem_fake_push_rtx = gen_rtx_PRE_INC (Pmode, stack_pointer_rtx);
+  mem_fake_push_rtx = gen_rtx_MEM (HImode, mem_fake_push_rtx);
+    
+  layout = stormy16_compute_stack_layout ();
+
+  /* Save the argument registers if necessary.  */
+  if (layout.stdarg_save_size)
+    for (regno = FIRST_ARGUMENT_REGISTER; 
+	 regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS;
+	 regno++)
+      {
+	rtx reg = gen_rtx_REG (HImode, regno);
+	insn = emit_move_insn (mem_push_rtx, reg);
+	RTX_FRAME_RELATED_P (insn) = 1;
+	REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+					      gen_rtx_SET (VOIDmode,
+							   mem_fake_push_rtx,
+							   reg),
+					      REG_NOTES (insn));
+      }
+  
+  /* Push each of the registers to save.  */
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+    if (REG_NEEDS_SAVE (regno, ifun))
+      {
+	rtx reg = gen_rtx_REG (HImode, regno);
+	insn = emit_move_insn (mem_push_rtx, reg);
+	RTX_FRAME_RELATED_P (insn) = 1;
+	REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+					      gen_rtx_SET (VOIDmode,
+							   mem_fake_push_rtx,
+							   reg),
+					      REG_NOTES (insn));
+      }
+
+  /* It's just possible that the SP here might be what we need for
+     the new FP... */
+  if (frame_pointer_needed && layout.sp_minus_fp == layout.locals_size)
+    {
+      insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
+      RTX_FRAME_RELATED_P (insn) = 1;
+    }
+
+  /* Allocate space for local variables.  */
+  if (layout.locals_size)
+    {
+      insn = emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx,
+				     GEN_INT (layout.locals_size));
+      RTX_FRAME_RELATED_P (insn) = 1;
+    }
+
+  /* Set up the frame pointer, if required.  */
+  if (frame_pointer_needed && layout.sp_minus_fp != layout.locals_size)
+    {
+      insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
+      RTX_FRAME_RELATED_P (insn) = 1;
+      if (layout.sp_minus_fp)
+	{
+	  insn = emit_addhi3_postreload (hard_frame_pointer_rtx,
+					 hard_frame_pointer_rtx,
+					 GEN_INT (-layout.sp_minus_fp));
+	  RTX_FRAME_RELATED_P (insn) = 1;
+	}
+    }
+}
+
+/* Do we need an epilogue at all?  */
+int
+direct_return ()
+{
+  return (reload_completed 
+	  && stormy16_compute_stack_layout ().frame_size == 0);
+}
+
+/* Called after register allocation to add any instructions needed for the
+   epilogue.  Using a epilogue insn is favored compared to putting all of the
+   instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
+   to intermix instructions with the saves of the caller saved registers.  In
+   some cases, it might be necessary to emit a barrier instruction as the last
+   insn to prevent such scheduling.  */
+
+void
+stormy16_expand_epilogue ()
+{
+  struct stormy16_stack_layout layout;
+  rtx mem_pop_rtx;
+  int regno;
+  const int ifun = stormy16_interrupt_function_p ();
+  
+  mem_pop_rtx = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
+  mem_pop_rtx = gen_rtx_MEM (HImode, mem_pop_rtx);
+  
+  layout = stormy16_compute_stack_layout ();
+
+  /* Pop the stack for the locals.  */
+  if (layout.locals_size)
+    emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx,
+			    GEN_INT (- layout.locals_size));
+
+  /* Restore any call-saved registers.  */
+  for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
+    if (REG_NEEDS_SAVE (regno, ifun))
+      emit_move_insn (gen_rtx_REG (HImode, regno), mem_pop_rtx);
+  
+  /* Pop the stack for the stdarg save area.  */
+  if (layout.stdarg_save_size)
+    emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx,
+			    GEN_INT (- layout.stdarg_save_size));
+
+  /* Return.  */
+  if (ifun)
+    emit_jump_insn (gen_return_internal_interrupt ());
+  else
+    emit_jump_insn (gen_return_internal ());
+}
+
+int
+stormy16_epilogue_uses (regno)
+     int regno;
+{
+  if (reload_completed && call_used_regs[regno])
+    {
+      const int ifun = stormy16_interrupt_function_p ();
+      return REG_NEEDS_SAVE (regno, ifun);
+    }
+  return 0;
+}
+
+/* Return an updated summarizer variable CUM to advance past an
+   argument in the argument list.  The values MODE, TYPE and NAMED
+   describe that argument.  Once this is done, the variable CUM is
+   suitable for analyzing the *following* argument with
+   `FUNCTION_ARG', etc.
+
+   This function need not do anything if the argument in question was
+   passed on the stack.  The compiler knows how to track the amount of
+   stack space used for arguments without any special help.  However,
+   it makes life easier for stormy16_build_va_list if it does update
+   the word count.  */
+CUMULATIVE_ARGS
+stormy16_function_arg_advance (cum, mode, type, named)
+     CUMULATIVE_ARGS cum;
+     enum machine_mode mode;
+     tree type;
+     int named ATTRIBUTE_UNUSED;
+{
+  /* If an argument would otherwise be passed partially in registers,
+     and partially on the stack, the whole of it is passed on the
+     stack.  */
+  if (cum < NUM_ARGUMENT_REGISTERS
+      && cum + STORMY16_WORD_SIZE (type, mode) > NUM_ARGUMENT_REGISTERS)
+    cum = NUM_ARGUMENT_REGISTERS;
+  
+  cum += STORMY16_WORD_SIZE (type, mode);
+  
+  return cum;
+}
+
+/* Do any needed setup for a variadic function.  CUM has not been updated
+   for the last named argument which has type TYPE and mode MODE.  */
+void
+stormy16_setup_incoming_varargs (cum, int_mode, type, pretend_size)
+     CUMULATIVE_ARGS cum ATTRIBUTE_UNUSED;
+     int             int_mode ATTRIBUTE_UNUSED;
+     tree            type ATTRIBUTE_UNUSED;
+     int *           pretend_size ATTRIBUTE_UNUSED;
+{
+}
+
+/* Build the va_list type.
+
+   For this chip, va_list is a record containing a counter and a pointer.
+   The counter is of type 'int' and indicates how many bytes
+   have been used to date.  The pointer indicates the stack position
+   for arguments that have not been passed in registers.  
+   To keep the layout nice, the pointer is first in the structure.  */
+
+tree
+stormy16_build_va_list ()
+{
+  tree f_1, f_2, record, type_decl;
+
+  record = make_lang_type (RECORD_TYPE);
+  type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
+
+  f_2 = build_decl (FIELD_DECL, get_identifier ("base"),
+		      ptr_type_node);
+  f_1 = build_decl (FIELD_DECL, get_identifier ("count"), 
+		      unsigned_type_node);
+
+  DECL_FIELD_CONTEXT (f_1) = record;
+  DECL_FIELD_CONTEXT (f_2) = record;
+
+  TREE_CHAIN (record) = type_decl;
+  TYPE_NAME (record) = type_decl;
+  TYPE_FIELDS (record) = f_1;
+  TREE_CHAIN (f_1) = f_2;
+
+  layout_type (record);
+
+  return record;
+}
+
+/* Implement the stdarg/varargs va_start macro.  STDARG_P is non-zero if this
+   is stdarg.h instead of varargs.h.  VALIST is the tree of the va_list
+   variable to initialize.  NEXTARG is the machine independent notion of the
+   'next' argument after the variable arguments.  */
+void
+stormy16_expand_builtin_va_start (stdarg_p, valist, nextarg)
+     int stdarg_p ATTRIBUTE_UNUSED;
+     tree valist;
+     rtx nextarg ATTRIBUTE_UNUSED;
+{
+  tree f_base, f_count;
+  tree base, count;
+  tree t;
+
+  if (stormy16_interrupt_function_p ())
+    error ("cannot use va_start in interrupt function");
+  
+  f_base = TYPE_FIELDS (va_list_type_node);
+  f_count = TREE_CHAIN (f_base);
+  
+  base = build (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base);
+  count = build (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count);
+
+  t = make_tree (TREE_TYPE (base), virtual_incoming_args_rtx);
+  t = build (PLUS_EXPR, TREE_TYPE (base), t, 
+	     build_int_2 (INCOMING_FRAME_SP_OFFSET, 0));
+  t = build (MODIFY_EXPR, TREE_TYPE (base), base, t);
+  TREE_SIDE_EFFECTS (t) = 1;
+  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+
+  t = build (MODIFY_EXPR, TREE_TYPE (count), count, 
+	     build_int_2 (current_function_args_info * UNITS_PER_WORD, 0));
+  TREE_SIDE_EFFECTS (t) = 1;
+  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+}
+
+/* Implement the stdarg/varargs va_arg macro.  VALIST is the variable
+   of type va_list as a tree, TYPE is the type passed to va_arg.  */
+rtx
+stormy16_expand_builtin_va_arg (valist, type)
+     tree valist;
+     tree type;
+{
+  tree f_base, f_count;
+  tree base, count;
+  rtx count_rtx, addr_rtx, r;
+  rtx lab_gotaddr, lab_fromstack;
+  tree t;
+  int size, last_reg_count;
+  tree size_tree, count_plus_size;
+  
+  f_base = TYPE_FIELDS (va_list_type_node);
+  f_count = TREE_CHAIN (f_base);
+  
+  base = build (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base);
+  count = build (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count);
+
+  size = PUSH_ROUNDING (int_size_in_bytes (type));
+  size_tree = round_up (size_in_bytes (type), UNITS_PER_WORD);
+  
+  last_reg_count = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD - size;
+
+  count_rtx = expand_expr (count, NULL_RTX, HImode, EXPAND_NORMAL);
+  lab_gotaddr = gen_label_rtx ();
+  lab_fromstack = gen_label_rtx ();
+  addr_rtx = gen_reg_rtx (Pmode);
+  emit_cmp_and_jump_insns (count_rtx, GEN_INT (last_reg_count),
+			  GTU, const1_rtx, HImode, 1, 1, lab_fromstack);
+  
+  t = build (PLUS_EXPR, ptr_type_node, base, count);
+  r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
+  if (r != addr_rtx)
+    emit_move_insn (addr_rtx, r);
+
+  emit_jump_insn (gen_jump (lab_gotaddr));
+  emit_barrier ();
+  emit_label (lab_fromstack);
+  
+  /* Arguments larger than a word might need to skip over some
+     registers, since arguments are either passed entirely in
+     registers or entirely on the stack.  */
+  if (size > 2 || size < 0)
+    {
+      rtx lab_notransition = gen_label_rtx ();
+      emit_cmp_and_jump_insns (count_rtx, GEN_INT (NUM_ARGUMENT_REGISTERS 
+						   * UNITS_PER_WORD),
+			       GEU, const1_rtx, HImode, 1, 1, 
+			       lab_notransition);
+      
+      t = build (MODIFY_EXPR, TREE_TYPE (count), count, 
+		 build_int_2 (NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD, 0));
+      TREE_SIDE_EFFECTS (t) = 1;
+      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+      
+      emit_label (lab_notransition);
+    }
+
+  t = build (PLUS_EXPR, sizetype, size_tree,
+	     build_int_2 ((- NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD
+			   + INCOMING_FRAME_SP_OFFSET),
+			  -1));
+  t = build (PLUS_EXPR, TREE_TYPE (count), count, fold (t));
+  t = build (MINUS_EXPR, TREE_TYPE (base), base, t);
+  r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
+  if (r != addr_rtx)
+    emit_move_insn (addr_rtx, r);
+	     
+  emit_label (lab_gotaddr);
+
+  count_plus_size = build (PLUS_EXPR, TREE_TYPE (count), count, size_tree);
+  t = build (MODIFY_EXPR, TREE_TYPE (count), count, count_plus_size);
+  TREE_SIDE_EFFECTS (t) = 1;
+  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+
+  return addr_rtx;
+}
+
+/* Initialize the variable parts of a trampoline.  ADDR is an RTX for
+   the address of the trampoline; FNADDR is an RTX for the address of
+   the nested function; STATIC_CHAIN is an RTX for the static chain
+   value that should be passed to the function when it is called.  */
+void
+stormy16_initialize_trampoline (addr, fnaddr, static_chain)
+     rtx addr;
+     rtx fnaddr;
+     rtx static_chain;
+{
+  rtx reg_addr = gen_reg_rtx (Pmode);
+  rtx temp = gen_reg_rtx (HImode);
+  rtx reg_fnaddr = gen_reg_rtx (HImode);
+  rtx reg_addr_mem;
+
+  reg_addr_mem = gen_rtx_MEM (HImode, gen_rtx_POST_INC (Pmode, reg_addr));
+    
+  emit_move_insn (reg_addr, addr);
+  emit_move_insn (temp, GEN_INT (0x3130 | STATIC_CHAIN_REGNUM));
+  emit_move_insn (reg_addr_mem, temp);
+  emit_move_insn (temp, static_chain);
+  emit_move_insn (reg_addr_mem, temp);
+  emit_move_insn (reg_fnaddr, fnaddr);
+  emit_move_insn (temp, reg_fnaddr);
+  emit_insn (gen_andhi3 (temp, temp, GEN_INT (0xFF)));
+  emit_insn (gen_iorhi3 (temp, temp, GEN_INT (0x0200)));
+  emit_move_insn (reg_addr_mem, temp);
+  emit_insn (gen_lshrhi3 (reg_fnaddr, reg_fnaddr, GEN_INT (8)));
+  emit_move_insn (reg_addr_mem, reg_fnaddr);
+}
+
+/* Create an RTX representing the place where a function returns a
+   value of data type VALTYPE.  VALTYPE is a tree node representing a
+   data type.  Write `TYPE_MODE (VALTYPE)' to get the machine mode
+   used to represent that type.  On many machines, only the mode is
+   relevant.  (Actually, on most machines, scalar values are returned
+   in the same place regardless of mode).
+
+   If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion
+   rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type.
+
+   If the precise function being called is known, FUNC is a tree node
+   (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer.  This makes it
+   possible to use a different value-returning convention for specific
+   functions when all their calls are known.
+
+   `FUNCTION_VALUE' is not used for return vales with aggregate data types,
+   because these are returned in another way.  See `STRUCT_VALUE_REGNUM' and
+   related macros.  */
+rtx
+stormy16_function_value (valtype, func)
+     tree valtype;
+     tree func ATTRIBUTE_UNUSED;
+{
+  enum machine_mode mode;
+  mode = TYPE_MODE (valtype);
+  PROMOTE_MODE (mode, 0, valtype);
+  return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
+}
+
+/* Mark functions with SYMBOL_REF_FLAG.  */
+
+void
+stormy16_encode_section_info (decl)
+     tree decl;
+{
+  if (TREE_CODE (decl) == FUNCTION_DECL)
+    SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
+}
+
+/* Print a memory address as an operand to reference that memory location.  */
+void
+stormy16_print_operand_address (file, address)
+     FILE * file;
+     rtx    address;
+{
+  HOST_WIDE_INT offset;
+  int pre_dec, post_inc;
+
+  /* There are a few easy cases.  */
+  if (GET_CODE (address) == CONST_INT)
+    {
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (address) & 0xFFFF);
+      return;
+    }
+  
+  if (CONSTANT_P (address) || GET_CODE (address) == CODE_LABEL)
+    {
+      output_addr_const (file, address);
+      return;
+    }
+  
+  /* Otherwise, it's hopefully something of the form 
+     (plus:HI (pre_dec:HI (reg:HI ...)) (const_int ...))
+  */
+
+  if (GET_CODE (address) == PLUS)
+    {
+      if (GET_CODE (XEXP (address, 1)) != CONST_INT)
+	abort ();
+      offset = INTVAL (XEXP (address, 1));
+      address = XEXP (address, 0);
+    }
+  else
+    offset = 0;
+
+  pre_dec = (GET_CODE (address) == PRE_DEC);
+  post_inc = (GET_CODE (address) == POST_INC);
+  if (pre_dec || post_inc)
+    address = XEXP (address, 0);
+  
+  if (GET_CODE (address) != REG)
+    abort ();
+
+  fputc ('(', file);
+  if (pre_dec)
+    fputs ("--", file);
+  fputs (reg_names [REGNO (address)], file);
+  if (post_inc)
+    fputs ("++", file);
+  if (offset != 0)
+    {
+      fputc (',', file);
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
+    }
+  fputc (')', file);
+}
+
+/* Print an operand to a assembler instruction.  */
+void
+stormy16_print_operand (file, x, code)
+     FILE * file;
+     rtx    x;
+     int    code;
+{
+  switch (code)
+    {
+    case 'B':
+	/* There is either one bit set, or one bit clear, in X.
+	   Print it preceded by '#'.  */
+      {
+	HOST_WIDE_INT xx, l;
+
+	if (GET_CODE (x) == CONST_INT)
+	  xx = INTVAL (x);
+	else
+	  output_operand_lossage ("`B' operand is not constant");
+	
+	l = exact_log2 (xx);
+	if (l == -1)
+	  l = exact_log2 (~xx);
+	if (l == -1)
+	  output_operand_lossage ("`B' operand has multiple bits set");
+	
+	fputs (IMMEDIATE_PREFIX, file);
+	fprintf (file, HOST_WIDE_INT_PRINT_DEC, l);
+	return;
+      }
+
+    case 'C':
+      /* Print the symbol without a surrounding @fptr().  */
+      if (GET_CODE (x) == SYMBOL_REF)
+	assemble_name (file, XSTR (x, 0));
+      else
+	stormy16_print_operand_address (file, x);
+      return;
+
+    case 'o':
+    case 'O':
+      /* Print the immediate operand less one, preceded by '#'.  
+         For 'O', negate it first.  */
+      {
+	HOST_WIDE_INT xx;
+	
+	if (GET_CODE (x) == CONST_INT)
+	  xx = INTVAL (x);
+	else
+	  output_operand_lossage ("`o' operand is not constant");
+	
+	if (code == 'O')
+	  xx = -xx;
+	
+	fputs (IMMEDIATE_PREFIX, file);
+	fprintf (file, HOST_WIDE_INT_PRINT_DEC, xx - 1);
+	return;
+      }
+
+    case 0:
+      /* Handled below.  */
+      break;
+      
+    default:
+      output_operand_lossage ("stormy16_print_operand: unknown code");
+      return;
+    }
+
+  switch (GET_CODE (x))
+    {
+    case REG:
+      fputs (reg_names [REGNO (x)], file);
+      break;
+
+    case MEM:
+      stormy16_print_operand_address (file, XEXP (x, 0));
+      break;
+
+    default:
+      /* Some kind of constant or label; an immediate operand,
+         so prefix it with '#' for the assembler.  */
+      fputs (IMMEDIATE_PREFIX, file);
+      output_addr_const (file, x);
+      break;
+    }
+
+  return;
+}
+
+
+/* Expander for the `casesi' pattern.
+   INDEX is the index of the switch statement.
+   LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding
+     to the first table entry.
+   RANGE is the number of table entries.
+   TABLE is an ADDR_VEC that is the jump table.
+   DEFAULT_LABEL is the address to branch to if INDEX is outside the
+     range LOWER_BOUND to LOWER_BOUND+RANGE-1.
+*/
+
+void 
+stormy16_expand_casesi (index, lower_bound, range, table, default_label)
+     rtx index;
+     rtx lower_bound;
+     rtx range;
+     rtx table;
+     rtx default_label;
+{
+  HOST_WIDE_INT range_i = INTVAL (range);
+  rtx int_index;
+
+  /* This code uses 'br', so it can deal only with tables of size up to
+     8192 entries.  */
+  if (range_i >= 8192)
+    sorry ("switch statement of size %lu entries too large", 
+	   (unsigned long) range_i);
+
+  index = expand_binop (SImode, sub_optab, index, lower_bound, index, 0,
+			OPTAB_LIB_WIDEN);
+  emit_cmp_and_jump_insns (index, range, GTU, NULL_RTX, SImode, 1,
+			   0, default_label);
+  int_index = gen_lowpart_common (HImode, index);
+  emit_insn (gen_ashlhi3 (int_index, int_index, GEN_INT (2)));
+  emit_jump_insn (gen_tablejump_pcrel (int_index, table));
+}
+
+/* Output an ADDR_VEC.  It is output as a sequence of 'jmpf'
+   instructions, without label or alignment or any other special
+   constructs.  We know that the previous instruction will be the
+   `tablejump_pcrel' output above.
+
+   TODO: it might be nice to output 'br' instructions if they could
+   all reach.  */
+
+void
+stormy16_output_addr_vec (file, label, table)
+     FILE *file;
+     rtx label ATTRIBUTE_UNUSED;
+     rtx table;
+{ 
+  int vlen, idx;
+  
+  function_section (current_function_decl);
+
+  vlen = XVECLEN (table, 0);
+  for (idx = 0; idx < vlen; idx++)
+    {
+      fputs ("\tjmpf ", file);
+      stormy16_print_operand_address (file, 
+				      XEXP (XVECEXP (table, 0, idx), 0));
+      fputc ('\n', file);
+    }
+}
+
+
+/* Expander for the `call' patterns.
+   INDEX is the index of the switch statement.
+   LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding
+     to the first table entry.
+   RANGE is the number of table entries.
+   TABLE is an ADDR_VEC that is the jump table.
+   DEFAULT_LABEL is the address to branch to if INDEX is outside the
+     range LOWER_BOUND to LOWER_BOUND+RANGE-1.
+*/
+
+void 
+stormy16_expand_call (retval, dest, counter)
+     rtx retval;
+     rtx dest;
+     rtx counter;
+{
+  rtx call, temp;
+  enum machine_mode mode;
+
+  if (GET_CODE (dest) != MEM)
+    abort ();
+  dest = XEXP (dest, 0);
+
+  if (! CONSTANT_P (dest)
+      && GET_CODE (dest) != REG)
+    dest = force_reg (Pmode, dest);
+  
+  if (retval == NULL)
+    mode = VOIDmode;
+  else
+    mode = GET_MODE (retval);
+
+  call = gen_rtx_CALL (mode, gen_rtx_MEM (FUNCTION_MODE, dest),
+		       counter);
+  if (retval)
+    call = gen_rtx_SET (VOIDmode, retval, call);
+  
+  if (! CONSTANT_P (dest))
+    {
+      temp = gen_reg_rtx (HImode);
+      emit_move_insn (temp, const0_rtx);
+    }
+  else
+    temp = const0_rtx;
+  
+  call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, 
+						gen_rtx_USE (VOIDmode, temp)));
+  emit_call_insn (call);
+}
+
+/* Expanders for multiword computational operations.  */
+
+/* Expander for arithmetic operations; emit insns to compute
+
+   (set DEST (CODE:MODE SRC0 SRC1))
+   
+   using CARRY as a temporary.  When CODE is COMPARE, a branch
+   template is generated (this saves duplicating code in
+   stormy16_split_cbranch).  */
+
+void 
+stormy16_expand_arith (mode, code, dest, src0, src1, carry)
+     enum machine_mode mode;
+     enum rtx_code code;
+     rtx dest;
+     rtx src0;
+     rtx src1;
+     rtx carry;
+{
+  int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD;
+  int i;
+  int firstloop = 1;
+
+  if (code == NEG)
+    {
+      rtx zero_reg = gen_reg_rtx (word_mode);
+      emit_move_insn (zero_reg, src0);
+      src0 = zero_reg;
+    }
+  
+  for (i = 0; i < num_words; i++)
+    {
+      rtx w_src0, w_src1, w_dest;
+      rtx insn;
+      
+      if (code == NEG)
+	w_src0 = src0;
+      else
+	w_src0 = simplify_gen_subreg (word_mode, src0, mode, 
+				      i * UNITS_PER_WORD);
+      w_src1 = simplify_gen_subreg (word_mode, src1, mode, i * UNITS_PER_WORD);
+      w_dest = simplify_gen_subreg (word_mode, dest, mode, i * UNITS_PER_WORD);
+
+      switch (code)
+	{
+	case PLUS:
+	  if (firstloop
+	      && GET_CODE (w_src1) == CONST_INT && INTVAL (w_src1) == 0)
+	    continue;
+	  
+	  if (firstloop)
+	    insn = gen_addchi4 (w_dest, w_src0, w_src1, carry);
+	  else
+	    insn = gen_addchi5 (w_dest, w_src0, w_src1, carry, carry);
+	  break;
+
+	case NEG:
+	case MINUS:
+	case COMPARE:
+	  if (code == COMPARE && i == num_words - 1)
+	    {
+	      rtx branch, sub, clobber, sub_1;
+	      
+	      sub_1 = gen_rtx_MINUS (HImode, w_src0, 
+				     gen_rtx_ZERO_EXTEND (HImode, carry));
+	      sub = gen_rtx_SET (VOIDmode, w_dest,
+				 gen_rtx_MINUS (HImode, sub_1, w_src1));
+	      clobber = gen_rtx_CLOBBER (VOIDmode, carry);
+	      branch = gen_rtx_SET (VOIDmode, pc_rtx,
+				    gen_rtx_IF_THEN_ELSE (VOIDmode,
+							  gen_rtx_EQ (HImode,
+								      sub_1,
+								      w_src1),
+							  pc_rtx,
+							  pc_rtx));
+	      insn = gen_rtx_PARALLEL (VOIDmode,
+				       gen_rtvec (3, branch, sub, clobber));
+	    }
+	  else if (firstloop
+		   && code != COMPARE
+		   && GET_CODE (w_src1) == CONST_INT && INTVAL (w_src1) == 0)
+	    continue;
+	  else if (firstloop)
+	    insn = gen_subchi4 (w_dest, w_src0, w_src1, carry);
+	  else
+	    insn = gen_subchi5 (w_dest, w_src0, w_src1, carry, carry);
+	  break;
+
+	case IOR:
+	case XOR:
+	case AND:
+	  if (GET_CODE (w_src1) == CONST_INT 
+	      && INTVAL (w_src1) == -(code == AND))
+	    continue;
+	  
+	  insn = gen_rtx_SET (VOIDmode, w_dest, gen_rtx (code, mode,
+							 w_src0, w_src1));
+	  break;
+
+	case NOT:
+	  insn = gen_rtx_SET (VOIDmode, w_dest, gen_rtx_NOT (mode, w_src0));
+	  break;
+
+	default:
+	  abort ();
+	}
+      
+      firstloop = 0;
+      emit (insn);
+    }
+}
+
+/* Return 1 if OP is a shift operator.  */
+
+int
+shift_operator (op, mode)
+     register rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  enum rtx_code code = GET_CODE (op);
+
+  return (code == ASHIFT
+	  || code == ASHIFTRT
+	  || code == LSHIFTRT);
+}
+
+/* The shift operations are split at output time for constant values;
+   variable-width shifts get handed off to a library routine.  
+
+   Generate an output string to do (set X (CODE:MODE X SIZE_R))
+   SIZE_R will be a CONST_INT, X will be a hard register.  */
+
+const char * 
+stormy16_output_shift (mode, code, x, size_r, temp)
+     enum machine_mode mode;
+     enum rtx_code code;
+     rtx x;
+     rtx size_r;
+     rtx temp;
+{
+  HOST_WIDE_INT size;
+  const char *r0, *r1, *rt;
+  static char r[64];
+
+  if (GET_CODE (size_r) != CONST_INT
+      || GET_CODE (x) != REG
+      || mode != SImode)
+    abort ();
+  size = INTVAL (size_r) & (GET_MODE_BITSIZE (mode) - 1);
+
+  if (size == 0)
+    return "";
+
+  r0 = reg_names [REGNO (x)];
+  r1 = reg_names [REGNO (x) + 1];
+  rt = reg_names [REGNO (temp)];
+
+  /* For shifts of size 1, we can use the rotate instructions.  */
+  if (size == 1)
+    {
+      switch (code)
+	{
+	case ASHIFT:
+	  sprintf (r, "shl %s,#1 | rlc %s,#1", r0, r1);
+	  break;
+	case ASHIFTRT:
+	  sprintf (r, "asr %s,#1 | rrc %s,#1", r1, r0);
+	  break;
+	case LSHIFTRT:
+	  sprintf (r, "shr %s,#1 | rrc %s,#1", r1, r0);
+	  break;
+	default:
+	  abort ();
+	}
+      return r;
+    }
+  
+  /* For large shifts, there are easy special cases.  */
+  if (size == 16)
+    {
+      switch (code)
+	{
+	case ASHIFT:
+	  sprintf (r, "mov %s,%s | mov %s,#0", r1, r0, r0);
+	  break;
+	case ASHIFTRT:
+	  sprintf (r, "mov %s,%s | asr %s,#15", r0, r1, r1);
+	  break;
+	case LSHIFTRT:
+	  sprintf (r, "mov %s,%s | mov %s,#0", r0, r1, r1);
+	  break;
+	default:
+	  abort ();
+	}
+      return r;
+    }
+  if (size > 16)
+    {
+      switch (code)
+	{
+	case ASHIFT:
+	  sprintf (r, "mov %s,%s | mov %s,#0 | shl %s,#%d", 
+		   r1, r0, r0, r1, (int) size - 16);
+	  break;
+	case ASHIFTRT:
+	  sprintf (r, "mov %s,%s | asr %s,#15 | asr %s,#%d", 
+		   r0, r1, r1, r0, (int) size - 16);
+	  break;
+	case LSHIFTRT:
+	  sprintf (r, "mov %s,%s | mov %s,#0 | shr %s,#%d", 
+		   r0, r1, r1, r0, (int) size - 16);
+	  break;
+	default:
+	  abort ();
+	}
+      return r;
+    }
+
+  /* For the rest, we have to do more work.  In particular, we
+     need a temporary.  */
+  switch (code)
+    {
+    case ASHIFT:
+      sprintf (r, 
+	       "mov %s,%s | shl %s,#%d | shl %s,#%d | shr %s,#%d | or %s,%s", 
+	       rt, r0, r0, (int) size, r1, (int) size, rt, (int) 16-size,
+	       r1, rt);
+      break;
+    case ASHIFTRT:
+      sprintf (r, 
+	       "mov %s,%s | asr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s", 
+	       rt, r1, r1, (int) size, r0, (int) size, rt, (int) 16-size,
+	       r0, rt);
+      break;
+    case LSHIFTRT:
+      sprintf (r, 
+	       "mov %s,%s | shr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s", 
+	       rt, r1, r1, (int) size, r0, (int) size, rt, (int) 16-size,
+	       r0, rt);
+      break;
+    default:
+      abort ();
+    }
+  return r;
+}
+
+/* Attribute handling.  */
+
+/* Return nonzero if the function is an interrupt function.  */
+int
+stormy16_interrupt_function_p ()
+{
+  tree attributes;
+  
+  /* The dwarf2 mechanism asks for INCOMING_FRAME_SP_OFFSET before
+     any functions are declared, which is demonstrably wrong, but
+     it is worked around here.  FIXME.  */
+  if (!cfun)
+    return 0;
+
+  attributes = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
+  return lookup_attribute ("interrupt", attributes) != NULL_TREE;
+}
+
+/* If defined, a C function which returns nonzero if IDENTIFIER
+   with arguments ARGS is a valid machine specific attribute for TYPE.
+   The attributes in ATTRIBUTES have previously been assigned to TYPE.  */
+#undef TARGET_VALID_TYPE_ATTRIBUTE
+#define TARGET_VALID_TYPE_ATTRIBUTE stormy16_valid_type_attribute
+static int stormy16_valid_type_attribute PARAMS ((tree TYPE,
+						  tree ATTRIBUTES,
+						  tree IDENTIFIER,
+						  tree ARGS));
+
+static int
+stormy16_valid_type_attribute (type, attributes, identifier, args)
+     tree type;
+     tree attributes ATTRIBUTE_UNUSED;
+     tree identifier;
+     tree args ATTRIBUTE_UNUSED;
+{
+  if (TREE_CODE (type) != FUNCTION_TYPE)
+    return 0;
+  
+  if (is_attribute_p ("interrupt", identifier))
+    return 1;
+
+  return 0;
+}
+
+struct gcc_target targetm = TARGET_INITIALIZER;

gcc/config/stormy16/stormy16.md

+;; STORMY16 Machine description template
+;; Copyright (C) 1997, 1998, 1999, 2001 Free Software Foundation, Inc.
+;; Contributed by Red Hat, Inc.
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: Attributes
+;; ::
+;; ::::::::::::::::::::
+
+; Categorize branches for the conditional in the length attribute.
+(define_attr "branch_class" "notdirectbranch,br12,bcc12,bcc8p2,bcc8p4" 
+    (const_string "notdirectbranch"))
+
+; The length of an instruction, used for branch shortening.
+(define_attr "length" "" 
+  (cond
+   [(eq_attr "branch_class" "br12")
+     (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -2046))
+			(lt (minus (match_dup 0) (pc)) (const_int 2048)))
+		   (const_int 2)
+		   (const_int 4))
+    (eq_attr "branch_class" "bcc12")
+     (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -2044))
+			(lt (minus (match_dup 0) (pc)) (const_int 2048)))
+		   (const_int 4)
+		   (const_int 8))
+    (eq_attr "branch_class" "bcc8p2")
+     (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -124))
+			(lt (minus (match_dup 0) (pc)) (const_int 128)))
+		   (const_int 4)
+		   (const_int 8))
+    (eq_attr "branch_class" "bcc8p4")
+     (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -122))
+			(lt (minus (match_dup 0) (pc)) (const_int 128)))
+		   (const_int 6)
+		   (const_int 10))]
+   (const_int 2)))
+
+; The operand which determines the setting of Rpsw.
+; The numbers indicate the operand number,
+; 'clobber' indicates it is changed in some unspecified way
+; 'nop' means it is not changed.
+(define_attr "psw_operand" "clobber,nop,0,1,2,3,4" (const_string "0"))
+
+(define_asm_attributes [(set_attr "length" "4")
+			(set_attr "psw_operand" "clobber")])
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: Moves
+;; ::
+;; ::::::::::::::::::::
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "")
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  "{ stormy16_expand_move (QImode, operands[0], operands[1]); DONE; }")
+
+(define_insn "*movqi_internal"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q,r,m,e,e,T,r,S")
+	(match_operand:QI 1 "general_operand"       "r,r,R,e,m,i,i,i,i"))]
+  ""
+  "@
+   mov %0,%1
+   push %1
+   pop %0
+   mov.b %0,%1
+   mov.b %0,%1
+   mov %0,%1
+   mov Rx,%1
+   mov %0,%1
+   mov.b %0,%1"
+  [(set_attr_alternative "length" 
+	     [(const_int 2)
+	      (const_int 2)
+	      (const_int 2)
+	      (if_then_else (match_operand:QI 0 "short_memory_operand" "")
+			    (const_int 2)
+			    (const_int 4))
+	      (if_then_else (match_operand:QI 1 "short_memory_operand" "")
+			    (const_int 2)
+			    (const_int 4))
+	      (const_int 2)
+	      (const_int 2)
+	      (const_int 4)
+	      (const_int 4)])
+   (set_attr "psw_operand" "0,nop,nop,0,0,0,nop,0,nop")])
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "")
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+  "{ stormy16_expand_move (HImode, operands[0], operands[1]); DONE; }")
+
+(define_insn "*movhi_internal"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,r,m,e,e,T,r,S")
+	(match_operand:HI 1 "general_operand"       "r,r,R,e,m,L,L,i,i"))]
+  ""
+  "@
+   mov %0,%1
+   push %1
+   pop %0
+   mov.w %0,%1
+   mov.w %0,%1
+   mov.w %0,%1
+   mov.w Rx,%1
+   mov.w %0,%1
+   mov.w %0,%1"
+  [(set_attr_alternative "length" 
+	     [(const_int 2)
+	      (const_int 2)
+	      (const_int 2)
+	      (if_then_else (match_operand:QI 0 "short_memory_operand" "")
+			    (const_int 2)
+			    (const_int 4))
+	      (if_then_else (match_operand:QI 1 "short_memory_operand" "")
+			    (const_int 2)
+			    (const_int 4))
+	      (const_int 2)
+	      (const_int 2)
+	      (const_int 4)
+	      (const_int 4)])
+   (set_attr "psw_operand" "0,nop,nop,0,0,0,nop,0,nop")])
+
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "")
+	(match_operand:SI 1 "general_operand" ""))]
+  ""
+  "{ stormy16_expand_move (SImode, operands[0], operands[1]); DONE; }")
+
+(define_insn_and_split "*movsi_internal"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,Q,r,m,e,&e,e,r,S")
+	(match_operand:SI 1 "general_operand"       "r,r,R,e,o, V,L,i,i"))]
+  ""
+  "#"
+  "reload_completed"
+  [(pc)]
+  "{ stormy16_split_move (SImode, operands[0], operands[1]); DONE; }"
+  [(set_attr_alternative "length" 
+	     [(const_int 4)
+	      (const_int 4)
+	      (const_int 4)
+	      (if_then_else (match_operand:QI 0 "short_memory_operand" "")
+			    (const_int 6)
+			    (const_int 8))
+	      (if_then_else (match_operand:QI 1 "short_memory_operand" "")
+			    (const_int 6)
+			    (const_int 8))
+	      (if_then_else (match_operand:QI 1 "short_memory_operand" "")
+			    (const_int 6)
+			    (const_int 8))
+	      (const_int 4)
+	      (const_int 8)
+	      (const_int 8)])])
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: Conversions
+;; ::
+;; ::::::::::::::::::::
+
+(define_insn "extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
+  ""
+  "cbw %0")
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: Bit field extraction
+;; ::
+;; ::::::::::::::::::::
+
+;; Extract an unsigned bit field
+;(define_insn "extzv"
+;  [(set (match_operand:SI 0 "register_operand" "=r")
+;	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+;			 (match_operand:SI 2 "const_int_operand" "n")
+;			 (match_operand:SI 3 "const_int_operand" "n")))]
+;  ""
+;  "extzv %0,%1,%2,%3"
+;  [(set_attr "length" "4")])
+
+;; Insert a bit field
+;(define_insn "insv"
+;  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+;			 (match_operand:SI 1 "const_int_operand" "n")
+;			 (match_operand:SI 2 "const_int_operand" "n"))
+;	(match_operand:SI 3 "nonmemory_operand" "ri"))]
+;  ""
+;  "insv %0,%1,%2,%3"
+;  [(set_attr "length" "4")])
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: 16 bit Integer arithmetic
+;; ::
+;; ::::::::::::::::::::
+
+;; Addition
+; Operand 3 is marked earlyclobber because that helps reload
+; to generate better code---this pattern will never need the
+; carry register as an input, and some output reloads or input
+; reloads might need to use it.  In fact, without the '&' reload
+; will fail in some cases.
+(define_insn "addhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r,r,T,T,r,r,r")
+	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,0")
+		 (match_operand:HI 2 "nonmemory_operand" "O,P,L,M,Ir,N,i")))
+   (clobber (match_scratch:BI 3 "=X,X,&y,&y,&y,&y,&y"))]
+  ""
+  "@
+   inc %0,%o2
+   dec %0,%O2
+   add Rx,%2
+   sub Rx,#%n2
+   add %0,%2
+   sub %0,#%n2
+   add %0,%2"
+  [(set_attr "length" "2,2,2,2,2,2,4")])
+
+; Reload can generate addition operations.  The SECONDARY_RELOAD_CLASS
+; macro causes it to allocate the carry register; this pattern
+; shows it how to place the register in RTL to make the addition work.
+(define_expand "reload_inhi"
+  [(parallel [(set (match_operand:HI 0 "register_operand" "=r")
+		   (match_operand:HI 1 "stormy16_carry_plus_operand" ""))
+	      (clobber (match_operand:BI 2 "" "=&y"))])]
+  ""
+  "if (! rtx_equal_p (operands[0], XEXP (operands[1], 0)))
+    {
+      emit_insn (gen_rtx_SET (VOIDmode, operands[0], XEXP (operands[1], 0)));
+      operands[1] = gen_rtx_PLUS (GET_MODE (operands[1]), operands[0],
+				  XEXP (operands[1], 1));
+    }
+ ")
+
+(define_insn "addchi4"
+  [(set (match_operand:HI 0 "register_operand" "=T,r,r")
+	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
+		 (match_operand:HI 2 "nonmemory_operand" "L,Ir,i")))
+   (set (match_operand:BI 3 "register_operand" "=y,y,y")
+        (truncate:BI (lshiftrt:SI (plus:SI (zero_extend:SI (match_dup 1))
+					   (zero_extend:SI (match_dup 2)))
+				  (const_int 16))))]
+  ""
+  "@
+   add Rx,%2
+   add %0,%2
+   add %0,%2"
+  [(set_attr "length" "2,2,4")])
+
+(define_insn "addchi5"
+  [(set (match_operand:HI 0 "register_operand" "=T,r,r")
+	(plus:HI (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
+			  (zero_extend:HI (match_operand:BI 3 
+							    "register_operand"
+							    "y,y,y")))
+		 (match_operand:HI 2 "nonmemory_operand" "L,Ir,i")))
+   (set (match_operand:BI 4 "register_operand" "=y,y,y") 
+        (truncate:BI (lshiftrt:SI (plus:SI (plus:SI 
+					    (zero_extend:SI (match_dup 1))
+					    (zero_extend:SI (match_dup 3)))
+					   (zero_extend:SI (match_dup 2)))
+				  (const_int 16))))]
+  ""
+  "@
+   adc Rx,%2
+   adc %0,%2
+   adc %0,%2"
+  [(set_attr "length" "2,2,4")])
+
+;; Subtraction
+; Operand 3 is marked earlyclobber because that helps reload
+; to generate better code---this pattern will never need the
+; carry register as an input, and some output reloads or input
+; reloads might need to use it.  In fact, without the '&' reload
+; will fail in some cases.
+(define_insn "subhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r,r,T,T,r,r,r")
+	(minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,0,0")
+		  (match_operand:HI 2 "nonmemory_operand" "O,P,L,M,rI,M,i")))
+   (clobber (match_scratch:BI 3 "=X,X,&y,&y,&y,&y,&y"))]
+  ""
+  "@
+   dec %0,%o2
+   inc %0,%O2
+   sub Rx,%2
+   add Rx,#%n2
+   sub %0,%2
+   add %0,#%n2
+   sub %0,%2"
+  [(set_attr "length" "2,2,2,2,2,2,4")])
+
+(define_insn "subchi4"
+  [(set (match_operand:HI 0 "register_operand" "=T,r,r")
+	(minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
+		  (match_operand:HI 2 "nonmemory_operand" "L,Ir,i")))
+   (set (match_operand:BI 3 "register_operand" "=y,y,y") 
+        (truncate:BI (lshiftrt:SI (minus:SI (zero_extend:SI (match_dup 1))
+					    (zero_extend:SI (match_dup 2)))
+				  (const_int 16))))]
+  ""
+  "@
+   sub Rx,%2
+   sub %0,%2
+   sub %0,%2"
+  [(set_attr "length" "2,2,4")])
+
+(define_insn "subchi5"
+  [(set (match_operand:HI 0 "register_operand" "=T,r,r")
+	(minus:HI (minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
+			  (zero_extend:HI (match_operand:BI 3 
+							    "register_operand"
+							    "y,y,y")))
+		 (match_operand:HI 2 "nonmemory_operand" "L,Ir,i")))
+   (set (match_operand:BI 4 "register_operand" "=y,y,y") 
+        (truncate:BI (lshiftrt:SI (minus:SI (minus:SI 
+					     (zero_extend:SI (match_dup 1))
+					     (zero_extend:SI (match_dup 3)))
+					    (zero_extend:SI (match_dup 2)))
+				  (const_int 16))))]
+  ""
+  "@
+   sbc Rx,%2
+   sbc %0,%2
+   sbc %0,%2"
+  [(set_attr "length" "2,2,4")])
+
+; Basic multiplication
+(define_insn "mulhi3"
+  [(set (match_operand:HI 0 "register_operand" "=a")
+	(mult:HI (match_operand:HI 1 "register_operand" "%a")
+		 (match_operand:HI 2 "register_operand" "c")))
+   (clobber (match_scratch:HI 3 "=b"))
+   ]
+  ""
+  "mul"
+  [(set_attr "psw_operand" "nop")])
+
+;; Unsigned multiplication producing 64 bit results from 32 bit inputs
+; The constraint on operand 0 is 't' because it is actually two regs
+; long, and both regs must match the constraint.
+(define_insn "umulhisi3"
+  [(set (match_operand:SI 0 "register_operand" "=t")
+	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%a"))
+		 (zero_extend:SI (match_operand:HI 2 "register_operand" "c"))))
+   ]
+  ""
+  "mul"
+  [(set_attr "psw_operand" "nop")])
+
+;; Unsigned division giving both quotient and remainder
+(define_insn "udivmodhi4"
+  [(set (match_operand:HI 0 "register_operand" "=a")
+	(div:HI (match_operand:HI 1 "register_operand" "a")
+		(match_operand:HI 2 "register_operand" "c")))
+   (set (match_operand:HI 3 "register_operand" "=b")
+	(mod:HI (match_dup 1)
+		(match_dup 2)))]
+  ""
+  "div"
+  [(set_attr "psw_operand" "nop")])
+
+;; Negation
+
+(define_expand "neghi2"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(not:HI (match_operand:HI 1 "register_operand" "")))
+   (parallel [(set (match_dup 0) (plus:HI (match_dup 0) (const_int 1)))
+	      (clobber (match_scratch:BI 3 ""))])]
+  ""
+  "")
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: 16 bit Integer Shifts and Rotates
+;; ::
+;; ::::::::::::::::::::
+
+;; Arithmetic Shift Left
+(define_insn "ashlhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(ashift:HI (match_operand:HI 1 "register_operand" "0")
+		   (match_operand:HI 2 "nonmemory_operand" "ri")))
+   (clobber (match_scratch:BI 3 "=y"))]
+  ""
+  "shl %0,%2")
+
+;; Arithmetic Shift Right
+(define_insn "ashrhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
+		     (match_operand:HI 2 "nonmemory_operand" "ri")))
+   (clobber (match_scratch:BI 3 "=y"))]
+  ""
+  "asr %0,%2")
+
+;; Logical Shift Right
+(define_insn "lshrhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
+		     (match_operand:HI 2 "nonmemory_operand" "ri")))
+   (clobber (match_scratch:BI 3 "=y"))]
+  ""
+  "shr %0,%2")
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: 16 Bit Integer Logical operations
+;; ::
+;; ::::::::::::::::::::
+
+;; Logical AND, 16 bit integers
+(define_insn "andhi3"
+  [(set (match_operand:HI 0 "register_operand" "=T,r,r,r")
+	(and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
+		(match_operand:HI 2 "nonmemory_operand" "L,r,K,i")))]
+  ""
+  "@
+   and Rx,%2
+   and %0,%2
+   clr1 %0,%B2
+   and %0,%2"
+  [(set_attr "length" "2,2,2,4")])
+
+;; Inclusive OR, 16 bit integers
+(define_insn "iorhi3"
+  [(set (match_operand:HI 0 "register_operand" "=T,r,r,r")
+	(ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
+		(match_operand:HI 2 "nonmemory_operand" "L,r,J,i")))]
+  ""
+  "@
+   or Rx,%2
+   or %0,%2
+   set1 %0,%B2
+   or %0,%2"
+  [(set_attr "length" "2,2,2,4")])
+
+;; Exclusive OR, 16 bit integers
+(define_insn "xorhi3"
+  [(set (match_operand:HI 0 "register_operand" "=T,r,r")
+	(xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
+		(match_operand:HI 2 "nonmemory_operand" "L,r,i")))]
+  ""
+  "@
+   xor Rx,%2
+   xor %0,%2
+   xor %0,%2"
+  [(set_attr "length" "2,2,4")])
+
+;; One's complement, 16 bit integers
+(define_insn "one_cmplhi2"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(not:HI (match_operand:HI 1 "register_operand" "0")))]
+  ""
+  "not %0")
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: 32 bit Integer arithmetic
+;; ::
+;; ::::::::::::::::::::
+
+;; Addition
+(define_insn_and_split "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_operand:SI 1 "register_operand" "%0")
+		 (match_operand:SI 2 "nonmemory_operand" "ri")))
+   (clobber (match_scratch:BI 3 "=y"))]
+  ""
+  "#"
+  "reload_completed"
+  [(pc)]
+  "{ stormy16_expand_arith (SImode, PLUS, operands[0], operands[1],
+			    operands[2], operands[3]); DONE; } "
+  [(set_attr "length" "4")])
+
+;; Subtraction
+(define_insn_and_split "subsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(minus:SI (match_operand:SI 1 "register_operand" "0")
+		 (match_operand:SI 2 "nonmemory_operand" "ri")))
+   (clobber (match_scratch:BI 3 "=y"))]
+  ""
+  "#"
+  "reload_completed"
+  [(pc)]
+  "{ stormy16_expand_arith (SImode, MINUS, operands[0], operands[1],
+			    operands[2], operands[3]); DONE; } "
+  [(set_attr "length" "4")])
+
+(define_expand "negsi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(neg:SI (match_operand:SI 1 "register_operand" "")))]
+  ""
+  "{ stormy16_expand_arith (SImode, NEG, operands[0], const0_rtx,
+			    operands[1], gen_reg_rtx (BImode)); DONE; }")
+
+;; ::::::::::::::::::::
+;; ::
+;; :: 32 bit Integer Shifts and Rotates
+;; ::
+;; ::::::::::::::::::::
+
+;; Arithmetic Shift Left
+(define_expand "ashlsi3"
+  [(parallel [(set (match_operand:SI 0 "register_operand" "")
+		   (ashift:SI (match_operand:SI 1 "register_operand" "")
+			      (match_operand:SI 2 "const_int_operand" "")))
+	      (clobber (match_dup 3))
+	      (clobber (match_dup 4))])]
+  ""
+  " if (! const_int_operand (operands[2], SImode)) FAIL;
+  operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
+
+;; Arithmetic Shift Right
+(define_expand "ashrsi3"
+  [(parallel [(set (match_operand:SI 0 "register_operand" "")
+		   (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
+			        (match_operand:SI 2 "const_int_operand" "")))
+	      (clobber (match_dup 3))
+	      (clobber (match_dup 4))])]
+  ""
+  " if (! const_int_operand (operands[2], SImode)) FAIL;
+  operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
+
+;; Logical Shift Right
+(define_expand "lshrsi3"
+  [(parallel [(set (match_operand:SI 0 "register_operand" "")
+		   (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
+			        (match_operand:SI 2 "const_int_operand" "")))
+	      (clobber (match_dup 3))
+	      (clobber (match_dup 4))])]
+  ""
+  " if (! const_int_operand (operands[2], SImode)) FAIL;
+  operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
+
+(define_insn "*shiftsi"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(match_operator:SI 5 "shift_operator"
+	 [(match_operand:SI 1 "register_operand" "0,0")
+	  (match_operand:SI 2 "const_int_operand" "U,n")]))
+   (clobber (match_operand:BI 3 "register_operand" "=y,y"))
+   (clobber (match_operand:HI 4 "" "=X,r"))]
+  ""
+  "* return stormy16_output_shift (SImode, GET_CODE (operands[5]), 
+				   operands[0], operands[2], operands[4]);"
+  [(set_attr "length" "6,10")
+   (set_attr "psw_operand" "clobber,clobber")])
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: Comparisons
+;; ::
+;; ::::::::::::::::::::
+
+;; Note, we store the operands in the comparison insns, and use them later
+;; when generating the branch or scc operation.
+
+;; First the routines called by the machine independent part of the compiler
+(define_expand "cmphi"
+  [(set (cc0)
+        (compare (match_operand:HI 0 "register_operand" "")
+  		 (match_operand:HI 1 "nonmemory_operand" "")))]
+  ""
+  "
+{
+  stormy16_compare_op0 = operands[0];
+  stormy16_compare_op1 = operands[1];
+  DONE;
+}")
+
+; There are no real SImode comparisons, but some can be emulated
+; by performing a SImode subtract and looking at the condition flags.
+(define_expand "cmpsi"
+  [(set (cc0)
+        (compare (match_operand:SI 0 "register_operand" "")
+  		 (match_operand:SI 1 "nonmemory_operand" "")))]
+  ""
+  "
+{
+  stormy16_compare_op0 = operands[0];
+  stormy16_compare_op1 = operands[1];
+  DONE;
+}")
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: Branches
+;; ::
+;; ::::::::::::::::::::
+
+(define_expand "beq"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (EQ, operands[0]); DONE; }")
+
+(define_expand "bne"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (NE, operands[0]); DONE; }")
+
+(define_expand "bge"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (GE, operands[0]); DONE; }")
+
+(define_expand "bgt"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (GT, operands[0]); DONE; }")
+
+(define_expand "ble"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (LE, operands[0]); DONE; }")
+
+(define_expand "blt"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (LT, operands[0]); DONE; }")
+
+(define_expand "bgeu"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (GEU, operands[0]); DONE; }")
+
+(define_expand "bgtu"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (GTU, operands[0]); DONE; }")
+
+(define_expand "bleu"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (LEU, operands[0]); DONE; }")
+
+(define_expand "bltu"
+  [(use (match_operand 0 "" ""))]
+  ""
+  "{ stormy16_emit_cbranch (LTU, operands[0]); DONE; }")
+
+
+(define_insn "*cbranchhi"
+  [(set (pc) 
+	(if_then_else (match_operator:HI 1 "comparison_operator"
+				      [(match_operand:HI 2 "nonmemory_operand" 
+					"r,e,L")
+				       (match_operand:HI 3 "nonmemory_operand"
+						      "r,L,e")])
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))
+   (clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
+  ""
+  "*
+{
+  return stormy16_output_cbranch_hi (operands[1], \"%l0\", 0, insn);
+}"
+  [(set_attr "branch_class" "bcc12")
+   (set_attr "psw_operand" "0,0,1")])
+
+(define_insn "*cbranchhi_neg"
+  [(set (pc) 
+	(if_then_else (match_operator:HI 1 "comparison_operator"
+				      [(match_operand:HI 2 "nonmemory_operand" 
+							 "r,e,L")
+				       (match_operand:HI 3 "nonmemory_operand"
+							 "r,L,e")])
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))
+   (clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
+  ""
+  "*
+{
+  return stormy16_output_cbranch_hi (operands[1], \"%l0\", 1, insn);
+}"
+  [(set_attr "branch_class" "bcc12")
+   (set_attr "psw_operand" "0,0,1")])
+
+(define_insn "*eqbranchsi"
+  [(set (pc)
+	(if_then_else (match_operator:SI 1 "equality_operator"
+				      [(match_operand:SI 2 "register_operand" 
+							 "+r")
+				       (const_int 0)])
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))
+;; Although I would greatly like the 'match_dup' in the following line
+;; to actually be a register constraint, there is (at the time of writing) no
+;; way for reload to insert an output reload on the edges out of a branch.
+;; If reload is fixed to use insert_insn_on_edge, this can be changed.
+   (clobber (match_dup 2))]
+  ""
+  "*
+{
+  return stormy16_output_cbranch_si (operands[1], \"%l0\", 0, insn);
+}"
+  [(set_attr "branch_class" "bcc8p2")
+   (set_attr "psw_operand" "clobber")])
+
+(define_insn_and_split "*ineqbranchsi"
+  [(set (pc)
+	(if_then_else (match_operator:SI 1 "stormy16_ineqsi_operator"
+				      [(match_operand:SI 2 "register_operand" 
+							 "+r")
+				       (match_operand:SI 3 "nonmemory_operand" 
+							 "ri")])
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))
+;; Although I would greatly like the 'match_dup' in the following line
+;; to actually be a register constraint, there is (at the time of writing) no
+;; way for reload to insert an output reload on the edges out of a branch.
+;; If reload is fixed to use insert_insn_on_edge, this can be changed,
+;; preferably to a 'minus' operand that explains the actual operation, like:
+; (set (match_operand 5 "register_operand" "=2")
+;      (minus:SI (match_operand 6 "register_operand" "2")
+;		 (match_operand 7 "register_operand" "3")))
+   (clobber (match_dup 2))
+   (clobber (match_operand:BI 4 "" "=&y"))]
+  ""
+  "#"
+  "reload_completed"
+  [(pc)]
+  "{ stormy16_split_cbranch (SImode, operands[0], operands[1], operands[2],
+			     operands[4]); DONE; }"
+  [(set_attr "length" "8")])
+
+(define_insn "*ineqbranch_1"
+  [(set (pc)
+	(if_then_else (match_operator:HI 5 "stormy16_ineqsi_operator"
+		       [(minus:HI (match_operand:HI 1 "register_operand" 
+						    "T,r,r")
+			   (zero_extend:HI (match_operand:BI 4
+							     "register_operand"
+							     "y,y,y")))
+			(match_operand:HI 3 "nonmemory_operand" "L,Ir,i")])
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))
+   (set (match_operand:HI 2 "register_operand" "=2,2,2")
+	(minus:HI (minus:HI (match_dup 1) (zero_extend:HI (match_dup 4)))
+		  (match_dup 3)))
+   (clobber (match_operand:BI 6 "" "=y,y,y"))]
+  ""
+  "*
+{
+  return stormy16_output_cbranch_si (operands[5], \"%l0\", 0, insn);
+}"
+  [(set_attr "branch_class" "bcc8p2,bcc8p2,bcc8p4")
+   (set_attr "psw_operand" "2,2,2")])
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: Call and branch instructions
+;; ::
+;; ::::::::::::::::::::
+
+;; Subroutine call instruction returning no value.  Operand 0 is the function
+;; to call; operand 1 is the number of bytes of arguments pushed (in mode
+;; `SImode', except it is normally a `const_int'); operand 2 is the number of
+;; registers used as operands.
+
+;; On most machines, operand 2 is not actually stored into the RTL pattern.  It
+;; is supplied for the sake of some RISC machines which need to put this
+;; information into the assembler code; they can put it in the RTL instead of
+;; operand 1.
+
+(define_expand "call"
+  [(call (match_operand:HI 0 "memory_operand" "m")
+	 (match_operand 1 "" ""))
+   (use (match_operand 2 "immediate_operand" ""))]
+  ""
+  "stormy16_expand_call (NULL_RTX, operands[0], operands[1]); DONE;")
+
+;; Subroutine call instruction returning a value.  Operand 0 is the hard
+;; register in which the value is returned.  There are three more operands, the
+;; same as the three operands of the `call' instruction (but with numbers
+;; increased by one).
+
+;; Subroutines that return `BLKmode' objects use the `call' insn.
+
+(define_expand "call_value"
+  [(set (match_operand 0 "register_operand" "=r")
+	(call (match_operand:HI 1 "memory_operand" "m")
+	      (match_operand:SI 2 "" "")))
+	(use (match_operand 3 "immediate_operand" ""))]
+  ""
+  "stormy16_expand_call (operands[0], operands[1], operands[2]); DONE;")
+
+(define_insn "*call_internal"
+  [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r"))
+	 (match_operand 1 "" ""))
+   (use (match_operand:HI 2 "nonmemory_operand" "X,t"))]
+  ""
+  "@
+   callf %C0
+   call %2,%0"
+  [(set_attr "length" "4,2")
+   (set_attr "psw_operand" "clobber")])
+
+(define_insn "*call_value_internal"
+  [(set (match_operand 3 "register_operand" "=r,r")
+        (call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r"))
+	      (match_operand 1 "" "")))
+   (use (match_operand:HI 2 "nonmemory_operand" "X,t"))]
+  ""
+  "@
+   callf %C0
+   call %2,%0"
+  [(set_attr "length" "4,2")
+   (set_attr "psw_operand" "clobber")])
+
+;; Subroutine return
+(define_expand "return"
+  [(return)]
+  "direct_return()"
+  "")
+
+(define_insn "return_internal"
+  [(return)]
+  ""
+  "ret"
+  [(set_attr "psw_operand" "nop")])
+
+(define_insn "return_internal_interrupt"
+  [(return)
+   (unspec_volatile [(const_int 0)] 1)]
+  ""
+  "iret"
+  [(set_attr "psw_operand" "clobber")])
+
+;; Normal unconditional jump
+(define_insn "jump"
+  [(set (pc) (label_ref (match_operand 0 "" "")))]
+  ""
+  "*
+{
+  return stormy16_output_cbranch_hi (NULL_RTX, \"%l0\", 0, insn);
+}"
+  [(set_attr "branch_class" "br12")
+   (set_attr "psw_operand" "nop")])
+
+;; Indirect jump through a register
+(define_expand "indirect_jump"
+  [(set (match_dup 1) (const_int 0))
+   (parallel [(set (pc) (match_operand:HI 0 "register_operand" "r"))
+	      (use (match_dup 1))])]
+  ""
+  "operands[1] = gen_reg_rtx (HImode);")
+
+(define_insn ""
+  [(set (pc) (match_operand:HI 0 "register_operand" "r"))
+   (use (match_operand:HI 1 "register_operand" "t"))]
+  ""
+  "jmp %1,%0"
+  [(set_attr "length" "4")
+   (set_attr "psw_operand" "nop")])
+
+;; Table-based switch statements.
+(define_expand "casesi"
+  [(use (match_operand:SI 0 "register_operand" ""))
+   (use (match_operand:SI 1 "immediate_operand" ""))
+   (use (match_operand:SI 2 "immediate_operand" ""))
+   (use (label_ref (match_operand 3 "" "")))
+   (use (label_ref (match_operand 4 "" "")))]
+  ""
+  "
+{
+  stormy16_expand_casesi (operands[0], operands[1], operands[2],
+			  operands[3], operands[4]);
+  DONE;
+}")
+
+(define_insn "tablejump_pcrel"
+  [(set (pc) (plus:HI (pc) (match_operand:HI 0 "register_operand" "r")))
+   (use (label_ref:SI (match_operand 1 "" "")))]
+  ""
+  "br %0"
+  [(set_attr "psw_operand" "nop")])
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: Prologue and Epilogue instructions
+;; ::
+;; ::::::::::::::::::::
+
+;; Called after register allocation to add any instructions needed for the
+;; prologue.  Using a prologue insn is favored compared to putting all of the
+;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
+;; to intermix instructions with the saves of the caller saved registers.  In
+;; some cases, it might be necessary to emit a barrier instruction as the last
+;; insn to prevent such scheduling.
+(define_expand "prologue"
+  [(const_int 1)]
+  ""
+  "
+{
+  stormy16_expand_prologue ();
+  DONE;
+}")
+
+;; Called after register allocation to add any instructions needed for the
+;; epilogue.  Using a epilogue insn is favored compared to putting all of the
+;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
+;; to intermix instructions with the restires of the caller saved registers.
+;; In some cases, it might be necessary to emit a barrier instruction as the
+;; first insn to prevent such scheduling.
+(define_expand "epilogue"
+  [(const_int 2)]
+  ""
+  "
+{
+  stormy16_expand_epilogue ();
+  DONE;
+}")
+
+
+;; ::::::::::::::::::::
+;; ::
+;; :: Miscellaneous instructions
+;; ::
+;; ::::::::::::::::::::
+
+;; No operation, needed in case the user uses -g but not -O.
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nop"
+  [(set_attr "psw_operand" "nop")])
+
+;; Pseudo instruction that prevents the scheduler from moving code above this
+;; point.
+(define_insn "blockage"
+  [(unspec_volatile [(const_int 0)] 0)]
+  ""
+  ""
+  [(set_attr "length" "0")
+   (set_attr "psw_operand" "nop")])

gcc/config/stormy16/t-stormy16

+# -*- makefile -*-
+
+# SImode routines
+
+LIB2FUNCS_EXTRA = \
+	$(srcdir)/config/stormy16/stormy16-lib2.c
+
+# floating point emulation libraries
+
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT'				> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c			>> fp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	cat $(srcdir)/config/fp-bit.c > dp-bit.c