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Commit 4816b8e4 by Nick Clifton Committed by Nick Clifton
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Fix comment formating, and adjust sequence of #include headers. 

From-SVN: r37407
parent ee7692d2
Showing with 137 additions and 86 deletions
gcc/ChangeLog
2000-11-12 Nick Clifton <nickc@redhat.com>
* config/mcore/mcore.c: Fix comment formating, and adjust sequence
of #include headers.
2000-11-12 Marc Espie <espie@openbsd.org> 2000-11-12 Marc Espie <espie@openbsd.org>
* configure.in: Fix filds test. * configure.in: Fix filds test.
* configure: Regen. * configure: Regen.
......
gcc/config/mcore/mcore.c
...@@ -19,19 +19,18 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ ...@@ -19,19 +19,18 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#include "config.h" #include "config.h"
#include "system.h" #include "system.h"
#include "rtl.h"
#include "tree.h"
#include "tm_p.h"
#include "assert.h" #include "assert.h"
#include "gansidecl.h" #include "gansidecl.h"
#include "rtl.h"
#include "mcore.h" #include "mcore.h"
#include "regs.h" #include "regs.h"
#include "hard-reg-set.h" #include "hard-reg-set.h"
#include "real.h" #include "real.h"
#include "insn-config.h" #include "insn-config.h"
#include "conditions.h" #include "conditions.h"
#include "insn-flags.h" #include "insn-flags.h"
#include "tree.h"
#include "output.h" #include "output.h"
#include "insn-attr.h" #include "insn-attr.h"
#include "flags.h" #include "flags.h"
...@@ -42,7 +41,6 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ ...@@ -42,7 +41,6 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#include "function.h" #include "function.h"
#include "ggc.h" #include "ggc.h"
#include "toplev.h" #include "toplev.h"
#include "mcore-protos.h"
/* Maximum size we are allowed to grow the stack in a single operation. /* Maximum size we are allowed to grow the stack in a single operation.
If we want more, we must do it in increments of at most this size. If we want more, we must do it in increments of at most this size.
...@@ -155,8 +153,8 @@ output_stack_adjust (direction, size) ...@@ -155,8 +153,8 @@ output_stack_adjust (direction, size)
} }
while (size > mcore_stack_increment); while (size > mcore_stack_increment);
/* 'size' is now the residual for the last adjustment, which doesn't /* SIZE is now the residual for the last adjustment,
* require a probe. */ which doesn't require a probe. */
} }
if (size) if (size)
...@@ -180,8 +178,9 @@ output_stack_adjust (direction, size) ...@@ -180,8 +178,9 @@ output_stack_adjust (direction, size)
} }
} }
/* Work out the registers which need to be saved, both as a mask and a /* Work out the registers which need to be saved,
count. */ both as a mask and a count. */
static int static int
calc_live_regs (count) calc_live_regs (count)
int * count; int * count;
...@@ -204,6 +203,7 @@ calc_live_regs (count) ...@@ -204,6 +203,7 @@ calc_live_regs (count)
} }
/* Print the operand address in x to the stream. */ /* Print the operand address in x to the stream. */
void void
mcore_print_operand_address (stream, x) mcore_print_operand_address (stream, x)
FILE * stream; FILE * stream;
...@@ -260,7 +260,8 @@ mcore_print_operand_address (stream, x) ...@@ -260,7 +260,8 @@ mcore_print_operand_address (stream, x)
'P' print log2 of a power of two 'P' print log2 of a power of two
'Q' print log2 of an inverse of a power of two 'Q' print log2 of an inverse of a power of two
'U' print register for ldm/stm instruction 'U' print register for ldm/stm instruction
'X' print byte number for xtrbN instruction */ 'X' print byte number for xtrbN instruction. */
void void
mcore_print_operand (stream, x, code) mcore_print_operand (stream, x, code)
FILE * stream; FILE * stream;
...@@ -331,6 +332,7 @@ mcore_print_operand (stream, x, code) ...@@ -331,6 +332,7 @@ mcore_print_operand (stream, x, code)
} }
/* What does a constant cost ? */ /* What does a constant cost ? */
int int
mcore_const_costs (exp, code) mcore_const_costs (exp, code)
rtx exp; rtx exp;
...@@ -360,7 +362,8 @@ mcore_const_costs (exp, code) ...@@ -360,7 +362,8 @@ mcore_const_costs (exp, code)
/* What does an and instruction cost - we do this b/c immediates may /* What does an and instruction cost - we do this b/c immediates may
have been relaxed. We want to ensure that cse will cse relaxed immeds have been relaxed. We want to ensure that cse will cse relaxed immeds
out. Otherwise we'll get bad code (multiple reloads of the same const) */ out. Otherwise we'll get bad code (multiple reloads of the same const). */
int int
mcore_and_cost (x) mcore_and_cost (x)
rtx x; rtx x;
...@@ -382,11 +385,12 @@ mcore_and_cost (x) ...@@ -382,11 +385,12 @@ mcore_and_cost (x)
else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val)) else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
return 4; return 4;
/* takes a lrw to load */ /* Takes a lrw to load. */
return 5; return 5;
} }
/* What does an or cost - see and_cost(). */ /* What does an or cost - see and_cost(). */
int int
mcore_ior_cost (x) mcore_ior_cost (x)
rtx x; rtx x;
...@@ -415,6 +419,7 @@ mcore_ior_cost (x) ...@@ -415,6 +419,7 @@ mcore_ior_cost (x)
/* Check to see if a comparison against a constant can be made more efficient /* Check to see if a comparison against a constant can be made more efficient
by incrementing/decrementing the constant to get one that is more efficient by incrementing/decrementing the constant to get one that is more efficient
to load. */ to load. */
int int
mcore_modify_comparison (code) mcore_modify_comparison (code)
enum rtx_code code; enum rtx_code code;
...@@ -444,6 +449,7 @@ mcore_modify_comparison (code) ...@@ -444,6 +449,7 @@ mcore_modify_comparison (code)
} }
/* Prepare the operands for a comparison. */ /* Prepare the operands for a comparison. */
rtx rtx
mcore_gen_compare_reg (code) mcore_gen_compare_reg (code)
enum rtx_code code; enum rtx_code code;
...@@ -456,29 +462,32 @@ mcore_gen_compare_reg (code) ...@@ -456,29 +462,32 @@ mcore_gen_compare_reg (code)
op1 = force_reg (SImode, op1); op1 = force_reg (SImode, op1);
/* cmpnei: 0-31 (K immediate) /* cmpnei: 0-31 (K immediate)
cmplti: 1-32 (J immediate, 0 using btsti x,31) */ cmplti: 1-32 (J immediate, 0 using btsti x,31). */
switch (code) switch (code)
{ {
case EQ: /* use inverted condition, cmpne */ case EQ: /* Use inverted condition, cmpne. */
code = NE; code = NE;
/* drop through */ /* drop through */
case NE: /* use normal condition, cmpne */
case NE: /* Use normal condition, cmpne. */
if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1))) if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
op1 = force_reg (SImode, op1); op1 = force_reg (SImode, op1);
break; break;
case LE: /* use inverted condition, reversed cmplt */ case LE: /* Use inverted condition, reversed cmplt. */
code = GT; code = GT;
/* drop through */ /* drop through */
case GT: /* use normal condition, reversed cmplt */
case GT: /* Use normal condition, reversed cmplt. */
if (GET_CODE (op1) == CONST_INT) if (GET_CODE (op1) == CONST_INT)
op1 = force_reg (SImode, op1); op1 = force_reg (SImode, op1);
break; break;
case GE: /* use inverted condition, cmplt */ case GE: /* Use inverted condition, cmplt. */
code = LT; code = LT;
/* drop through */ /* drop through */
case LT: /* use normal condition, cmplt */
case LT: /* Use normal condition, cmplt. */
if (GET_CODE (op1) == CONST_INT && if (GET_CODE (op1) == CONST_INT &&
/* covered by btsti x,31 */ /* covered by btsti x,31 */
INTVAL (op1) != 0 && INTVAL (op1) != 0 &&
...@@ -486,7 +495,7 @@ mcore_gen_compare_reg (code) ...@@ -486,7 +495,7 @@ mcore_gen_compare_reg (code)
op1 = force_reg (SImode, op1); op1 = force_reg (SImode, op1);
break; break;
case GTU: /* use inverted condition, cmple */ case GTU: /* Use inverted condition, cmple. */
if (GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0) if (GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0)
{ {
/* Unsigned > 0 is the same as != 0, but we need /* Unsigned > 0 is the same as != 0, but we need
...@@ -501,15 +510,17 @@ mcore_gen_compare_reg (code) ...@@ -501,15 +510,17 @@ mcore_gen_compare_reg (code)
} }
code = LEU; code = LEU;
/* drop through */ /* drop through */
case LEU: /* use normal condition, reversed cmphs */
case LEU: /* Use normal condition, reversed cmphs. */
if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0) if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
op1 = force_reg (SImode, op1); op1 = force_reg (SImode, op1);
break; break;
case LTU: /* use inverted condition, cmphs */ case LTU: /* Use inverted condition, cmphs. */
code = GEU; code = GEU;
/* drop through */ /* drop through */
case GEU: /* use normal condition, cmphs */
case GEU: /* Use normal condition, cmphs. */
if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0) if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
op1 = force_reg (SImode, op1); op1 = force_reg (SImode, op1);
break; break;
...@@ -594,6 +605,7 @@ mcore_output_call (operands, index) ...@@ -594,6 +605,7 @@ mcore_output_call (operands, index)
} }
/* Can we load a constant with a single instruction ? */ /* Can we load a constant with a single instruction ? */
static int static int
const_ok_for_mcore (value) const_ok_for_mcore (value)
int value; int value;
...@@ -613,6 +625,7 @@ const_ok_for_mcore (value) ...@@ -613,6 +625,7 @@ const_ok_for_mcore (value)
} }
/* Can we load a constant inline with up to 2 instructions ? */ /* Can we load a constant inline with up to 2 instructions ? */
int int
mcore_const_ok_for_inline (value) mcore_const_ok_for_inline (value)
long value; long value;
...@@ -623,6 +636,7 @@ mcore_const_ok_for_inline (value) ...@@ -623,6 +636,7 @@ mcore_const_ok_for_inline (value)
} }
/* Are we loading the constant using a not ? */ /* Are we loading the constant using a not ? */
int int
mcore_const_trick_uses_not (value) mcore_const_trick_uses_not (value)
long value; long value;
...@@ -634,20 +648,19 @@ mcore_const_trick_uses_not (value) ...@@ -634,20 +648,19 @@ mcore_const_trick_uses_not (value)
/* Try tricks to load a constant inline and return the trick number if /* Try tricks to load a constant inline and return the trick number if
success (0 is non-inlinable). success (0 is non-inlinable).
*
* 0: not inlinable 0: not inlinable
* 1: single instruction (do the usual thing) 1: single instruction (do the usual thing)
* 2: single insn followed by a 'not' 2: single insn followed by a 'not'
* 3: single insn followed by a subi 3: single insn followed by a subi
* 4: single insn followed by an addi 4: single insn followed by an addi
* 5: single insn followed by rsubi 5: single insn followed by rsubi
* 6: single insn followed by bseti 6: single insn followed by bseti
* 7: single insn followed by bclri 7: single insn followed by bclri
* 8: single insn followed by rotli 8: single insn followed by rotli
* 9: single insn followed by lsli 9: single insn followed by lsli
* 10: single insn followed by ixh 10: single insn followed by ixh
* 11: single insn followed by ixw 11: single insn followed by ixw. */
*/
static int static int
try_constant_tricks (value, x, y) try_constant_tricks (value, x, y)
...@@ -659,7 +672,7 @@ try_constant_tricks (value, x, y) ...@@ -659,7 +672,7 @@ try_constant_tricks (value, x, y)
unsigned bit, shf, rot; unsigned bit, shf, rot;
if (const_ok_for_mcore (value)) if (const_ok_for_mcore (value))
return 1; /* do the usual thing */ return 1; /* Do the usual thing. */
if (TARGET_HARDLIT) if (TARGET_HARDLIT)
{ {
...@@ -778,6 +791,7 @@ try_constant_tricks (value, x, y) ...@@ -778,6 +791,7 @@ try_constant_tricks (value, x, y)
reg. Don't just use dead_or_set_p() since reload does not always mark reg. Don't just use dead_or_set_p() since reload does not always mark
deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
can ignore subregs by extracting the actual register. BRC */ can ignore subregs by extracting the actual register. BRC */
int int
mcore_is_dead (first, reg) mcore_is_dead (first, reg)
rtx first; rtx first;
...@@ -825,11 +839,12 @@ mcore_is_dead (first, reg) ...@@ -825,11 +839,12 @@ mcore_is_dead (first, reg)
/* Count the number of ones in mask. */ /* Count the number of ones in mask. */
int int
mcore_num_ones (mask) mcore_num_ones (mask)
int mask; int mask;
{ {
/* A trick to count set bits recently posted on comp.compilers */ /* A trick to count set bits recently posted on comp.compilers. */
mask = (mask >> 1 & 0x55555555) + (mask & 0x55555555); mask = (mask >> 1 & 0x55555555) + (mask & 0x55555555);
mask = ((mask >> 2) & 0x33333333) + (mask & 0x33333333); mask = ((mask >> 2) & 0x33333333) + (mask & 0x33333333);
mask = ((mask >> 4) + mask) & 0x0f0f0f0f; mask = ((mask >> 4) + mask) & 0x0f0f0f0f;
...@@ -839,6 +854,7 @@ mcore_num_ones (mask) ...@@ -839,6 +854,7 @@ mcore_num_ones (mask)
} }
/* Count the number of zeros in mask. */ /* Count the number of zeros in mask. */
int int
mcore_num_zeros (mask) mcore_num_zeros (mask)
int mask; int mask;
...@@ -847,6 +863,7 @@ mcore_num_zeros (mask) ...@@ -847,6 +863,7 @@ mcore_num_zeros (mask)
} }
/* Determine byte being masked. */ /* Determine byte being masked. */
int int
mcore_byte_offset (mask) mcore_byte_offset (mask)
unsigned int mask; unsigned int mask;
...@@ -864,6 +881,7 @@ mcore_byte_offset (mask) ...@@ -864,6 +881,7 @@ mcore_byte_offset (mask)
} }
/* Determine halfword being masked. */ /* Determine halfword being masked. */
int int
mcore_halfword_offset (mask) mcore_halfword_offset (mask)
unsigned int mask; unsigned int mask;
...@@ -877,6 +895,7 @@ mcore_halfword_offset (mask) ...@@ -877,6 +895,7 @@ mcore_halfword_offset (mask)
} }
/* Output a series of bseti's corresponding to mask. */ /* Output a series of bseti's corresponding to mask. */
const char * const char *
mcore_output_bseti (dst, mask) mcore_output_bseti (dst, mask)
rtx dst; rtx dst;
...@@ -902,6 +921,7 @@ mcore_output_bseti (dst, mask) ...@@ -902,6 +921,7 @@ mcore_output_bseti (dst, mask)
} }
/* Output a series of bclri's corresponding to mask. */ /* Output a series of bclri's corresponding to mask. */
const char * const char *
mcore_output_bclri (dst, mask) mcore_output_bclri (dst, mask)
rtx dst; rtx dst;
...@@ -930,6 +950,7 @@ mcore_output_bclri (dst, mask) ...@@ -930,6 +950,7 @@ mcore_output_bclri (dst, mask)
/* Output a conditional move of two constants that are +/- 1 within each /* Output a conditional move of two constants that are +/- 1 within each
other. See the "movtK" patterns in mcore.md. I'm not sure this is other. See the "movtK" patterns in mcore.md. I'm not sure this is
really worth the effort. */ really worth the effort. */
const char * const char *
mcore_output_cmov (operands, cmp_t, test) mcore_output_cmov (operands, cmp_t, test)
rtx operands[]; rtx operands[];
...@@ -942,8 +963,7 @@ mcore_output_cmov (operands, cmp_t, test) ...@@ -942,8 +963,7 @@ mcore_output_cmov (operands, cmp_t, test)
out_operands[0] = operands[0]; out_operands[0] = operands[0];
/* check to see which constant is loadable */ /* Check to see which constant is loadable. */
if (const_ok_for_mcore (INTVAL (operands[1]))) if (const_ok_for_mcore (INTVAL (operands[1])))
{ {
out_operands[1] = operands[1]; out_operands[1] = operands[1];
...@@ -954,22 +974,21 @@ mcore_output_cmov (operands, cmp_t, test) ...@@ -954,22 +974,21 @@ mcore_output_cmov (operands, cmp_t, test)
out_operands[1] = operands[2]; out_operands[1] = operands[2];
out_operands[2] = operands[1]; out_operands[2] = operands[1];
/* complement test since constants are swapped */ /* Complement test since constants are swapped. */
cmp_t = (cmp_t == 0); cmp_t = (cmp_t == 0);
} }
load_value = INTVAL (out_operands[1]); load_value = INTVAL (out_operands[1]);
adjust_value = INTVAL (out_operands[2]); adjust_value = INTVAL (out_operands[2]);
/* first output the test if folded into the pattern */ /* First output the test if folded into the pattern. */
if (test) if (test)
output_asm_insn (test, operands); output_asm_insn (test, operands);
/* load the constant - for now, only support constants that can be /* Load the constant - for now, only support constants that can be
generated with a single instruction. maybe add general inlinable generated with a single instruction. maybe add general inlinable
constants later (this will increase the # of patterns since the constants later (this will increase the # of patterns since the
instruction sequence has a different length attribute). */ instruction sequence has a different length attribute). */
if (load_value >= 0 && load_value <= 127) if (load_value >= 0 && load_value <= 127)
output_asm_insn ("movi\t%0,%1", out_operands); output_asm_insn ("movi\t%0,%1", out_operands);
else if ((load_value & (load_value - 1)) == 0) else if ((load_value & (load_value - 1)) == 0)
...@@ -977,8 +996,7 @@ mcore_output_cmov (operands, cmp_t, test) ...@@ -977,8 +996,7 @@ mcore_output_cmov (operands, cmp_t, test)
else if ((load_value & (load_value + 1)) == 0) else if ((load_value & (load_value + 1)) == 0)
output_asm_insn ("bmaski\t%0,%N1", out_operands); output_asm_insn ("bmaski\t%0,%N1", out_operands);
/* output the constant adjustment */ /* Output the constant adjustment. */
if (load_value > adjust_value) if (load_value > adjust_value)
{ {
if (cmp_t) if (cmp_t)
...@@ -998,7 +1016,8 @@ mcore_output_cmov (operands, cmp_t, test) ...@@ -998,7 +1016,8 @@ mcore_output_cmov (operands, cmp_t, test)
} }
/* Outputs the peephole for moving a constant that gets not'ed followed /* Outputs the peephole for moving a constant that gets not'ed followed
by an and (i.e. combine the not and the and into andn) BRC */ by an and (i.e. combine the not and the and into andn). BRC */
const char * const char *
mcore_output_andn (insn, operands) mcore_output_andn (insn, operands)
rtx insn ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED;
...@@ -1018,12 +1037,15 @@ mcore_output_andn (insn, operands) ...@@ -1018,12 +1037,15 @@ mcore_output_andn (insn, operands)
if (x >= 0 && x <= 127) if (x >= 0 && x <= 127)
load_op = "movi\t%0,%1"; load_op = "movi\t%0,%1";
/* try exact power of two */
/* Try exact power of two. */
else if ((x & (x - 1)) == 0) else if ((x & (x - 1)) == 0)
load_op = "bgeni\t%0,%P1"; load_op = "bgeni\t%0,%P1";
/* try exact power of two - 1 */
/* Try exact power of two - 1. */
else if ((x & (x + 1)) == 0) else if ((x & (x + 1)) == 0)
load_op = "bmaski\t%0,%N1"; load_op = "bmaski\t%0,%N1";
else else
load_op = "BADMOVI\t%0,%1"; load_op = "BADMOVI\t%0,%1";
...@@ -1034,6 +1056,7 @@ mcore_output_andn (insn, operands) ...@@ -1034,6 +1056,7 @@ mcore_output_andn (insn, operands)
} }
/* Output an inline constant. */ /* Output an inline constant. */
static const char * static const char *
output_inline_const (mode, operands) output_inline_const (mode, operands)
enum machine_mode mode; enum machine_mode mode;
...@@ -1060,16 +1083,14 @@ output_inline_const (mode, operands) ...@@ -1060,16 +1083,14 @@ output_inline_const (mode, operands)
if (trick_no == 1) if (trick_no == 1)
x = value; x = value;
/* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment */ /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
out_operands[0] = operands[0]; out_operands[0] = operands[0];
out_operands[1] = GEN_INT (x); out_operands[1] = GEN_INT (x);
if (trick_no > 2) if (trick_no > 2)
out_operands[2] = GEN_INT (y); out_operands[2] = GEN_INT (y);
/* Select dst format based on mode */ /* Select dst format based on mode. */
if (mode == DImode && (! TARGET_LITTLE_END)) if (mode == DImode && (! TARGET_LITTLE_END))
dst_fmt = "%R0"; dst_fmt = "%R0";
else else
...@@ -1077,12 +1098,15 @@ output_inline_const (mode, operands) ...@@ -1077,12 +1098,15 @@ output_inline_const (mode, operands)
if (x >= 0 && x <= 127) if (x >= 0 && x <= 127)
sprintf (load_op, "movi\t%s,%%1", dst_fmt); sprintf (load_op, "movi\t%s,%%1", dst_fmt);
/* Try exact power of two. */ /* Try exact power of two. */
else if ((x & (x - 1)) == 0) else if ((x & (x - 1)) == 0)
sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt); sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt);
/* try exact power of two - 1. */
/* Try exact power of two - 1. */
else if ((x & (x + 1)) == 0) else if ((x & (x + 1)) == 0)
sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt); sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt);
else else
sprintf (load_op, "BADMOVI\t%s,%%1", dst_fmt); sprintf (load_op, "BADMOVI\t%s,%%1", dst_fmt);
...@@ -1101,7 +1125,7 @@ output_inline_const (mode, operands) ...@@ -1101,7 +1125,7 @@ output_inline_const (mode, operands)
sprintf (buf, "%s\n\tsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value); sprintf (buf, "%s\n\tsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
break; break;
case 5: /* rsub */ case 5: /* rsub */
/* never happens unless -mrsubi, see try_constant_tricks() */ /* Never happens unless -mrsubi, see try_constant_tricks(). */
sprintf (buf, "%s\n\trsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value); sprintf (buf, "%s\n\trsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
break; break;
case 6: /* bset */ case 6: /* bset */
...@@ -1132,6 +1156,7 @@ output_inline_const (mode, operands) ...@@ -1132,6 +1156,7 @@ output_inline_const (mode, operands)
} }
/* Output a move of a word or less value. */ /* Output a move of a word or less value. */
const char * const char *
mcore_output_move (insn, operands, mode) mcore_output_move (insn, operands, mode)
rtx insn ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED;
...@@ -1170,10 +1195,10 @@ mcore_output_move (insn, operands, mode) ...@@ -1170,10 +1195,10 @@ mcore_output_move (insn, operands, mode)
else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */ else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */
return output_inline_const (SImode, operands); /* 1-2 insns */ return output_inline_const (SImode, operands); /* 1-2 insns */
else else
return "lrw\t%0,%x1\t// %1"; /* get it from literal pool */ return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
} }
else else
return "lrw\t%0, %1"; /* into the literal pool */ return "lrw\t%0, %1"; /* Into the literal pool. */
} }
else if (GET_CODE (dst) == MEM) /* m-r */ else if (GET_CODE (dst) == MEM) /* m-r */
return "stw\t%1,%0"; return "stw\t%1,%0";
...@@ -1185,6 +1210,7 @@ mcore_output_move (insn, operands, mode) ...@@ -1185,6 +1210,7 @@ mcore_output_move (insn, operands, mode)
Useful for things where we've gotten into trouble and think we'd Useful for things where we've gotten into trouble and think we'd
be doing an lrw into r15 (forbidden). This lets us get out of be doing an lrw into r15 (forbidden). This lets us get out of
that pickle even after register allocation. */ that pickle even after register allocation. */
const char * const char *
mcore_output_inline_const_forced (insn, operands, mode) mcore_output_inline_const_forced (insn, operands, mode)
rtx insn ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED;
...@@ -1272,6 +1298,7 @@ mcore_output_inline_const_forced (insn, operands, mode) ...@@ -1272,6 +1298,7 @@ mcore_output_inline_const_forced (insn, operands, mode)
/* Return a sequence of instructions to perform DI or DF move. /* Return a sequence of instructions to perform DI or DF move.
Since the MCORE cannot move a DI or DF in one instruction, we have Since the MCORE cannot move a DI or DF in one instruction, we have
to take care when we see overlapping source and dest registers. */ to take care when we see overlapping source and dest registers. */
const char * const char *
mcore_output_movedouble (operands, mode) mcore_output_movedouble (operands, mode)
rtx operands[]; rtx operands[];
...@@ -1286,6 +1313,7 @@ mcore_output_movedouble (operands, mode) ...@@ -1286,6 +1313,7 @@ mcore_output_movedouble (operands, mode)
{ {
int dstreg = REGNO (dst); int dstreg = REGNO (dst);
int srcreg = REGNO (src); int srcreg = REGNO (src);
/* Ensure the second source not overwritten. */ /* Ensure the second source not overwritten. */
if (srcreg + 1 == dstreg) if (srcreg + 1 == dstreg)
return "mov %R0,%R1\n\tmov %0,%1"; return "mov %R0,%R1\n\tmov %0,%1";
...@@ -1314,13 +1342,14 @@ mcore_output_movedouble (operands, mode) ...@@ -1314,13 +1342,14 @@ mcore_output_movedouble (operands, mode)
else else
abort (); abort ();
/* ??? length attribute is wrong here */ /* ??? length attribute is wrong here. */
if (dstreg == basereg) if (dstreg == basereg)
{ {
/* just load them in reverse order */ /* Just load them in reverse order. */
return "ldw\t%R0,%R1\n\tldw\t%0,%1"; return "ldw\t%R0,%R1\n\tldw\t%0,%1";
/* XXX: alternative: move basereg to basereg+1 /* XXX: alternative: move basereg to basereg+1
* and then fall through */ and then fall through. */
} }
else else
return "ldw\t%0,%1\n\tldw\t%R0,%R1"; return "ldw\t%0,%1\n\tldw\t%R0,%R1";
...@@ -1376,6 +1405,7 @@ mcore_output_movedouble (operands, mode) ...@@ -1376,6 +1405,7 @@ mcore_output_movedouble (operands, mode)
/* Predicates used by the templates. */ /* Predicates used by the templates. */
/* Non zero if OP can be source of a simple move operation. */ /* Non zero if OP can be source of a simple move operation. */
int int
mcore_general_movsrc_operand (op, mode) mcore_general_movsrc_operand (op, mode)
rtx op; rtx op;
...@@ -1389,6 +1419,7 @@ mcore_general_movsrc_operand (op, mode) ...@@ -1389,6 +1419,7 @@ mcore_general_movsrc_operand (op, mode)
} }
/* Non zero if OP can be destination of a simple move operation. */ /* Non zero if OP can be destination of a simple move operation. */
int int
mcore_general_movdst_operand (op, mode) mcore_general_movdst_operand (op, mode)
rtx op; rtx op;
...@@ -1401,6 +1432,7 @@ mcore_general_movdst_operand (op, mode) ...@@ -1401,6 +1432,7 @@ mcore_general_movdst_operand (op, mode)
} }
/* Nonzero if OP is a normal arithmetic register. */ /* Nonzero if OP is a normal arithmetic register. */
int int
mcore_arith_reg_operand (op, mode) mcore_arith_reg_operand (op, mode)
rtx op; rtx op;
...@@ -1420,6 +1452,7 @@ mcore_arith_reg_operand (op, mode) ...@@ -1420,6 +1452,7 @@ mcore_arith_reg_operand (op, mode)
/* Non zero if OP should be recognized during reload for an ixh/ixw /* Non zero if OP should be recognized during reload for an ixh/ixw
operand. See the ixh/ixw patterns. */ operand. See the ixh/ixw patterns. */
int int
mcore_reload_operand (op, mode) mcore_reload_operand (op, mode)
rtx op; rtx op;
...@@ -1435,6 +1468,7 @@ mcore_reload_operand (op, mode) ...@@ -1435,6 +1468,7 @@ mcore_reload_operand (op, mode)
} }
/* Nonzero if OP is a valid source operand for an arithmetic insn. */ /* Nonzero if OP is a valid source operand for an arithmetic insn. */
int int
mcore_arith_J_operand (op, mode) mcore_arith_J_operand (op, mode)
rtx op; rtx op;
...@@ -1450,6 +1484,7 @@ mcore_arith_J_operand (op, mode) ...@@ -1450,6 +1484,7 @@ mcore_arith_J_operand (op, mode)
} }
/* Nonzero if OP is a valid source operand for an arithmetic insn. */ /* Nonzero if OP is a valid source operand for an arithmetic insn. */
int int
mcore_arith_K_operand (op, mode) mcore_arith_K_operand (op, mode)
rtx op; rtx op;
...@@ -1465,6 +1500,7 @@ mcore_arith_K_operand (op, mode) ...@@ -1465,6 +1500,7 @@ mcore_arith_K_operand (op, mode)
} }
/* Nonzero if OP is a valid source operand for a shift or rotate insn. */ /* Nonzero if OP is a valid source operand for a shift or rotate insn. */
int int
mcore_arith_K_operand_not_0 (op, mode) mcore_arith_K_operand_not_0 (op, mode)
rtx op; rtx op;
...@@ -1522,7 +1558,8 @@ mcore_arith_M_operand (op, mode) ...@@ -1522,7 +1558,8 @@ mcore_arith_M_operand (op, mode)
return 0; return 0;
} }
/* Nonzero if OP is a valid source operand for loading */ /* Nonzero if OP is a valid source operand for loading. */
int int
mcore_arith_imm_operand (op, mode) mcore_arith_imm_operand (op, mode)
rtx op; rtx op;
...@@ -1551,7 +1588,8 @@ mcore_arith_any_imm_operand (op, mode) ...@@ -1551,7 +1588,8 @@ mcore_arith_any_imm_operand (op, mode)
return 0; return 0;
} }
/* Nonzero if OP is a valid source operand for a cmov with two consts +/- 1 */ /* Nonzero if OP is a valid source operand for a cmov with two consts +/- 1. */
int int
mcore_arith_O_operand (op, mode) mcore_arith_O_operand (op, mode)
rtx op; rtx op;
...@@ -1567,6 +1605,7 @@ mcore_arith_O_operand (op, mode) ...@@ -1567,6 +1605,7 @@ mcore_arith_O_operand (op, mode)
} }
/* Nonzero if OP is a valid source operand for a btsti. */ /* Nonzero if OP is a valid source operand for a btsti. */
int int
mcore_literal_K_operand (op, mode) mcore_literal_K_operand (op, mode)
rtx op; rtx op;
...@@ -1579,6 +1618,7 @@ mcore_literal_K_operand (op, mode) ...@@ -1579,6 +1618,7 @@ mcore_literal_K_operand (op, mode)
} }
/* Nonzero if OP is a valid source operand for an add/sub insn. */ /* Nonzero if OP is a valid source operand for an add/sub insn. */
int int
mcore_addsub_operand (op, mode) mcore_addsub_operand (op, mode)
rtx op; rtx op;
...@@ -1596,7 +1636,7 @@ mcore_addsub_operand (op, mode) ...@@ -1596,7 +1636,7 @@ mcore_addsub_operand (op, mode)
constants may not directly be used in an add/sub, they may if first loaded constants may not directly be used in an add/sub, they may if first loaded
into a register. Thus, this predicate should indicate that they are valid, into a register. Thus, this predicate should indicate that they are valid,
and the constraint in mcore.md should control whether an additional load to and the constraint in mcore.md should control whether an additional load to
register is needed. (see mcore.md, addsi) -- DAC 4/2/1998 */ register is needed. (see mcore.md, addsi). -- DAC 4/2/1998 */
/* /*
if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op))) if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op)))
return 1; return 1;
...@@ -1607,6 +1647,7 @@ mcore_addsub_operand (op, mode) ...@@ -1607,6 +1647,7 @@ mcore_addsub_operand (op, mode)
} }
/* Nonzero if OP is a valid source operand for a compare operation. */ /* Nonzero if OP is a valid source operand for a compare operation. */
int int
mcore_compare_operand (op, mode) mcore_compare_operand (op, mode)
rtx op; rtx op;
...@@ -1622,6 +1663,7 @@ mcore_compare_operand (op, mode) ...@@ -1622,6 +1663,7 @@ mcore_compare_operand (op, mode)
} }
/* Expand insert bit field. BRC */ /* Expand insert bit field. BRC */
int int
mcore_expand_insv (operands) mcore_expand_insv (operands)
rtx operands[]; rtx operands[];
...@@ -1634,11 +1676,10 @@ mcore_expand_insv (operands) ...@@ -1634,11 +1676,10 @@ mcore_expand_insv (operands)
/* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191) /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
for width==1 must be removed. Look around line 368. This is something for width==1 must be removed. Look around line 368. This is something
we really want the md part to do. */ we really want the md part to do. */
if (width == 1 && GET_CODE (operands[3]) == CONST_INT) if (width == 1 && GET_CODE (operands[3]) == CONST_INT)
{ {
/* Do directly with bseti or bclri */ /* Do directly with bseti or bclri. */
/* RBE: 2/97 consider only low bit of constant */ /* RBE: 2/97 consider only low bit of constant. */
if ((INTVAL(operands[3])&1) == 0) if ((INTVAL(operands[3])&1) == 0)
{ {
mask = ~(1 << posn); mask = ~(1 << posn);
...@@ -1656,7 +1697,7 @@ mcore_expand_insv (operands) ...@@ -1656,7 +1697,7 @@ mcore_expand_insv (operands)
} }
/* Look at some bitfield placements that we aren't interested /* Look at some bitfield placements that we aren't interested
* in handling ourselves, unless specifically directed to do so */ in handling ourselves, unless specifically directed to do so. */
if (! TARGET_W_FIELD) if (! TARGET_W_FIELD)
return 0; /* Generally, give up about now. */ return 0; /* Generally, give up about now. */
...@@ -1765,6 +1806,7 @@ mcore_load_multiple_operation (op, mode) ...@@ -1765,6 +1806,7 @@ mcore_load_multiple_operation (op, mode)
} }
/* Similar, but tests for store multiple. */ /* Similar, but tests for store multiple. */
int int
mcore_store_multiple_operation (op, mode) mcore_store_multiple_operation (op, mode)
rtx op; rtx op;
...@@ -1936,7 +1978,7 @@ mcore_expand_block_move (dst_mem, src_mem, operands) ...@@ -1936,7 +1978,7 @@ mcore_expand_block_move (dst_mem, src_mem, operands)
align = 4; align = 4;
/* RBE: bumped 1 and 2 byte align from 1 and 2 to 4 and 8 bytes before /* RBE: bumped 1 and 2 byte align from 1 and 2 to 4 and 8 bytes before
we give up and go to memcpy.. */ we give up and go to memcpy. */
if ((align == 4 && (bytes <= 4*4 if ((align == 4 && (bytes <= 4*4
|| ((bytes & 01) == 0 && bytes <= 8*4) || ((bytes & 01) == 0 && bytes <= 8*4)
|| ((bytes & 03) == 0 && bytes <= 16*4))) || ((bytes & 03) == 0 && bytes <= 16*4)))
...@@ -1958,6 +2000,7 @@ mcore_expand_block_move (dst_mem, src_mem, operands) ...@@ -1958,6 +2000,7 @@ mcore_expand_block_move (dst_mem, src_mem, operands)
/* Code to generate prologue and epilogue sequences. */ /* Code to generate prologue and epilogue sequences. */
static int number_of_regs_before_varargs; static int number_of_regs_before_varargs;
/* Set by SETUP_INCOMING_VARARGS to indicate to prolog that this is /* Set by SETUP_INCOMING_VARARGS to indicate to prolog that this is
for a varargs function. */ for a varargs function. */
static int current_function_anonymous_args; static int current_function_anonymous_args;
...@@ -2050,7 +2093,7 @@ layout_mcore_frame (infp) ...@@ -2050,7 +2093,7 @@ layout_mcore_frame (infp)
infp->reg_growth = growths; infp->reg_growth = growths;
infp->local_growth = growths; infp->local_growth = growths;
/* If we haven't already folded it in... */ /* If we haven't already folded it in. */
if (outbounds) if (outbounds)
infp->growth[growths++] = outbounds; infp->growth[growths++] = outbounds;
...@@ -2098,7 +2141,7 @@ layout_mcore_frame (infp) ...@@ -2098,7 +2141,7 @@ layout_mcore_frame (infp)
assert (all == 0); assert (all == 0);
/* Finish off if we need to do so... */ /* Finish off if we need to do so. */
if (outbounds) if (outbounds)
infp->growth[growths++] = outbounds; infp->growth[growths++] = outbounds;
...@@ -2129,7 +2172,7 @@ layout_mcore_frame (infp) ...@@ -2129,7 +2172,7 @@ layout_mcore_frame (infp)
infp->growth[growths++] = step; infp->growth[growths++] = step;
infp->local_growth = growths; infp->local_growth = growths;
/* If there's any left to be done... */ /* If there's any left to be done. */
if (outbounds) if (outbounds)
infp->growth[growths++] = outbounds; infp->growth[growths++] = outbounds;
...@@ -2137,17 +2180,14 @@ layout_mcore_frame (infp) ...@@ -2137,17 +2180,14 @@ layout_mcore_frame (infp)
} }
/* XXX: optimizations that we'll want to play with.... /* XXX: optimizations that we'll want to play with....
* -- regarg is not aligned, but it's a small number of registers; -- regarg is not aligned, but it's a small number of registers;
* use some of localsize so that regarg is aligned and then use some of localsize so that regarg is aligned and then
* save the registers. save the registers. */
*
*/
/* Simple encoding; plods down the stack buying the pieces as it goes. /* Simple encoding; plods down the stack buying the pieces as it goes.
* -- does not optimize space consumption. -- does not optimize space consumption.
* -- does not attempt to optimize instruction counts. -- does not attempt to optimize instruction counts.
* -- but it is safe for all alignments. -- but it is safe for all alignments. */
*/
if (regarg % STACK_BYTES != 0) if (regarg % STACK_BYTES != 0)
infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES); infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES);
...@@ -2193,6 +2233,7 @@ layout_mcore_frame (infp) ...@@ -2193,6 +2233,7 @@ layout_mcore_frame (infp)
/* Define the offset between two registers, one to be eliminated, and /* Define the offset between two registers, one to be eliminated, and
the other its replacement, at the start of a routine. */ the other its replacement, at the start of a routine. */
int int
mcore_initial_elimination_offset (from, to) mcore_initial_elimination_offset (from, to)
int from; int from;
...@@ -2224,6 +2265,7 @@ mcore_initial_elimination_offset (from, to) ...@@ -2224,6 +2265,7 @@ mcore_initial_elimination_offset (from, to)
} }
/* Keep track of some information about varargs for the prolog. */ /* Keep track of some information about varargs for the prolog. */
void void
mcore_setup_incoming_varargs (args_so_far, mode, type, ptr_pretend_size) mcore_setup_incoming_varargs (args_so_far, mode, type, ptr_pretend_size)
CUMULATIVE_ARGS args_so_far; CUMULATIVE_ARGS args_so_far;
...@@ -2421,7 +2463,6 @@ mcore_expand_epilog () ...@@ -2421,7 +2463,6 @@ mcore_expand_epilog ()
/* Make sure we've shrunk stack back to the point where the registers /* Make sure we've shrunk stack back to the point where the registers
were laid down. This is typically 0/1 iterations. Then pull the were laid down. This is typically 0/1 iterations. Then pull the
register save information back off the stack. */ register save information back off the stack. */
while (growth >= fi.reg_growth) while (growth >= fi.reg_growth)
output_stack_adjust ( 1, fi.growth[growth--]); output_stack_adjust ( 1, fi.growth[growth--]);
...@@ -2459,7 +2500,7 @@ mcore_expand_epilog () ...@@ -2459,7 +2500,7 @@ mcore_expand_epilog ()
} }
/* Give back anything else. */ /* Give back anything else. */
/* XXX: Should accumuate total and then give it back... */ /* XXX: Should accumuate total and then give it back. */
while (growth >= 0) while (growth >= 0)
output_stack_adjust ( 1, fi.growth[growth--]); output_stack_adjust ( 1, fi.growth[growth--]);
} }
...@@ -2534,6 +2575,7 @@ static int pool_size; ...@@ -2534,6 +2575,7 @@ static int pool_size;
/* Dump out any constants accumulated in the final pass. These /* Dump out any constants accumulated in the final pass. These
will only be labels. */ will only be labels. */
const char * const char *
mcore_output_jump_label_table () mcore_output_jump_label_table ()
{ {
...@@ -2585,8 +2627,7 @@ mcore_dependent_simplify_rtx (x, int_op0_mode, last, in_dest, general_simplify) ...@@ -2585,8 +2627,7 @@ mcore_dependent_simplify_rtx (x, int_op0_mode, last, in_dest, general_simplify)
enum machine_mode mode = GET_MODE (x); enum machine_mode mode = GET_MODE (x);
enum rtx_code code = GET_CODE (x); enum rtx_code code = GET_CODE (x);
/* always simplify unless explicitly asked not to */ /* Always simplify unless explicitly asked not to. */
* general_simplify = 1; * general_simplify = 1;
if (code == IF_THEN_ELSE) if (code == IF_THEN_ELSE)
...@@ -2624,6 +2665,7 @@ mcore_dependent_simplify_rtx (x, int_op0_mode, last, in_dest, general_simplify) ...@@ -2624,6 +2665,7 @@ mcore_dependent_simplify_rtx (x, int_op0_mode, last, in_dest, general_simplify)
#endif #endif
/* Check whether insn is a candidate for a conditional. */ /* Check whether insn is a candidate for a conditional. */
static cond_type static cond_type
is_cond_candidate (insn) is_cond_candidate (insn)
rtx insn; rtx insn;
...@@ -2693,6 +2735,7 @@ is_cond_candidate (insn) ...@@ -2693,6 +2735,7 @@ is_cond_candidate (insn)
/* Emit a conditional version of insn and replace the old insn with the /* Emit a conditional version of insn and replace the old insn with the
new one. Return the new insn if emitted. */ new one. Return the new insn if emitted. */
static rtx static rtx
emit_new_cond_insn (insn, cond) emit_new_cond_insn (insn, cond)
rtx insn; rtx insn;
...@@ -2950,6 +2993,7 @@ conditionalize_block (first) ...@@ -2950,6 +2993,7 @@ conditionalize_block (first)
but, the pay back probably isn't really worth the effort (we'd have but, the pay back probably isn't really worth the effort (we'd have
to update all reg/flow/notes/links/etc to make it work - and stick it to update all reg/flow/notes/links/etc to make it work - and stick it
in before cse 2). */ in before cse 2). */
static void static void
conditionalize_optimization (first) conditionalize_optimization (first)
rtx first; rtx first;
...@@ -2964,6 +3008,7 @@ static int saved_warn_return_type = -1; ...@@ -2964,6 +3008,7 @@ static int saved_warn_return_type = -1;
static int saved_warn_return_type_count = 0; static int saved_warn_return_type_count = 0;
/* This function is called from toplev.c before reorg. */ /* This function is called from toplev.c before reorg. */
void void
mcore_dependent_reorg (first) mcore_dependent_reorg (first)
rtx first; rtx first;
...@@ -2971,7 +3016,7 @@ mcore_dependent_reorg (first) ...@@ -2971,7 +3016,7 @@ mcore_dependent_reorg (first)
/* Reset this variable. */ /* Reset this variable. */
current_function_anonymous_args = 0; current_function_anonymous_args = 0;
/* Restore the warn_return_type if it has been altered */ /* Restore the warn_return_type if it has been altered. */
if (saved_warn_return_type != -1) if (saved_warn_return_type != -1)
{ {
/* Only restore the value if we have reached another function. /* Only restore the value if we have reached another function.
......
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