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Commit 467e6f1b by Kugan Vivekanandarajah Committed by Kugan Vivekanandarajah
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aarch64-simd.md (aarch64_ld1x2<VQ:mode>): New. 

gcc/ChangeLog:

2017-12-27  Kugan Vivekanandarajah  <kuganv@linaro.org>

	* config/aarch64/aarch64-simd.md (aarch64_ld1x2<VQ:mode>): New.
	(aarch64_ld1x2<VDC:mode>): Likewise.
	(aarch64_simd_ld1<mode>_x2): Likewise.
	(aarch64_simd_ld1<mode>_x2): Likewise.
	* config/aarch64/arm_neon.h (vld1_u8_x2): New.
	(vld1_s8_x2): Likewise.
	(vld1_u16_x2): Likewise.
	(vld1_s16_x2): Likewise.
	(vld1_u32_x2): Likewise.
	(vld1_s32_x2): Likewise.
	(vld1_u64_x2): Likewise.
	(vld1_s64_x2): Likewise.
	(vld1_f16_x2): Likewise.
	(vld1_f32_x2): Likewise.
	(vld1_f64_x2): Likewise.
	(vld1_p8_x2): Likewise.
	(vld1_p16_x2): Likewise.
	(vld1_p64_x2): Likewise.
	(vld1q_u8_x2): Likewise.
	(vld1q_s8_x2): Likewise.
	(vld1q_u16_x2): Likewise.
	(vld1q_s16_x2): Likewise.
	(vld1q_u32_x2): Likewise.
	(vld1q_s32_x2): Likewise.
	(vld1q_u64_x2): Likewise.
	(vld1q_s64_x2): Likewise.
	(vld1q_f16_x2): Likewise.
	(vld1q_f32_x2): Likewise.
	(vld1q_f64_x2): Likewise.
	(vld1q_p8_x2): Likewise.
	(vld1q_p16_x2): Likewise.
	(vld1q_p64_x2): Likewise.

gcc/testsuite/ChangeLog:

2017-12-27  Kugan Vivekanandarajah  <kuganv@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: New test.

From-SVN: r256010
parent 96863f32
Showing with 163 additions and 2 deletions
gcc/ChangeLog
2017-12-27 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/aarch64/aarch64-simd.md (aarch64_ld1x2<VQ:mode>): New.
(aarch64_ld1x2<VDC:mode>): Likewise.
(aarch64_simd_ld1<mode>_x2): Likewise.
(aarch64_simd_ld1<mode>_x2): Likewise.
* config/aarch64/arm_neon.h (vld1_u8_x2): New.
(vld1_s8_x2): Likewise.
(vld1_u16_x2): Likewise.
(vld1_s16_x2): Likewise.
(vld1_u32_x2): Likewise.
(vld1_s32_x2): Likewise.
(vld1_u64_x2): Likewise.
(vld1_s64_x2): Likewise.
(vld1_f16_x2): Likewise.
(vld1_f32_x2): Likewise.
(vld1_f64_x2): Likewise.
(vld1_p8_x2): Likewise.
(vld1_p16_x2): Likewise.
(vld1_p64_x2): Likewise.
(vld1q_u8_x2): Likewise.
(vld1q_s8_x2): Likewise.
(vld1q_u16_x2): Likewise.
(vld1q_s16_x2): Likewise.
(vld1q_u32_x2): Likewise.
(vld1q_s32_x2): Likewise.
(vld1q_u64_x2): Likewise.
(vld1q_s64_x2): Likewise.
(vld1q_f16_x2): Likewise.
(vld1q_f32_x2): Likewise.
(vld1q_f64_x2): Likewise.
(vld1q_p8_x2): Likewise.
(vld1q_p16_x2): Likewise.
(vld1q_p64_x2): Likewise.
2017-12-27 Martin Liska <mliska@suse.cz>
PR tree-optimization/83552
gcc/config/aarch64/aarch64-simd-builtins.def
......@@ -86,6 +86,10 @@
VAR1 (SETREGP, set_qregoi, 0, v2di)
VAR1 (SETREGP, set_qregci, 0, v2di)
VAR1 (SETREGP, set_qregxi, 0, v2di)
/* Implemented by aarch64_ld1x2<VQ:mode>. */
BUILTIN_VQ (LOADSTRUCT, ld1x2, 0)
/* Implemented by aarch64_ld1x2<VDC:mode>. */
BUILTIN_VDC (LOADSTRUCT, ld1x2, 0)
/* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */
BUILTIN_VDC (LOADSTRUCT, ld2, 0)
BUILTIN_VDC (LOADSTRUCT, ld3, 0)
......@@ -571,4 +575,4 @@
BUILTIN_GPI (UNOP, fix_truncdf, 2)
BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2)
BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2)
BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
\ No newline at end of file
BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
gcc/config/aarch64/aarch64-simd.md
......@@ -5296,6 +5296,33 @@
DONE;
})
(define_expand "aarch64_ld1x2<VQ:mode>"
[(match_operand:OI 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "r")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
machine_mode mode = OImode;
rtx mem = gen_rtx_MEM (mode, operands[1]);
emit_insn (gen_aarch64_simd_ld1<VQ:mode>_x2 (operands[0], mem));
DONE;
})
(define_expand "aarch64_ld1x2<VDC:mode>"
[(match_operand:OI 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "r")
(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
machine_mode mode = OImode;
rtx mem = gen_rtx_MEM (mode, operands[1]);
emit_insn (gen_aarch64_simd_ld1<VDC:mode>_x2 (operands[0], mem));
DONE;
})
(define_expand "aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>"
[(match_operand:VSTRUCT 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "w")
......@@ -5692,6 +5719,27 @@
[(set_attr "type" "neon_load1_all_lanes")]
)
(define_insn "aarch64_simd_ld1<mode>_x2"
[(set (match_operand:OI 0 "register_operand" "=w")
(unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_LD1))]
"TARGET_SIMD"
"ld1\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
[(set_attr "type" "neon_load1_2reg<q>")]
)
(define_insn "aarch64_simd_ld1<mode>_x2"
[(set (match_operand:OI 0 "register_operand" "=w")
(unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")
(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_LD1))]
"TARGET_SIMD"
"ld1\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
[(set_attr "type" "neon_load1_2reg<q>")]
)
(define_insn "aarch64_frecpe<mode>"
[(set (match_operand:VHSDF 0 "register_operand" "=w")
(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")]
......
gcc/testsuite/ChangeLog
2017-12-27 Kugan Vivekanandarajah <kuganv@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: New test.
2017-12-27 Martin Liska <mliska@suse.cz>
PR tree-optimization/83552
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c 0 → 100644
/* { dg-do run } */
/* { dg-options "-O3" } */
#include <arm_neon.h>
extern void abort (void);
#define TESTMETH(BASE, ELTS, SUFFIX) \
int __attribute__ ((noinline)) \
test_vld##SUFFIX##_x2 () \
{ \
BASE##_t data[ELTS * 2]; \
BASE##_t temp[ELTS * 2]; \
BASE##x##ELTS##x##2##_t vectors; \
int i,j; \
for (i = 0; i < ELTS * 2; i++) \
data [i] = (BASE##_t) 2*i + 1; \
asm volatile ("" : : : "memory"); \
vectors = vld1##SUFFIX##_x2 (data); \
vst1##SUFFIX (temp, vectors.val[0]); \
vst1##SUFFIX (&temp[ELTS], vectors.val[1]); \
asm volatile ("" : : : "memory"); \
for (j = 0; j < ELTS * 2; j++) \
if (temp[j] != data[j]) \
return 1; \
return 0; \
}
#define VARIANTS(VARIANT) \
VARIANT (uint8, 8, _u8) \
VARIANT (uint16, 4, _u16) \
VARIANT (uint32, 2, _u32) \
VARIANT (uint64, 1, _u64) \
VARIANT (int8, 8, _s8) \
VARIANT (int16, 4, _s16) \
VARIANT (int32, 2, _s32) \
VARIANT (int64, 1, _s64) \
VARIANT (poly8, 8, _p8) \
VARIANT (poly16, 4, _p16) \
VARIANT (float16, 4, _f16) \
VARIANT (float32, 2, _f32) \
VARIANT (float64, 1, _f64) \
VARIANT (uint8, 16, q_u8) \
VARIANT (uint16, 8, q_u16) \
VARIANT (uint32, 4, q_u32) \
VARIANT (uint64, 2, q_u64) \
VARIANT (int8, 16, q_s8) \
VARIANT (int16, 8, q_s16) \
VARIANT (int32, 4, q_s32) \
VARIANT (int64, 2, q_s64) \
VARIANT (poly8, 16, q_p8) \
VARIANT (poly16, 8, q_p16) \
VARIANT (float16, 8, q_f16) \
VARIANT (float32, 4, q_f32) \
VARIANT (float64, 2, q_f64)
/* Tests of vld1_x2 and vld1q_x2. */
VARIANTS (TESTMETH)
#define CHECK(BASE, ELTS, SUFFIX) \
if (test_vld##SUFFIX##_x2 () != 0) \
abort ();
int
main (int argc, char **argv)
{
VARIANTS (CHECK)
return 0;
}
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