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Commit 3e5c062e by Wilco Dijkstra
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[AArch64] Fix lane specifier syntax 

The syntax for lane specifiers uses a vector element rather than a vector:

fmls    v0.2s, v1.2s, v1.s[1]  // rather than v1.2s[1]

Fix all the lane specifiers to use Vetype which uses the correct element type.

    gcc/
	* aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
	(aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
	(aarch64_mls_elt<mode>): Likewise.
	(aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
	(aarch64_fma4_elt<mode>): Likewise.
	(aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
	(aarch64_fma4_elt_to_64v2df): Likewise.
	(aarch64_fnma4_elt<mode>): Likewise.
	(aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
	(aarch64_fnma4_elt_to_64v2df): Likewise.

    testsuite/
	* gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax.
	* gcc.target/aarch64/fmls_intrinsic_1.c: Likewise.
	* gcc.target/aarch64/mla_intrinsic_1.c: Likewise.
	* gcc.target/aarch64/mls_intrinsic_1.c: Likewise.
parent 4a5c938b
Showing with 40 additions and 20 deletions
gcc/ChangeLog
2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
* aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
(aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
(aarch64_mls_elt<mode>): Likewise.
(aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fma4_elt<mode>): Likewise.
(aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fma4_elt_to_64v2df): Likewise.
(aarch64_fnma4_elt<mode>): Likewise.
(aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fnma4_elt_to_64v2df): Likewise.
2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
......
gcc/config/aarch64/aarch64-simd.md
......@@ -1350,7 +1350,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
......@@ -1368,7 +1368,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
......@@ -1408,7 +1408,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
......@@ -1426,7 +1426,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
......@@ -2003,7 +2003,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
......@@ -2020,7 +2020,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
......@@ -2048,7 +2048,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
return "fmla\\t%0.2d, %3.2d, %1.2d[%2]";
return "fmla\\t%0.2d, %3.2d, %1.d[%2]";
}
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
......@@ -2077,7 +2077,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
......@@ -2095,7 +2095,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
......@@ -2125,7 +2125,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
return "fmls\\t%0.2d, %3.2d, %1.2d[%2]";
return "fmls\\t%0.2d, %3.2d, %1.d[%2]";
}
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
......
gcc/testsuite/ChangeLog
2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
* gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax.
* gcc.target/aarch64/fmls_intrinsic_1.c: Likewise.
* gcc.target/aarch64/mla_intrinsic_1.c: Likewise.
* gcc.target/aarch64/mls_intrinsic_1.c: Likewise.
2020-03-06 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/tumaddsidi4.c: Step-up optimization level.
......
gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
......@@ -98,11 +98,11 @@ main (int argc, char **argv)
/* vfma_laneq_f32.
vfma_lane_f32. */
/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
/* vfmaq_lane_f32.
vfmaq_laneq_f32. */
/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
/* vfma_lane_f64. */
/* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
......@@ -110,6 +110,6 @@ main (int argc, char **argv)
/* vfmaq_lane_f64.
vfma_laneq_f64.
vfmaq_laneq_f64. */
/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */
gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
......@@ -99,11 +99,11 @@ main (int argc, char **argv)
/* vfms_laneq_f32.
vfms_lane_f32. */
/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
/* vfmsq_lane_f32.
vfmsq_laneq_f32. */
/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
/* vfms_lane_f64. */
/* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
......@@ -111,6 +111,6 @@ main (int argc, char **argv)
/* vfmsq_lane_f64.
vfms_laneq_f64.
vfmsq_laneq_f64. */
/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */
gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
......@@ -78,6 +78,6 @@ main (int argc, char **argv)
return 0;
}
/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */
/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */
gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
......@@ -83,6 +83,6 @@ main (int argc, char **argv)
return 0;
}
/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */
/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */
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