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riscv-gcc-1
Commit 3e4be43f by Ulrich Weigand Committed by Andreas Krebbel
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S/390: Memory constraint cleanup 

This fixes an issue with the long displacement memory address
constraints S and T.  These were defined to only accept long
displacement addresses.  This is wrong since a memory constraint must
not reject an address with a 0 displacement.  Reload relies on being
able to turn an invalid memory address into a valid one by reloading
the address into a base register.  The S and T constraints would
reject such an address.

This isn't really a problem for the backend since we used the
constraints with that knowledge there but it is a problem for people
writing inline assemblies.

gcc/ChangeLog:

2016-04-29  Ulrich Weigand  <uweigand@de.ibm.com>

	* config/s390/constraints.md ("U", "W"): Invoke
	s390_mem_constraint with "ZR" and "ZT".
	* config/s390/s390.c (s390_check_qrst_address): Reject invalid
	addresses when using LRA.  Accept also short displacements for S
	and T constraints.  Do not check for long displacement target for
	S and T constraints.
	(s390_mem_constraint): Remove handling of U and W constraints.
	* config/s390/s390.md (various patterns): Remove the short
	displacement constraints (Q and R) if a long displacement
	constraint is present.  Add longdisp as required CPU capability.
	* config/s390/vector.md: Likewise.
	* config/s390/vx-builtins.md: Likewise.

From-SVN: r235626
parent 849b265d
Showing with 274 additions and 230 deletions
gcc/ChangeLog
2016-04-29 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/constraints.md ("U", "W"): Invoke
s390_mem_constraint with "ZR" and "ZT".
* config/s390/s390.c (s390_check_qrst_address): Reject invalid
addresses when using LRA. Accept also short displacements for S
and T constraints. Do not check for long displacement target for
S and T constraints.
(s390_mem_constraint): Remove handling of U and W constraints.
* config/s390/s390.md (various patterns): Remove the short
displacement constraints (Q and R) if a long displacement
constraint is present. Add longdisp as required CPU capability.
* config/s390/vector.md: Likewise.
* config/s390/vx-builtins.md: Likewise.
2016-04-29 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> 2016-04-29 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR target/60040 PR target/60040
......
gcc/config/s390/constraints.md
...@@ -77,8 +77,8 @@ ...@@ -77,8 +77,8 @@
;; B -- Multiple letter constraint followed by Q, R, S, or T: ;; B -- Multiple letter constraint followed by Q, R, S, or T:
;; Memory reference of the type specified by second letter that ;; Memory reference of the type specified by second letter that
;; does *not* refer to a literal pool entry. ;; does *not* refer to a literal pool entry.
;; U -- Pointer with short displacement. (deprecated - use ZQZR) ;; U -- Pointer with short displacement. (deprecated - use ZR)
;; W -- Pointer with long displacement. (deprecated - use ZSZT) ;; W -- Pointer with long displacement. (deprecated - use ZT)
;; Y -- Address style operand without index. ;; Y -- Address style operand without index.
;; ZQ -- Pointer without index register and with short displacement. ;; ZQ -- Pointer without index register and with short displacement.
;; ZR -- Pointer with index register and short displacement. ;; ZR -- Pointer with index register and short displacement.
...@@ -455,8 +455,7 @@ ...@@ -455,8 +455,7 @@
; the TARGET_MEM_CONSTRAINT macro. ; the TARGET_MEM_CONSTRAINT macro.
(define_memory_constraint "m" (define_memory_constraint "m"
"Matches the most general memory address for pre-z10 machines." "Matches the most general memory address for pre-z10 machines."
(match_test "s390_mem_constraint (\"R\", op) (match_test "s390_mem_constraint (\"T\", op)"))
|| s390_mem_constraint (\"T\", op)"))
(define_memory_constraint "AQ" (define_memory_constraint "AQ"
"@internal "@internal
...@@ -512,12 +511,12 @@ ...@@ -512,12 +511,12 @@
(define_address_constraint "U" (define_address_constraint "U"
"Pointer with short displacement. (deprecated - use ZQZR)" "Pointer with short displacement. (deprecated - use ZR)"
(match_test "s390_mem_constraint (\"U\", op)")) (match_test "s390_mem_constraint (\"ZR\", op)"))
(define_address_constraint "W" (define_address_constraint "W"
"Pointer with long displacement. (deprecated - use ZSZT)" "Pointer with long displacement. (deprecated - use ZT)"
(match_test "s390_mem_constraint (\"W\", op)")) (match_test "s390_mem_constraint (\"ZT\", op)"))
(define_address_constraint "ZQ" (define_address_constraint "ZQ"
......
gcc/config/s390/s390.c
...@@ -3116,6 +3116,19 @@ s390_check_qrst_address (char c, rtx op, bool lit_pool_ok) ...@@ -3116,6 +3116,19 @@ s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
decomposed = true; decomposed = true;
} }
/* With reload, we sometimes get intermediate address forms that are
actually invalid as-is, but we need to accept them in the most
generic cases below ('R' or 'T'), since reload will in fact fix
them up. LRA behaves differently here; we never see such forms,
but on the other hand, we need to strictly reject every invalid
address form. Perform this check right up front. */
if (lra_in_progress)
{
if (!decomposed && !s390_decompose_address (op, &addr))
return 0;
decomposed = true;
}
switch (c) switch (c)
{ {
case 'Q': /* no index short displacement */ case 'Q': /* no index short displacement */
...@@ -3140,25 +3153,17 @@ s390_check_qrst_address (char c, rtx op, bool lit_pool_ok) ...@@ -3140,25 +3153,17 @@ s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
break; break;
case 'S': /* no index long displacement */ case 'S': /* no index long displacement */
if (!TARGET_LONG_DISPLACEMENT)
return 0;
if (!decomposed && !s390_decompose_address (op, &addr)) if (!decomposed && !s390_decompose_address (op, &addr))
return 0; return 0;
if (addr.indx) if (addr.indx)
return 0; return 0;
if (s390_short_displacement (addr.disp))
return 0;
break; break;
case 'T': /* with index long displacement */ case 'T': /* with index long displacement */
if (!TARGET_LONG_DISPLACEMENT)
return 0;
/* Any invalid address here will be fixed up by reload, /* Any invalid address here will be fixed up by reload,
so accept it for the most generic constraint. */ so accept it for the most generic constraint. */
if ((decomposed || s390_decompose_address (op, &addr))
&& s390_short_displacement (addr.disp))
return 0;
break; break;
default: default:
return 0; return 0;
} }
...@@ -3167,7 +3172,7 @@ s390_check_qrst_address (char c, rtx op, bool lit_pool_ok) ...@@ -3167,7 +3172,7 @@ s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
/* Evaluates constraint strings described by the regular expression /* Evaluates constraint strings described by the regular expression
([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for ([A|B|Z](Q|R|S|T))|Y and returns 1 if OP is a valid operand for
the constraint given in STR, or 0 else. */ the constraint given in STR, or 0 else. */
int int
...@@ -3197,12 +3202,6 @@ s390_mem_constraint (const char *str, rtx op) ...@@ -3197,12 +3202,6 @@ s390_mem_constraint (const char *str, rtx op)
if (GET_CODE (op) != MEM) if (GET_CODE (op) != MEM)
return 0; return 0;
return s390_check_qrst_address (c, XEXP (op, 0), true); return s390_check_qrst_address (c, XEXP (op, 0), true);
case 'U':
return (s390_check_qrst_address ('Q', op, true)
|| s390_check_qrst_address ('R', op, true));
case 'W':
return (s390_check_qrst_address ('S', op, true)
|| s390_check_qrst_address ('T', op, true));
case 'Y': case 'Y':
/* Simply check for the basic form of a shift count. Reload will /* Simply check for the basic form of a shift count. Reload will
take care of making sure we have a proper base register. */ take care of making sure we have a proper base register. */
......
gcc/config/s390/s390.md
...@@ -797,6 +797,7 @@ ...@@ -797,6 +797,7 @@
tm\t%S0,%b1 tm\t%S0,%b1
tmy\t%S0,%b1" tmy\t%S0,%b1"
[(set_attr "op_type" "SI,SIY") [(set_attr "op_type" "SI,SIY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super,z10_super")]) (set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*tmdi_reg" (define_insn "*tmdi_reg"
...@@ -850,7 +851,7 @@ ...@@ -850,7 +851,7 @@
(compare (compare
(ashiftrt:DI (ashiftrt:DI
(ashift:DI (ashift:DI
(subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
(const_int 32)) (const_int 32)) (const_int 32)) (const_int 32))
(match_operand:DI 1 "const0_operand" ""))) (match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d,d") (set (match_operand:DI 2 "register_operand" "=d,d")
...@@ -865,7 +866,7 @@ ...@@ -865,7 +866,7 @@
; ltr, lt, ltgr, ltg ; ltr, lt, ltgr, ltg
(define_insn "*tst<mode>_extimm" (define_insn "*tst<mode>_extimm"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
(match_operand:GPR 1 "const0_operand" ""))) (match_operand:GPR 1 "const0_operand" "")))
(set (match_operand:GPR 2 "register_operand" "=d,d") (set (match_operand:GPR 2 "register_operand" "=d,d")
(match_dup 0))] (match_dup 0))]
...@@ -879,7 +880,7 @@ ...@@ -879,7 +880,7 @@
; ltr, lt, ltgr, ltg ; ltr, lt, ltgr, ltg
(define_insn "*tst<mode>_cconly_extimm" (define_insn "*tst<mode>_cconly_extimm"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
(match_operand:GPR 1 "const0_operand" ""))) (match_operand:GPR 1 "const0_operand" "")))
(clobber (match_scratch:GPR 2 "=X,d"))] (clobber (match_scratch:GPR 2 "=X,d"))]
"s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
...@@ -912,6 +913,7 @@ ...@@ -912,6 +913,7 @@
icm\t%2,15,%S0 icm\t%2,15,%S0
icmy\t%2,15,%S0" icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY") [(set_attr "op_type" "RR,RS,RSY")
(set_attr "cpu_facility" "*,*,longdisp")
(set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
(define_insn "*tstsi_cconly" (define_insn "*tstsi_cconly"
...@@ -925,6 +927,7 @@ ...@@ -925,6 +927,7 @@
icm\t%2,15,%S0 icm\t%2,15,%S0
icmy\t%2,15,%S0" icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY") [(set_attr "op_type" "RR,RS,RSY")
(set_attr "cpu_facility" "*,*,longdisp")
(set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
(define_insn "*tstdi_cconly_31" (define_insn "*tstdi_cconly_31"
...@@ -960,6 +963,7 @@ ...@@ -960,6 +963,7 @@
icmy\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0
tml\t%0,<max_uint>" tml\t%0,<max_uint>"
[(set_attr "op_type" "RS,RSY,RI") [(set_attr "op_type" "RS,RSY,RI")
(set_attr "cpu_facility" "*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
(define_insn "*tsthiCCT_cconly" (define_insn "*tsthiCCT_cconly"
...@@ -973,6 +977,7 @@ ...@@ -973,6 +977,7 @@
icmy\t%2,3,%S0 icmy\t%2,3,%S0
tml\t%0,65535" tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI") [(set_attr "op_type" "RS,RSY,RI")
(set_attr "cpu_facility" "*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
(define_insn "*tstqiCCT_cconly" (define_insn "*tstqiCCT_cconly"
...@@ -985,6 +990,7 @@ ...@@ -985,6 +990,7 @@
cliy\t%S0,0 cliy\t%S0,0
tml\t%0,255" tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI") [(set_attr "op_type" "SI,SIY,RI")
(set_attr "cpu_facility" "*,longdisp,*")
(set_attr "z10prop" "z10_super,z10_super,z10_super")]) (set_attr "z10prop" "z10_super,z10_super,z10_super")])
(define_insn "*tst<mode>" (define_insn "*tst<mode>"
...@@ -998,6 +1004,7 @@ ...@@ -998,6 +1004,7 @@
icm\t%2,<icm_lo>,%S0 icm\t%2,<icm_lo>,%S0
icmy\t%2,<icm_lo>,%S0" icmy\t%2,<icm_lo>,%S0"
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*tst<mode>_cconly" (define_insn "*tst<mode>_cconly"
...@@ -1010,6 +1017,7 @@ ...@@ -1010,6 +1017,7 @@
icm\t%2,<icm_lo>,%S0 icm\t%2,<icm_lo>,%S0
icmy\t%2,<icm_lo>,%S0" icmy\t%2,<icm_lo>,%S0"
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
...@@ -1018,7 +1026,7 @@ ...@@ -1018,7 +1026,7 @@
(define_insn "*cmpdi_cct" (define_insn "*cmpdi_cct"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
(match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
"s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
"@ "@
cgr\t%0,%1 cgr\t%0,%1
...@@ -1042,6 +1050,7 @@ ...@@ -1042,6 +1050,7 @@
cy\t%0,%1 cy\t%0,%1
#" #"
[(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
(set_attr "cpu_facility" "*,*,*,*,longdisp,*")
(set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
; Compare (signed) instructions ; Compare (signed) instructions
...@@ -1049,7 +1058,7 @@ ...@@ -1049,7 +1058,7 @@
(define_insn "*cmpdi_ccs_sign" (define_insn "*cmpdi_ccs_sign"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b")) "d,T,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))] (match_operand:DI 0 "register_operand" "d, d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
"@ "@
...@@ -1072,7 +1081,7 @@ ...@@ -1072,7 +1081,7 @@
chy\t%0,%1 chy\t%0,%1
chrl\t%0,%1" chrl\t%0,%1"
[(set_attr "op_type" "RX,RXY,RIL") [(set_attr "op_type" "RX,RXY,RIL")
(set_attr "cpu_facility" "*,*,z10") (set_attr "cpu_facility" "*,longdisp,z10")
(set_attr "type" "*,*,larl") (set_attr "type" "*,*,larl")
(set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
...@@ -1087,7 +1096,7 @@ ...@@ -1087,7 +1096,7 @@
(define_insn "*cmpdi_ccs_signhi_rl" (define_insn "*cmpdi_ccs_signhi_rl"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
(match_operand:GPR 0 "register_operand" "d,d")))] (match_operand:GPR 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
"@ "@
...@@ -1113,7 +1122,7 @@ ...@@ -1113,7 +1122,7 @@
c<y>\t%0,%1 c<y>\t%0,%1
c<g>rl\t%0,%1" c<g>rl\t%0,%1"
[(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
(set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
(set_attr "type" "*,*,*,*,*,*,larl") (set_attr "type" "*,*,*,*,*,*,larl")
(set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
...@@ -1146,8 +1155,8 @@ ...@@ -1146,8 +1155,8 @@
(define_insn "*cmpdi_ccu_zero" (define_insn "*cmpdi_ccu_zero"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b")) "d,T,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))] (match_operand:DI 0 "register_operand" "d,d,d")))]
"s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
"@ "@
clgfr\t%0,%1 clgfr\t%0,%1
...@@ -1161,9 +1170,9 @@ ...@@ -1161,9 +1170,9 @@
(define_insn "*cmpdi_ccu" (define_insn "*cmpdi_ccu"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" (compare (match_operand:DI 0 "nonimmediate_operand"
"d, d,d,Q, d, Q,BQ") "d, d,d,Q,d, Q,BQ")
(match_operand:DI 1 "general_operand" (match_operand:DI 1 "general_operand"
"d,Op,b,D,RT,BQ,Q")))] "d,Op,b,D,T,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
"@ "@
clgr\t%0,%1 clgr\t%0,%1
...@@ -1193,7 +1202,7 @@ ...@@ -1193,7 +1202,7 @@
# #
#" #"
[(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
(set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
(set_attr "type" "*,*,larl,*,*,*,*,*") (set_attr "type" "*,*,larl,*,*,*,*,*")
(set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
...@@ -1210,7 +1219,7 @@ ...@@ -1210,7 +1219,7 @@
# #
#" #"
[(set_attr "op_type" "RS,RSY,SIL,SS,SS") [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
(set_attr "cpu_facility" "*,*,z10,*,*") (set_attr "cpu_facility" "*,longdisp,z10,*,*")
(set_attr "z10prop" "*,*,z10_super,*,*")]) (set_attr "z10prop" "*,*,z10_super,*,*")])
(define_insn "*cmpqi_ccu" (define_insn "*cmpqi_ccu"
...@@ -1227,6 +1236,7 @@ ...@@ -1227,6 +1236,7 @@
# #
#" #"
[(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
(set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
(set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
...@@ -1426,8 +1436,8 @@ ...@@ -1426,8 +1436,8 @@
; FIXME: More constants are possible by enabling jxx, jyy constraints ; FIXME: More constants are possible by enabling jxx, jyy constraints
; for TImode (use double-int for the calculations) ; for TImode (use double-int for the calculations)
(define_insn "movti" (define_insn "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o") [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o")
(match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))] (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dPT,d"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
lmg\t%0,%N0,%S1 lmg\t%0,%N0,%S1
...@@ -1635,9 +1645,9 @@ ...@@ -1635,9 +1645,9 @@
(define_insn "*movdi_64" (define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" [(set (match_operand:DI 0 "nonimmediate_operand"
"=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR") "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R")
(match_operand:DI 1 "general_operand" (match_operand:DI 1 "general_operand"
" K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))] " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
lghi\t%0,%h1 lghi\t%0,%h1
...@@ -1743,9 +1753,9 @@ ...@@ -1743,9 +1753,9 @@
(define_insn "*movdi_31" (define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand" [(set (match_operand:DI 0 "nonimmediate_operand"
"=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
(match_operand:DI 1 "general_operand" (match_operand:DI 1 "general_operand"
" Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))]
"!TARGET_ZARCH" "!TARGET_ZARCH"
"@ "@
lm\t%0,%N0,%S1 lm\t%0,%N0,%S1
...@@ -1762,7 +1772,7 @@ ...@@ -1762,7 +1772,7 @@
#" #"
[(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
(set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
(set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
; For a load from a symbol ref we can use one of the target registers ; For a load from a symbol ref we can use one of the target registers
; together with larl to load the address. ; together with larl to load the address.
...@@ -1834,13 +1844,14 @@ ...@@ -1834,13 +1844,14 @@
(define_insn "*la_64" (define_insn "*la_64"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] (match_operand:QI 1 "address_operand" "ZR,ZT"))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
la\t%0,%a1 la\t%0,%a1
lay\t%0,%a1" lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY") [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la") (set_attr "type" "la")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_peephole2 (define_peephole2
...@@ -1897,9 +1908,9 @@ ...@@ -1897,9 +1908,9 @@
(define_insn "*movsi_zarch" (define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand" [(set (match_operand:SI 0 "nonimmediate_operand"
"=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR") "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
(match_operand:SI 1 "general_operand" (match_operand:SI 1 "general_operand"
" K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))] " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
lhi\t%0,%h1 lhi\t%0,%h1
...@@ -2023,13 +2034,14 @@ ...@@ -2023,13 +2034,14 @@
(define_insn "*la_31" (define_insn "*la_31"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] (match_operand:QI 1 "address_operand" "ZR,ZT"))]
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])" "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
"@ "@
la\t%0,%a1 la\t%0,%a1
lay\t%0,%a1" lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY") [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la") (set_attr "type" "la")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_peephole2 (define_peephole2
...@@ -2058,7 +2070,7 @@ ...@@ -2058,7 +2070,7 @@
(define_insn "*la_31_and" (define_insn "*la_31_and"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
(const_int 2147483647)))] (const_int 2147483647)))]
"!TARGET_64BIT" "!TARGET_64BIT"
"@ "@
...@@ -2066,6 +2078,7 @@ ...@@ -2066,6 +2078,7 @@
lay\t%0,%a1" lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY") [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la") (set_attr "type" "la")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_insn_and_split "*la_31_and_cc" (define_insn_and_split "*la_31_and_cc"
...@@ -2084,7 +2097,7 @@ ...@@ -2084,7 +2097,7 @@
(define_insn "force_la_31" (define_insn "force_la_31"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) (match_operand:QI 1 "address_operand" "ZR,ZT"))
(use (const_int 0))] (use (const_int 0))]
"!TARGET_64BIT" "!TARGET_64BIT"
"@ "@
...@@ -2092,6 +2105,7 @@ ...@@ -2092,6 +2105,7 @@
lay\t%0,%a1" lay\t%0,%a1"
[(set_attr "op_type" "RX") [(set_attr "op_type" "RX")
(set_attr "type" "la") (set_attr "type" "la")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
; ;
...@@ -2117,8 +2131,8 @@ ...@@ -2117,8 +2131,8 @@
}) })
(define_insn "*movhi" (define_insn "*movhi"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR") [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
(match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))] (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
"" ""
"@ "@
lr\t%0,%1 lr\t%0,%1
...@@ -2138,7 +2152,7 @@ ...@@ -2138,7 +2152,7 @@
vsteh\t%v1,%0,0" vsteh\t%v1,%0,0"
[(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
(set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
(set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec") (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vec,vec,vec,vec,vec,vec")
(set_attr "z10prop" "z10_fr_E1, (set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1, z10_fwd_A1,
z10_super_E1, z10_super_E1,
...@@ -2182,8 +2196,8 @@ ...@@ -2182,8 +2196,8 @@
}) })
(define_insn "*movqi" (define_insn "*movqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR") [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
(match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))] (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
"" ""
"@ "@
lr\t%0,%1 lr\t%0,%1
...@@ -2203,7 +2217,7 @@ ...@@ -2203,7 +2217,7 @@
vsteb\t%v1,%0,0" vsteb\t%v1,%0,0"
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
(set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
(set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec") (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vec,vec,vec,vec,vec,vec")
(set_attr "z10prop" "z10_fr_E1, (set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1, z10_fwd_A1,
z10_super_E1, z10_super_E1,
...@@ -2236,6 +2250,7 @@ ...@@ -2236,6 +2250,7 @@
ic\t%0,%1 ic\t%0,%1
icy\t%0,%1" icy\t%0,%1"
[(set_attr "op_type" "RX,RXY") [(set_attr "op_type" "RX,RXY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
; ;
...@@ -2251,6 +2266,7 @@ ...@@ -2251,6 +2266,7 @@
icm\t%0,3,%S1 icm\t%0,3,%S1
icmy\t%0,3,%S1" icmy\t%0,3,%S1"
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
; ;
...@@ -2268,6 +2284,7 @@ ...@@ -2268,6 +2284,7 @@
ear\t%0,%1" ear\t%0,%1"
[(set_attr "op_type" "RR,RX,RXY,RRE") [(set_attr "op_type" "RR,RX,RXY,RRE")
(set_attr "type" "lr,load,load,*") (set_attr "type" "lr,load,load,*")
(set_attr "cpu_facility" "*,*,longdisp,*")
(set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
; ;
...@@ -2281,8 +2298,8 @@ ...@@ -2281,8 +2298,8 @@
"") "")
(define_insn "*mov<mode>_64" (define_insn "*mov<mode>_64"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
lzxr\t%0 lzxr\t%0
...@@ -2400,9 +2417,9 @@ ...@@ -2400,9 +2417,9 @@
(define_insn "*mov<mode>_64dfp" (define_insn "*mov<mode>_64dfp"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" [(set (match_operand:DD_DF 0 "nonimmediate_operand"
"=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR") "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,d,v,R")
(match_operand:DD_DF 1 "general_operand" (match_operand:DD_DF 1 "general_operand"
" G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))] " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,d,v,R,v"))]
"TARGET_DFP" "TARGET_DFP"
"@ "@
lzdr\t%0 lzdr\t%0
...@@ -2428,11 +2445,11 @@ ...@@ -2428,11 +2445,11 @@
(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store") fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
(set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*") (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
(set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")]) (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
(define_insn "*mov<mode>_64" (define_insn "*mov<mode>_64"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR") [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T,v,v,R")
(match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))] (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d,v,R,v"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
lzdr\t%0 lzdr\t%0
...@@ -2454,13 +2471,13 @@ ...@@ -2454,13 +2471,13 @@
(set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store") fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
(set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*") (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
(set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")]) (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec")])
(define_insn "*mov<mode>_31" (define_insn "*mov<mode>_31"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" [(set (match_operand:DD_DF 0 "nonimmediate_operand"
"=f,f,f,f,R,T,d,d,Q,S, d,o") "=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand" (match_operand:DD_DF 1 "general_operand"
" G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
"!TARGET_ZARCH" "!TARGET_ZARCH"
"@ "@
lzdr\t%0 lzdr\t%0
...@@ -2478,7 +2495,7 @@ ...@@ -2478,7 +2495,7 @@
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
(set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
(set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
(define_split (define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "") [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
...@@ -2527,9 +2544,9 @@ ...@@ -2527,9 +2544,9 @@
(define_insn "mov<mode>" (define_insn "mov<mode>"
[(set (match_operand:SD_SF 0 "nonimmediate_operand" [(set (match_operand:SD_SF 0 "nonimmediate_operand"
"=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR") "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
(match_operand:SD_SF 1 "general_operand" (match_operand:SD_SF 1 "general_operand"
" G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))] " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
"" ""
"@ "@
lzer\t%0 lzer\t%0
...@@ -2558,7 +2575,7 @@ ...@@ -2558,7 +2575,7 @@
(set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
(set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
(set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")]) (set_attr "cpu_facility" "z196,vec,*,vec,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vec,vec,vec,vec,vec,vec")])
; ;
; movcc instruction pattern ; movcc instruction pattern
...@@ -2578,6 +2595,7 @@ ...@@ -2578,6 +2595,7 @@
sty\t%1,%0" sty\t%1,%0"
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
(set_attr "type" "lr,*,*,load,load,store,store") (set_attr "type" "lr,*,*,load,load,store,store")
(set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
(set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
(set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
...@@ -2701,7 +2719,7 @@ ...@@ -2701,7 +2719,7 @@
(define_insn "*load_multiple_di" (define_insn "*load_multiple_di"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r") [(set (match_operand:DI 1 "register_operand" "=r")
(match_operand:DI 2 "s_operand" "QS"))])] (match_operand:DI 2 "s_operand" "S"))])]
"reload_completed && TARGET_ZARCH" "reload_completed && TARGET_ZARCH"
{ {
int words = XVECLEN (operands[0], 0); int words = XVECLEN (operands[0], 0);
...@@ -2722,6 +2740,7 @@ ...@@ -2722,6 +2740,7 @@
return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
} }
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "lm")]) (set_attr "type" "lm")])
; ;
...@@ -2791,7 +2810,7 @@ ...@@ -2791,7 +2810,7 @@
(define_insn "*store_multiple_di" (define_insn "*store_multiple_di"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (match_operand:DI 1 "s_operand" "=QS") [(set (match_operand:DI 1 "s_operand" "=S")
(match_operand:DI 2 "register_operand" "r"))])] (match_operand:DI 2 "register_operand" "r"))])]
"reload_completed && TARGET_ZARCH" "reload_completed && TARGET_ZARCH"
{ {
...@@ -2814,6 +2833,7 @@ ...@@ -2814,6 +2833,7 @@
return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
} }
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "stm")]) (set_attr "type" "stm")])
;; ;;
...@@ -3670,11 +3690,12 @@ ...@@ -3670,11 +3690,12 @@
icm\t%0,%2,%S1 icm\t%0,%2,%S1
icmy\t%0,%2,%S1" icmy\t%0,%2,%S1"
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*sethighpartdi_64" (define_insn "*sethighpartdi_64"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(unspec:DI [(match_operand:BLK 1 "s_operand" "QS") (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
(match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH" "TARGET_ZARCH"
...@@ -3692,6 +3713,7 @@ ...@@ -3692,6 +3713,7 @@
icm\t%0,%2,%S1 icm\t%0,%2,%S1
icmy\t%0,%2,%S1" icmy\t%0,%2,%S1"
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
; ;
...@@ -3747,7 +3769,7 @@ ...@@ -3747,7 +3769,7 @@
(define_insn_and_split "*pre_z10_extzv<mode>" (define_insn_and_split "*pre_z10_extzv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
(match_operand 2 "nonzero_shift_count_operand" "") (match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0))) (const_int 0)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
...@@ -3771,7 +3793,7 @@ ...@@ -3771,7 +3793,7 @@
(define_insn_and_split "*pre_z10_extv<mode>" (define_insn_and_split "*pre_z10_extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d")
(sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
(match_operand 2 "nonzero_shift_count_operand" "") (match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0))) (const_int 0)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
...@@ -4070,10 +4092,11 @@ ...@@ -4070,10 +4092,11 @@
: "stcmy\t%2,%1,%S0"; : "stcmy\t%2,%1,%S0";
} }
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super,z10_super")]) (set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*insvdi_mem_reghigh" (define_insn "*insvdi_mem_reghigh"
[(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
(match_operand 1 "const_int_operand" "n") (match_operand 1 "const_int_operand" "n")
(const_int 0)) (const_int 0))
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d") (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
...@@ -4156,7 +4179,7 @@ ...@@ -4156,7 +4179,7 @@
(define_insn "*extendsidi2" (define_insn "*extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
lgfr\t%0,%1 lgfr\t%0,%1
...@@ -4200,7 +4223,7 @@ ...@@ -4200,7 +4223,7 @@
(define_insn "*extendhidi2_extimm" (define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
"TARGET_ZARCH && TARGET_EXTIMM" "TARGET_ZARCH && TARGET_EXTIMM"
"@ "@
lghr\t%0,%1 lghr\t%0,%1
...@@ -4213,7 +4236,7 @@ ...@@ -4213,7 +4236,7 @@
(define_insn "*extendhidi2" (define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
"TARGET_ZARCH" "TARGET_ZARCH"
"lgh\t%0,%1" "lgh\t%0,%1"
[(set_attr "op_type" "RXY") [(set_attr "op_type" "RXY")
...@@ -4245,6 +4268,7 @@ ...@@ -4245,6 +4268,7 @@
lh\t%0,%1 lh\t%0,%1
lhy\t%0,%1" lhy\t%0,%1"
[(set_attr "op_type" "RX,RXY") [(set_attr "op_type" "RX,RXY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
; ;
...@@ -4254,7 +4278,7 @@ ...@@ -4254,7 +4278,7 @@
; lbr, lgbr, lb, lgb ; lbr, lgbr, lb, lgb
(define_insn "*extendqi<mode>2_extimm" (define_insn "*extendqi<mode>2_extimm"
[(set (match_operand:GPR 0 "register_operand" "=d,d") [(set (match_operand:GPR 0 "register_operand" "=d,d")
(sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
"TARGET_EXTIMM" "TARGET_EXTIMM"
"@ "@
l<g>br\t%0,%1 l<g>br\t%0,%1
...@@ -4265,7 +4289,7 @@ ...@@ -4265,7 +4289,7 @@
; lb, lgb ; lb, lgb
(define_insn "*extendqi<mode>2" (define_insn "*extendqi<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d")
(sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
"!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
"l<g>b\t%0,%1" "l<g>b\t%0,%1"
[(set_attr "op_type" "RXY") [(set_attr "op_type" "RXY")
...@@ -4310,7 +4334,7 @@ ...@@ -4310,7 +4334,7 @@
(define_insn "*zero_extendsidi2" (define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
llgfr\t%0,%1 llgfr\t%0,%1
...@@ -4327,7 +4351,7 @@ ...@@ -4327,7 +4351,7 @@
(define_insn "*llgt_sidi" (define_insn "*llgt_sidi"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
(const_int 2147483647)))] (const_int 2147483647)))]
"TARGET_ZARCH" "TARGET_ZARCH"
"llgt\t%0,%1" "llgt\t%0,%1"
...@@ -4336,7 +4360,7 @@ ...@@ -4336,7 +4360,7 @@
(define_insn_and_split "*llgt_sidi_split" (define_insn_and_split "*llgt_sidi_split"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
(const_int 2147483647))) (const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH" "TARGET_ZARCH"
...@@ -4349,7 +4373,7 @@ ...@@ -4349,7 +4373,7 @@
(define_insn "*llgt_sisi" (define_insn "*llgt_sisi"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
(const_int 2147483647)))] (const_int 2147483647)))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
...@@ -4423,7 +4447,7 @@ ...@@ -4423,7 +4447,7 @@
; llhrl, llghrl ; llhrl, llghrl
(define_insn "*zero_extendhi<mode>2_z10" (define_insn "*zero_extendhi<mode>2_z10"
[(set (match_operand:GPR 0 "register_operand" "=d,d,d") [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
(zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
"TARGET_Z10" "TARGET_Z10"
"@ "@
ll<g>hr\t%0,%1 ll<g>hr\t%0,%1
...@@ -4437,7 +4461,7 @@ ...@@ -4437,7 +4461,7 @@
; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
[(set (match_operand:GPR 0 "register_operand" "=d,d") [(set (match_operand:GPR 0 "register_operand" "=d,d")
(zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
"TARGET_EXTIMM" "TARGET_EXTIMM"
"@ "@
ll<g><hc>r\t%0,%1 ll<g><hc>r\t%0,%1
...@@ -4448,7 +4472,7 @@ ...@@ -4448,7 +4472,7 @@
; llgh, llgc ; llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2" (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
"TARGET_ZARCH && !TARGET_EXTIMM" "TARGET_ZARCH && !TARGET_EXTIMM"
"llg<hc>\t%0,%1" "llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY") [(set_attr "op_type" "RXY")
...@@ -4456,7 +4480,7 @@ ...@@ -4456,7 +4480,7 @@
(define_insn_and_split "*zero_extendhisi2_31" (define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d") [(set (match_operand:SI 0 "register_operand" "=&d")
(zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH" "!TARGET_ZARCH"
"#" "#"
...@@ -4469,7 +4493,7 @@ ...@@ -4469,7 +4493,7 @@
(define_insn_and_split "*zero_extendqisi2_31" (define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d") [(set (match_operand:SI 0 "register_operand" "=&d")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
"!TARGET_ZARCH" "!TARGET_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
...@@ -4493,7 +4517,7 @@ ...@@ -4493,7 +4517,7 @@
(define_insn "*zero_extendqihi2_64" (define_insn "*zero_extendqihi2_64"
[(set (match_operand:HI 0 "register_operand" "=d") [(set (match_operand:HI 0 "register_operand" "=d")
(zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
"TARGET_ZARCH && !TARGET_EXTIMM" "TARGET_ZARCH && !TARGET_EXTIMM"
"llgc\t%0,%1" "llgc\t%0,%1"
[(set_attr "op_type" "RXY") [(set_attr "op_type" "RXY")
...@@ -4501,7 +4525,7 @@ ...@@ -4501,7 +4525,7 @@
(define_insn_and_split "*zero_extendqihi2_31" (define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d") [(set (match_operand:HI 0 "register_operand" "=&d")
(zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
"!TARGET_ZARCH" "!TARGET_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
...@@ -5213,7 +5237,7 @@ ...@@ -5213,7 +5237,7 @@
(define_insn "*adddi3_sign" (define_insn "*adddi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0"))) (match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH" "TARGET_ZARCH"
...@@ -5225,7 +5249,7 @@ ...@@ -5225,7 +5249,7 @@
(define_insn "*adddi3_zero_cc" (define_insn "*adddi3_zero_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0")) (match_operand:DI 1 "register_operand" "0,0"))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d")
...@@ -5239,7 +5263,7 @@ ...@@ -5239,7 +5263,7 @@
(define_insn "*adddi3_zero_cconly" (define_insn "*adddi3_zero_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0")) (match_operand:DI 1 "register_operand" "0,0"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d"))]
...@@ -5252,7 +5276,7 @@ ...@@ -5252,7 +5276,7 @@
(define_insn "*adddi3_zero" (define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0"))) (match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH" "TARGET_ZARCH"
...@@ -5342,6 +5366,7 @@ ...@@ -5342,6 +5366,7 @@
ah\t%0,%2 ah\t%0,%2
ahy\t%0,%2" ahy\t%0,%2"
[(set_attr "op_type" "RX,RXY") [(set_attr "op_type" "RX,RXY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z196prop" "z196_cracked,z196_cracked")]) (set_attr "z196prop" "z196_cracked,z196_cracked")])
; ;
...@@ -5350,9 +5375,9 @@ ...@@ -5350,9 +5375,9 @@
; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
(define_insn "*add<mode>3" (define_insn "*add<mode>3"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S")
(plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
(match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) )
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" ""
"@ "@
...@@ -5366,7 +5391,7 @@ ...@@ -5366,7 +5391,7 @@
a<y>\t%0,%2 a<y>\t%0,%2
a<g>si\t%0,%c2" a<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
(set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
z10_super_E1,z10_super_E1,z10_super_E1")]) z10_super_E1,z10_super_E1,z10_super_E1")])
...@@ -5389,7 +5414,7 @@ ...@@ -5389,7 +5414,7 @@
al<y>\t%0,%2 al<y>\t%0,%2
al<g>si\t%0,%c2" al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
(set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")]) z10_super_E1,z10_super_E1,z10_super_E1")])
...@@ -5407,16 +5432,16 @@ ...@@ -5407,16 +5432,16 @@
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2" al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_carry2_cc" (define_insn "*add<mode>3_carry2_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
(match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
(match_dup 2))) (match_dup 2)))
(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
(plus:GPR (match_dup 1) (match_dup 2)))] (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
...@@ -5429,7 +5454,7 @@ ...@@ -5429,7 +5454,7 @@
al<y>\t%0,%2 al<y>\t%0,%2
al<g>si\t%0,%c2" al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
(set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")]) z10_super_E1,z10_super_E1,z10_super_E1")])
...@@ -5447,16 +5472,16 @@ ...@@ -5447,16 +5472,16 @@
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2" al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_cc" (define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
(match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
(const_int 0))) (const_int 0)))
(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
(plus:GPR (match_dup 1) (match_dup 2)))] (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)" "s390_match_ccmode (insn, CCLmode)"
"@ "@
...@@ -5469,7 +5494,7 @@ ...@@ -5469,7 +5494,7 @@
al<y>\t%0,%2 al<y>\t%0,%2
al<g>si\t%0,%c2" al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
(set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
*,z10_super_E1,z10_super_E1,z10_super_E1")]) *,z10_super_E1,z10_super_E1,z10_super_E1")])
...@@ -5487,7 +5512,7 @@ ...@@ -5487,7 +5512,7 @@
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2" al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, al, aly, algr, alg, alrk, algrk ; alr, al, aly, algr, alg, alrk, algrk
...@@ -5503,16 +5528,16 @@ ...@@ -5503,16 +5528,16 @@
al<g>\t%0,%2 al<g>\t%0,%2
al<y>\t%0,%2" al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; ahi, afi, aghi, agfi, asi, agsi ; ahi, afi, aghi, agfi, asi, agsi
(define_insn "*add<mode>3_imm_cc" (define_insn "*add<mode>3_imm_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
(match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) (match_operand:GPR 2 "const_int_operand" " K, K,Os,C"))
(const_int 0))) (const_int 0)))
(set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S")
(plus:GPR (match_dup 1) (match_dup 2)))] (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode) "s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
...@@ -5704,7 +5729,7 @@ ...@@ -5704,7 +5729,7 @@
(define_insn "*subdi3_sign" (define_insn "*subdi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0") (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
...@@ -5717,7 +5742,7 @@ ...@@ -5717,7 +5742,7 @@
(define_insn "*subdi3_zero_cc" (define_insn "*subdi3_zero_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d") (set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
...@@ -5731,7 +5756,7 @@ ...@@ -5731,7 +5756,7 @@
(define_insn "*subdi3_zero_cconly" (define_insn "*subdi3_zero_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
...@@ -5744,7 +5769,7 @@ ...@@ -5744,7 +5769,7 @@
(define_insn "*subdi3_zero" (define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0") (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
...@@ -5832,6 +5857,7 @@ ...@@ -5832,6 +5857,7 @@
sh\t%0,%2 sh\t%0,%2
shy\t%0,%2" shy\t%0,%2"
[(set_attr "op_type" "RX,RXY") [(set_attr "op_type" "RX,RXY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z196prop" "z196_cracked,z196_cracked")]) (set_attr "z196prop" "z196_cracked,z196_cracked")])
; ;
...@@ -5851,7 +5877,7 @@ ...@@ -5851,7 +5877,7 @@
s<g>\t%0,%2 s<g>\t%0,%2
s<y>\t%0,%2" s<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk ; slr, sl, sly, slgr, slg, slrk, slgrk
...@@ -5869,7 +5895,7 @@ ...@@ -5869,7 +5895,7 @@
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk ; slr, sl, sly, slgr, slg, slrk, slgrk
...@@ -5886,7 +5912,7 @@ ...@@ -5886,7 +5912,7 @@
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk ; slr, sl, sly, slgr, slg, slrk, slgrk
...@@ -5904,7 +5930,7 @@ ...@@ -5904,7 +5930,7 @@
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk ; slr, sl, sly, slgr, slg, slrk, slgrk
...@@ -5921,7 +5947,7 @@ ...@@ -5921,7 +5947,7 @@
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk ; slr, sl, sly, slgr, slg, slrk, slgrk
...@@ -5938,7 +5964,7 @@ ...@@ -5938,7 +5964,7 @@
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
...@@ -5955,7 +5981,7 @@ ...@@ -5955,7 +5981,7 @@
sl<g>\t%0,%2 sl<g>\t%0,%2
sl<y>\t%0,%2" sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
(set_attr "cpu_facility" "*,z196,*,*") (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
...@@ -6033,7 +6059,7 @@ ...@@ -6033,7 +6059,7 @@
(compare (compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0")) (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
(match_operand:GPR 2 "general_operand" "d,RT")) (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 1))) (match_dup 1)))
(set (match_operand:GPR 0 "register_operand" "=d,d") (set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
...@@ -6050,7 +6076,7 @@ ...@@ -6050,7 +6076,7 @@
(compare (compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0")) (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
(match_operand:GPR 2 "general_operand" "d,RT")) (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 1))) (match_dup 1)))
(clobber (match_scratch:GPR 0 "=d,d"))] (clobber (match_scratch:GPR 0 "=d,d"))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
...@@ -6068,7 +6094,7 @@ ...@@ -6068,7 +6094,7 @@
(compare (compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0")) (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
(match_operand:GPR 2 "general_operand" "d,RT")) (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 2))) (match_dup 2)))
(set (match_operand:GPR 0 "register_operand" "=d,d") (set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
...@@ -6084,7 +6110,7 @@ ...@@ -6084,7 +6110,7 @@
(compare (compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0")) (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
(match_operand:GPR 2 "general_operand" "d,RT")) (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 2))) (match_dup 2)))
(clobber (match_scratch:GPR 0 "=d,d"))] (clobber (match_scratch:GPR 0 "=d,d"))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
...@@ -6099,7 +6125,7 @@ ...@@ -6099,7 +6125,7 @@
(compare (compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0")) (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
(match_operand:GPR 2 "general_operand" "d,RT")) (match_operand:GPR 2 "general_operand" "d,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d") (set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
...@@ -6114,7 +6140,7 @@ ...@@ -6114,7 +6140,7 @@
[(set (match_operand:GPR 0 "register_operand" "=d,d") [(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0")) (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
(match_operand:GPR 2 "general_operand" "d,RT"))) (match_operand:GPR 2 "general_operand" "d,T")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH" "TARGET_CPU_ZARCH"
"@ "@
...@@ -6127,7 +6153,7 @@ ...@@ -6127,7 +6153,7 @@
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (compare
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
(match_operand:GPR 2 "general_operand" "d,RT")) (match_operand:GPR 2 "general_operand" "d,T"))
(match_operand:GPR 3 "s390_slb_comparison" "")) (match_operand:GPR 3 "s390_slb_comparison" ""))
(const_int 0))) (const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d") (set (match_operand:GPR 0 "register_operand" "=d,d")
...@@ -6143,7 +6169,7 @@ ...@@ -6143,7 +6169,7 @@
(define_insn "*sub<mode>3_slb" (define_insn "*sub<mode>3_slb"
[(set (match_operand:GPR 0 "register_operand" "=d,d") [(set (match_operand:GPR 0 "register_operand" "=d,d")
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
(match_operand:GPR 2 "general_operand" "d,RT")) (match_operand:GPR 2 "general_operand" "d,T"))
(match_operand:GPR 3 "s390_slb_comparison" ""))) (match_operand:GPR 3 "s390_slb_comparison" "")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH" "TARGET_CPU_ZARCH"
...@@ -6255,13 +6281,13 @@ ...@@ -6255,13 +6281,13 @@
; locr, loc, stoc, locgr, locg, stocg ; locr, loc, stoc, locgr, locg, stocg
(define_insn_and_split "*mov<mode>cc" (define_insn_and_split "*mov<mode>cc"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,S,S,&d")
(if_then_else:GPR (if_then_else:GPR
(match_operator 1 "s390_comparison" (match_operator 1 "s390_comparison"
[(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c")
(match_operand 5 "const_int_operand" "")]) (match_operand 5 "const_int_operand" "")])
(match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") (match_operand:GPR 3 "nonimmediate_operand" " d,0,S,0,d,0,S")
(match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] (match_operand:GPR 4 "nonimmediate_operand" " 0,d,0,S,0,d,S")))]
"TARGET_Z196" "TARGET_Z196"
"@ "@
loc<g>r%C1\t%0,%3 loc<g>r%C1\t%0,%3
...@@ -6296,7 +6322,7 @@ ...@@ -6296,7 +6322,7 @@
(define_insn "*muldi3_sign" (define_insn "*muldi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0")))] (match_operand:DI 1 "register_operand" "0,0")))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
...@@ -6308,7 +6334,7 @@ ...@@ -6308,7 +6334,7 @@
(define_insn "muldi3" (define_insn "muldi3"
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,K,RT,Os")))] (match_operand:DI 2 "general_operand" "d,K,T,Os")))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
msgr\t%0,%2 msgr\t%0,%2
...@@ -6348,7 +6374,7 @@ ...@@ -6348,7 +6374,7 @@
msfi\t%0,%2" msfi\t%0,%2"
[(set_attr "op_type" "RRE,RI,RX,RXY,RIL") [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
(set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
(set_attr "cpu_facility" "*,*,*,*,z10")]) (set_attr "cpu_facility" "*,*,*,longdisp,z10")])
; ;
; mulsidi3 instruction pattern(s). ; mulsidi3 instruction pattern(s).
...@@ -6375,11 +6401,11 @@ ...@@ -6375,11 +6401,11 @@
; mlr, ml, mlgr, mlg ; mlr, ml, mlgr, mlg
(define_insn "umul<dwh><mode>3" (define_insn "umul<dwh><mode>3"
[(set (match_operand:DW 0 "register_operand" "=d, d") [(set (match_operand:DW 0 "register_operand" "=d,d")
(mult:DW (zero_extend:DW (mult:DW (zero_extend:DW
(match_operand:<DWH> 1 "register_operand" "%0, 0")) (match_operand:<DWH> 1 "register_operand" "%0,0"))
(zero_extend:DW (zero_extend:DW
(match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
"TARGET_CPU_ZARCH" "TARGET_CPU_ZARCH"
"@ "@
ml<tg>r\t%0,%2 ml<tg>r\t%0,%2
...@@ -6479,7 +6505,7 @@ ...@@ -6479,7 +6505,7 @@
(ashift:TI (ashift:TI
(zero_extend:TI (zero_extend:TI
(mod:DI (match_operand:DI 1 "register_operand" "0,0") (mod:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,RT"))) (match_operand:DI 2 "general_operand" "d,T")))
(const_int 64)) (const_int 64))
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
"TARGET_ZARCH" "TARGET_ZARCH"
...@@ -6496,7 +6522,7 @@ ...@@ -6496,7 +6522,7 @@
(zero_extend:TI (zero_extend:TI
(mod:DI (match_operand:DI 1 "register_operand" "0,0") (mod:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,RT")))) (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
(const_int 64)) (const_int 64))
(zero_extend:TI (zero_extend:TI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
...@@ -6555,7 +6581,7 @@ ...@@ -6555,7 +6581,7 @@
(truncate:DI (truncate:DI
(umod:TI (match_operand:TI 1 "register_operand" "0,0") (umod:TI (match_operand:TI 1 "register_operand" "0,0")
(zero_extend:TI (zero_extend:TI
(match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
(const_int 64)) (const_int 64))
(zero_extend:TI (zero_extend:TI
(truncate:DI (truncate:DI
...@@ -6673,7 +6699,7 @@ ...@@ -6673,7 +6699,7 @@
(truncate:SI (truncate:SI
(umod:DI (match_operand:DI 1 "register_operand" "0,0") (umod:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
(const_int 32)) (const_int 32))
(zero_extend:DI (zero_extend:DI
(truncate:SI (truncate:SI
...@@ -6897,10 +6923,10 @@ ...@@ -6897,10 +6923,10 @@
(define_insn "*anddi3_cc" (define_insn "*anddi3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (compare
(and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
(match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) (match_operand:DI 2 "general_operand" " d,d,T,NxxDq"))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d, d, d") (set (match_operand:DI 0 "register_operand" "=d,d,d, d")
(and:DI (match_dup 1) (match_dup 2)))] (and:DI (match_dup 1) (match_dup 2)))]
"TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
"@ "@
...@@ -6915,10 +6941,10 @@ ...@@ -6915,10 +6941,10 @@
(define_insn "*anddi3_cconly" (define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (compare
(and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
(match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) (match_operand:DI 2 "general_operand" " d,d,T,NxxDq"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d, d, d"))] (clobber (match_scratch:DI 0 "=d,d,d, d"))]
"TARGET_ZARCH "TARGET_ZARCH
&& s390_match_ccmode(insn, CCTmode) && s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */ /* Do not steal TM patterns. */
...@@ -6934,12 +6960,12 @@ ...@@ -6934,12 +6960,12 @@
(define_insn "*anddi3" (define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" [(set (match_operand:DI 0 "nonimmediate_operand"
"=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q") "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q")
(and:DI (and:DI
(match_operand:DI 1 "nonimmediate_operand" (match_operand:DI 1 "nonimmediate_operand"
"%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0") "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0")
(match_operand:DI 2 "general_operand" (match_operand:DI 2 "general_operand"
"M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q"))) "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDq,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
...@@ -7037,7 +7063,7 @@ ...@@ -7037,7 +7063,7 @@
ny\t%0,%2 ny\t%0,%2
risbg\t%0,%1,%t2,128+%f2,0" risbg\t%0,%1,%t2,128+%f2,0"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
(set_attr "cpu_facility" "*,*,z196,*,*,z10") (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*, (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")]) z10_super_E1,z10_super_E1,z10_super_E1")])
...@@ -7060,7 +7086,7 @@ ...@@ -7060,7 +7086,7 @@
ny\t%0,%2 ny\t%0,%2
risbg\t%0,%1,%t2,128+%f2,0" risbg\t%0,%1,%t2,128+%f2,0"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
(set_attr "cpu_facility" "*,*,z196,*,*,z10") (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*, (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")]) z10_super_E1,z10_super_E1,z10_super_E1")])
...@@ -7087,7 +7113,7 @@ ...@@ -7087,7 +7113,7 @@
# #
#" #"
[(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
(set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*") (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
(set_attr "z10prop" "*, (set_attr "z10prop" "*,
*, *,
z10_super_E1, z10_super_E1,
...@@ -7189,7 +7215,7 @@ ...@@ -7189,7 +7215,7 @@
niy\t%S0,%b2 niy\t%S0,%b2
#" #"
[(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
(set_attr "cpu_facility" "*,z196,*,*,*,*") (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
(define_insn "*andqi3_esa" (define_insn "*andqi3_esa"
...@@ -7283,10 +7309,10 @@ ...@@ -7283,10 +7309,10 @@
(define_insn "*iordi3_cc" (define_insn "*iordi3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
(match_operand:DI 2 "general_operand" " d,d,RT")) (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d, d") (set (match_operand:DI 0 "register_operand" "=d,d,d")
(ior:DI (match_dup 1) (match_dup 2)))] (ior:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
...@@ -7300,7 +7326,7 @@ ...@@ -7300,7 +7326,7 @@
(define_insn "*iordi3_cconly" (define_insn "*iordi3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
(match_operand:DI 2 "general_operand" " d,d,RT")) (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d,d"))] (clobber (match_scratch:DI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
...@@ -7314,11 +7340,11 @@ ...@@ -7314,11 +7340,11 @@
(define_insn "*iordi3" (define_insn "*iordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" [(set (match_operand:DI 0 "nonimmediate_operand"
"=d, d, d, d, d, d,d,d, d, AQ,Q") "=d, d, d, d, d, d,d,d,d, AQ,Q")
(ior:DI (match_operand:DI 1 "nonimmediate_operand" (ior:DI (match_operand:DI 1 "nonimmediate_operand"
" %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") " %0, 0, 0, 0, 0, 0,0,d,0, 0,0")
(match_operand:DI 2 "general_operand" (match_operand:DI 2 "general_operand"
"N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
...@@ -7376,7 +7402,7 @@ ...@@ -7376,7 +7402,7 @@
o\t%0,%2 o\t%0,%2
oy\t%0,%2" oy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "cpu_facility" "*,*,z196,*,*") (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_cconly" (define_insn "*iorsi3_cconly"
...@@ -7393,7 +7419,7 @@ ...@@ -7393,7 +7419,7 @@
o\t%0,%2 o\t%0,%2
oy\t%0,%2" oy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "cpu_facility" "*,*,z196,*,*") (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_zarch" (define_insn "*iorsi3_zarch"
...@@ -7413,7 +7439,7 @@ ...@@ -7413,7 +7439,7 @@
# #
#" #"
[(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
(set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
(set_attr "z10prop" "z10_super_E1, (set_attr "z10prop" "z10_super_E1,
z10_super_E1, z10_super_E1,
z10_super_E1, z10_super_E1,
...@@ -7509,7 +7535,7 @@ ...@@ -7509,7 +7535,7 @@
oiy\t%S0,%b2 oiy\t%S0,%b2
#" #"
[(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
(set_attr "cpu_facility" "*,z196,*,*,*,*") (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1, (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
z10_super,z10_super,*")]) z10_super,z10_super,*")])
...@@ -7619,10 +7645,10 @@ ...@@ -7619,10 +7645,10 @@
(define_insn "*xordi3_cc" (define_insn "*xordi3_cc"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
(match_operand:DI 2 "general_operand" " d,d,RT")) (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d, d") (set (match_operand:DI 0 "register_operand" "=d,d,d")
(xor:DI (match_dup 1) (match_dup 2)))] (xor:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
...@@ -7635,10 +7661,10 @@ ...@@ -7635,10 +7661,10 @@
(define_insn "*xordi3_cconly" (define_insn "*xordi3_cconly"
[(set (reg CC_REGNUM) [(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
(match_operand:DI 2 "general_operand" " d,d,RT")) (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:DI 0 "=d,d, d"))] (clobber (match_scratch:DI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@ "@
xgr\t%0,%2 xgr\t%0,%2
...@@ -7649,9 +7675,9 @@ ...@@ -7649,9 +7675,9 @@
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*xordi3" (define_insn "*xordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q")
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0")
(match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@ "@
...@@ -7696,7 +7722,7 @@ ...@@ -7696,7 +7722,7 @@
x\t%0,%2 x\t%0,%2
xy\t%0,%2" xy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "cpu_facility" "*,*,z196,*,*") (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*, (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1")]) z10_super_E1,z10_super_E1")])
...@@ -7714,7 +7740,7 @@ ...@@ -7714,7 +7740,7 @@
x\t%0,%2 x\t%0,%2
xy\t%0,%2" xy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
(set_attr "cpu_facility" "*,*,z196,*,*") (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*, (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1")]) z10_super_E1,z10_super_E1")])
...@@ -7733,7 +7759,7 @@ ...@@ -7733,7 +7759,7 @@
# #
#" #"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
(set_attr "cpu_facility" "*,*,z196,*,*,*,*") (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*, (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,*,*")]) z10_super_E1,z10_super_E1,*,*")])
...@@ -7795,7 +7821,7 @@ ...@@ -7795,7 +7821,7 @@
xiy\t%S0,%b2 xiy\t%S0,%b2
#" #"
[(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
(set_attr "cpu_facility" "*,*,z196,*,*,*") (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
...@@ -8778,8 +8804,8 @@ ...@@ -8778,8 +8804,8 @@
; clrt, clgrt, clfit, clgit, clt, clgt ; clrt, clgrt, clfit, clgit, clt, clgt
(define_insn "*cmp_and_trap_unsigned_int<mode>" (define_insn "*cmp_and_trap_unsigned_int<mode>"
[(trap_if (match_operator 0 "s390_unsigned_integer_comparison" [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
[(match_operand:GPR 1 "register_operand" "d,d, d") [(match_operand:GPR 1 "register_operand" "d,d,d")
(match_operand:GPR 2 "general_operand" "d,D,RT")]) (match_operand:GPR 2 "general_operand" "d,D,T")])
(const_int 0))] (const_int 0))]
"TARGET_Z10" "TARGET_Z10"
"@ "@
...@@ -8793,7 +8819,7 @@ ...@@ -8793,7 +8819,7 @@
; lat, lgat ; lat, lgat
(define_insn "*load_and_trap<mode>" (define_insn "*load_and_trap<mode>"
[(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T")
(const_int 0)) (const_int 0))
(const_int 0)) (const_int 0))
(set (match_operand:GPR 1 "register_operand" "=d") (set (match_operand:GPR 1 "register_operand" "=d")
...@@ -9092,7 +9118,7 @@ ...@@ -9092,7 +9118,7 @@
(if_then_else (if_then_else
(ne (match_operand:SI 1 "register_operand" "d") (ne (match_operand:SI 1 "register_operand" "d")
(const_int 1)) (const_int 1))
(match_operand 0 "address_operand" "ZQZR") (match_operand 0 "address_operand" "ZR")
(pc))) (pc)))
(set (match_operand:SI 2 "register_operand" "=1") (set (match_operand:SI 2 "register_operand" "=1")
(plus:SI (match_dup 1) (const_int -1))) (plus:SI (match_dup 1) (const_int -1)))
...@@ -9204,7 +9230,7 @@ ...@@ -9204,7 +9230,7 @@
; ;
(define_insn "indirect_jump" (define_insn "indirect_jump"
[(set (pc) (match_operand 0 "address_operand" "ZQZR"))] [(set (pc) (match_operand 0 "address_operand" "ZR"))]
"" ""
{ {
if (get_attr_op_type (insn) == OP_TYPE_RR) if (get_attr_op_type (insn) == OP_TYPE_RR)
...@@ -9223,7 +9249,7 @@ ...@@ -9223,7 +9249,7 @@
; ;
(define_insn "casesi_jump" (define_insn "casesi_jump"
[(set (pc) (match_operand 0 "address_operand" "ZQZR")) [(set (pc) (match_operand 0 "address_operand" "ZR"))
(use (label_ref (match_operand 1 "" "")))] (use (label_ref (match_operand 1 "" "")))]
"" ""
{ {
...@@ -9447,7 +9473,7 @@ ...@@ -9447,7 +9473,7 @@
(set_attr "z196prop" "z196_cracked")]) (set_attr "z196prop" "z196_cracked")])
(define_insn "*basr" (define_insn "*basr"
[(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
(match_operand 1 "const_int_operand" "n")) (match_operand 1 "const_int_operand" "n"))
(clobber (match_operand 2 "register_operand" "=r"))] (clobber (match_operand 2 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
...@@ -9508,7 +9534,7 @@ ...@@ -9508,7 +9534,7 @@
(define_insn "*basr_r" (define_insn "*basr_r"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
(call (mem:QI (match_operand 1 "address_operand" "ZQZR")) (call (mem:QI (match_operand 1 "address_operand" "ZR"))
(match_operand 2 "const_int_operand" "n"))) (match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))] (clobber (match_operand 3 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
...@@ -9549,7 +9575,7 @@ ...@@ -9549,7 +9575,7 @@
(define_insn "*tls_load_64" (define_insn "*tls_load_64"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(unspec:DI [(match_operand:DI 1 "memory_operand" "RT") (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
(match_operand:DI 2 "" "")] (match_operand:DI 2 "" "")]
UNSPEC_TLS_LOAD))] UNSPEC_TLS_LOAD))]
"TARGET_64BIT" "TARGET_64BIT"
...@@ -9568,6 +9594,7 @@ ...@@ -9568,6 +9594,7 @@
ly\t%0,%1%J2" ly\t%0,%1%J2"
[(set_attr "op_type" "RX,RXY") [(set_attr "op_type" "RX,RXY")
(set_attr "type" "load") (set_attr "type" "load")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
(define_insn "*bras_tls" (define_insn "*bras_tls"
...@@ -9600,7 +9627,7 @@ ...@@ -9600,7 +9627,7 @@
(define_insn "*basr_tls" (define_insn "*basr_tls"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
(call (mem:QI (match_operand 1 "address_operand" "ZQZR")) (call (mem:QI (match_operand 1 "address_operand" "ZR"))
(match_operand 2 "const_int_operand" "n"))) (match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r")) (clobber (match_operand 3 "register_operand" "=r"))
(use (match_operand 4 "" ""))] (use (match_operand 4 "" ""))]
...@@ -9704,11 +9731,12 @@ ...@@ -9704,11 +9731,12 @@
ld\t%0,%1 ld\t%0,%1
ldy\t%0,%1" ldy\t%0,%1"
[(set_attr "op_type" "RS,RSY,RS,RSY") [(set_attr "op_type" "RS,RSY,RS,RSY")
(set_attr "cpu_facility" "*,longdisp,*,longdisp")
(set_attr "type" "lm,lm,floaddf,floaddf")]) (set_attr "type" "lm,lm,floaddf,floaddf")])
(define_insn "atomic_loadti_1" (define_insn "atomic_loadti_1"
[(set (match_operand:TI 0 "register_operand" "=r") [(set (match_operand:TI 0 "register_operand" "=r")
(unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
UNSPEC_MOVA))] UNSPEC_MOVA))]
"TARGET_ZARCH" "TARGET_ZARCH"
"lpq\t%0,%1" "lpq\t%0,%1"
...@@ -9750,10 +9778,11 @@ ...@@ -9750,10 +9778,11 @@
std %1,%0 std %1,%0
stdy %1,%0" stdy %1,%0"
[(set_attr "op_type" "RS,RSY,RS,RSY") [(set_attr "op_type" "RS,RSY,RS,RSY")
(set_attr "cpu_facility" "*,longdisp,*,longdisp")
(set_attr "type" "stm,stm,fstoredf,fstoredf")]) (set_attr "type" "stm,stm,fstoredf,fstoredf")])
(define_insn "atomic_storeti_1" (define_insn "atomic_storeti_1"
[(set (match_operand:TI 0 "memory_operand" "=RT") [(set (match_operand:TI 0 "memory_operand" "=T")
(unspec:TI [(match_operand:TI 1 "register_operand" "r")] (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
UNSPEC_MOVA))] UNSPEC_MOVA))]
"TARGET_ZARCH" "TARGET_ZARCH"
...@@ -9834,7 +9863,7 @@ ...@@ -9834,7 +9863,7 @@
; cdsg, csg ; cdsg, csg
(define_insn "*atomic_compare_and_swap<mode>_1" (define_insn "*atomic_compare_and_swap<mode>_1"
[(set (match_operand:TDI 0 "register_operand" "=r") [(set (match_operand:TDI 0 "register_operand" "=r")
(match_operand:TDI 1 "memory_operand" "+QS")) (match_operand:TDI 1 "memory_operand" "+S"))
(set (match_dup 1) (set (match_dup 1)
(unspec_volatile:TDI (unspec_volatile:TDI
[(match_dup 1) [(match_dup 1)
...@@ -9865,6 +9894,7 @@ ...@@ -9865,6 +9894,7 @@
cds\t%0,%3,%S1 cds\t%0,%3,%S1
cdsy\t%0,%3,%S1" cdsy\t%0,%3,%S1"
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "sem")]) (set_attr "type" "sem")])
; cs, csy ; cs, csy
...@@ -9884,6 +9914,7 @@ ...@@ -9884,6 +9914,7 @@
cs\t%0,%3,%S1 cs\t%0,%3,%S1
csy\t%0,%3,%S1" csy\t%0,%3,%S1"
[(set_attr "op_type" "RS,RSY") [(set_attr "op_type" "RS,RSY")
(set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "sem")]) (set_attr "type" "sem")])
; ;
...@@ -9911,7 +9942,7 @@ ...@@ -9911,7 +9942,7 @@
; lan, lang, lao, laog, lax, laxg, laa, laag ; lan, lang, lao, laog, lax, laxg, laa, laag
(define_insn "atomic_fetch_<atomic><mode>_iaf" (define_insn "atomic_fetch_<atomic><mode>_iaf"
[(set (match_operand:GPR 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d")
(match_operand:GPR 1 "memory_operand" "+QS")) (match_operand:GPR 1 "memory_operand" "+S"))
(set (match_dup 1) (set (match_dup 1)
(unspec_volatile:GPR (unspec_volatile:GPR
[(ATOMIC_Z196:GPR (match_dup 1) [(ATOMIC_Z196:GPR (match_dup 1)
...@@ -10402,9 +10433,9 @@ ...@@ -10402,9 +10433,9 @@
; ;
(define_insn "prefetch" (define_insn "prefetch"
[(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") [(prefetch (match_operand 0 "address_operand" "ZT,X")
(match_operand:SI 1 "const_int_operand" " n,n") (match_operand:SI 1 "const_int_operand" " n,n")
(match_operand:SI 2 "const_int_operand" " n,n"))] (match_operand:SI 2 "const_int_operand" " n,n"))]
"TARGET_Z10" "TARGET_Z10"
{ {
switch (which_alternative) switch (which_alternative)
...@@ -10435,8 +10466,8 @@ ...@@ -10435,8 +10466,8 @@
; FIXME: There is also mvcin but we cannot use it since src and target ; FIXME: There is also mvcin but we cannot use it since src and target
; may overlap. ; may overlap.
(define_insn "bswap<mode>2" (define_insn "bswap<mode>2"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,RT") [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
(bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))] (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
"TARGET_CPU_ZARCH" "TARGET_CPU_ZARCH"
"@ "@
lrv<g>r\t%0,%1 lrv<g>r\t%0,%1
...@@ -10447,8 +10478,8 @@ ...@@ -10447,8 +10478,8 @@
(set_attr "z10prop" "z10_super")]) (set_attr "z10prop" "z10_super")])
(define_insn "bswaphi2" (define_insn "bswaphi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d, d,RT") [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T")
(bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))] (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
"TARGET_CPU_ZARCH" "TARGET_CPU_ZARCH"
"@ "@
# #
...@@ -10798,7 +10829,7 @@ ...@@ -10798,7 +10829,7 @@
; Non-transactional store ; Non-transactional store
(define_insn "ntstg" (define_insn "ntstg"
[(set (match_operand:DI 0 "memory_operand" "=RT") [(set (match_operand:DI 0 "memory_operand" "=T")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
UNSPECV_NTSTG))] UNSPECV_NTSTG))]
"TARGET_HTM" "TARGET_HTM"
...@@ -10844,7 +10875,7 @@ ...@@ -10844,7 +10875,7 @@
(define_insn "lcbb" (define_insn "lcbb"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand 1 "address_operand" "ZQZR") (unspec:SI [(match_operand 1 "address_operand" "ZR")
(match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_Z13" "TARGET_Z13"
......
gcc/config/s390/vector.md
...@@ -137,8 +137,8 @@ ...@@ -137,8 +137,8 @@
; Full HW vector size moves ; Full HW vector size moves
(define_insn "mov<mode>" (define_insn "mov<mode>"
[(set (match_operand:V_128 0 "nonimmediate_operand" "=v, v,QR, v, v, v, v, v,v,d") [(set (match_operand:V_128 0 "nonimmediate_operand" "=v,v,R, v, v, v, v, v,v,d")
(match_operand:V_128 1 "general_operand" " v,QR, v,j00,jm1,jyy,jxx,jKK,d,v"))] (match_operand:V_128 1 "general_operand" " v,R,v,j00,jm1,jyy,jxx,jKK,d,v"))]
"TARGET_VX" "TARGET_VX"
"@ "@
vlr\t%v0,%v1 vlr\t%v0,%v1
...@@ -178,8 +178,8 @@ ...@@ -178,8 +178,8 @@
; However, this would probably be slower. ; However, this would probably be slower.
(define_insn "mov<mode>" (define_insn "mov<mode>"
[(set (match_operand:V_8 0 "nonimmediate_operand" "=v,v,d, v,QR, v, v, v, v,d, Q, S, Q, S, d, d,d,d,d,R,T") [(set (match_operand:V_8 0 "nonimmediate_operand" "=v,v,d,v,R, v, v, v, v,d, Q, S, Q, S, d, d,d,d,d,R,T")
(match_operand:V_8 1 "general_operand" " v,d,v,QR, v,j00,jm1,jyy,jxx,d,j00,j00,jm1,jm1,j00,jm1,R,T,b,d,d"))] (match_operand:V_8 1 "general_operand" " v,d,v,R,v,j00,jm1,jyy,jxx,d,j00,j00,jm1,jm1,j00,jm1,R,T,b,d,d"))]
"" ""
"@ "@
vlr\t%v0,%v1 vlr\t%v0,%v1
...@@ -206,8 +206,8 @@ ...@@ -206,8 +206,8 @@
[(set_attr "op_type" "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SI,SIY,SI,SIY,RI,RI,RX,RXY,RIL,RX,RXY")]) [(set_attr "op_type" "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SI,SIY,SI,SIY,RI,RI,RX,RXY,RIL,RX,RXY")])
(define_insn "mov<mode>" (define_insn "mov<mode>"
[(set (match_operand:V_16 0 "nonimmediate_operand" "=v,v,d, v,QR, v, v, v, v,d, Q, Q, d, d,d,d,d,R,T,b") [(set (match_operand:V_16 0 "nonimmediate_operand" "=v,v,d,v,R, v, v, v, v,d, Q, Q, d, d,d,d,d,R,T,b")
(match_operand:V_16 1 "general_operand" " v,d,v,QR, v,j00,jm1,jyy,jxx,d,j00,jm1,j00,jm1,R,T,b,d,d,d"))] (match_operand:V_16 1 "general_operand" " v,d,v,R,v,j00,jm1,jyy,jxx,d,j00,jm1,j00,jm1,R,T,b,d,d,d"))]
"" ""
"@ "@
vlr\t%v0,%v1 vlr\t%v0,%v1
...@@ -233,8 +233,8 @@ ...@@ -233,8 +233,8 @@
[(set_attr "op_type" "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SIL,SIL,RI,RI,RX,RXY,RIL,RX,RXY,RIL")]) [(set_attr "op_type" "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SIL,SIL,RI,RI,RX,RXY,RIL,RX,RXY,RIL")])
(define_insn "mov<mode>" (define_insn "mov<mode>"
[(set (match_operand:V_32 0 "nonimmediate_operand" "=f,f,f,R,T,v,v,d, v,QR, f, v, v, v, v, Q, Q, d, d,d,d,d,d,R,T,b") [(set (match_operand:V_32 0 "nonimmediate_operand" "=f,f,f,R,T,v,v,d,v,R, f, v, v, v, v, Q, Q, d, d,d,d,d,d,R,T,b")
(match_operand:V_32 1 "general_operand" " f,R,T,f,f,v,d,v,QR, v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,b,d,R,T,d,d,d"))] (match_operand:V_32 1 "general_operand" " f,R,T,f,f,v,d,v,R,v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,b,d,R,T,d,d,d"))]
"TARGET_VX" "TARGET_VX"
"@ "@
lder\t%v0,%v1 lder\t%v0,%v1
...@@ -268,9 +268,9 @@ ...@@ -268,9 +268,9 @@
(define_insn "mov<mode>" (define_insn "mov<mode>"
[(set (match_operand:V_64 0 "nonimmediate_operand" [(set (match_operand:V_64 0 "nonimmediate_operand"
"=f,f,f,R,T,v,v,d, v,QR, f, v, v, v, v, Q, Q, d, d,f,d,d,d, d,RT,b") "=f,f,f,R,T,v,v,d,v,R, f, v, v, v, v, Q, Q, d, d,f,d,d,d,d,T,b")
(match_operand:V_64 1 "general_operand" (match_operand:V_64 1 "general_operand"
" f,R,T,f,f,v,d,v,QR, v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,d,f,b,d,RT, d,d"))] " f,R,T,f,f,v,d,v,R,v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,d,f,b,d,T,d,d"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
ldr\t%0,%1 ldr\t%0,%1
...@@ -322,10 +322,10 @@ ...@@ -322,10 +322,10 @@
; up with vl vlvgg vst. Shouldn't the middle-end be able to handle ; up with vl vlvgg vst. Shouldn't the middle-end be able to handle
; that itself? ; that itself?
(define_insn "*vec_set<mode>" (define_insn "*vec_set<mode>"
[(set (match_operand:V 0 "register_operand" "=v, v,v") [(set (match_operand:V 0 "register_operand" "=v,v,v")
(unspec:V [(match_operand:<non_vec> 1 "general_operand" "d,QR,K") (unspec:V [(match_operand:<non_vec> 1 "general_operand" "d,R,K")
(match_operand:SI 2 "nonmemory_operand" "an, I,I") (match_operand:SI 2 "nonmemory_operand" "an,I,I")
(match_operand:V 3 "register_operand" "0, 0,0")] (match_operand:V 3 "register_operand" "0,0,0")]
UNSPEC_VEC_SET))] UNSPEC_VEC_SET))]
"TARGET_VX "TARGET_VX
&& (!CONST_INT_P (operands[2]) && (!CONST_INT_P (operands[2])
...@@ -359,9 +359,9 @@ ...@@ -359,9 +359,9 @@
"TARGET_VX") "TARGET_VX")
(define_insn "*vec_extract<mode>" (define_insn "*vec_extract<mode>"
[(set (match_operand:<non_vec> 0 "nonimmediate_operand" "=d,QR") [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "=d,R")
(unspec:<non_vec> [(match_operand:V 1 "register_operand" "v, v") (unspec:<non_vec> [(match_operand:V 1 "register_operand" "v,v")
(match_operand:SI 2 "nonmemory_operand" "an, I")] (match_operand:SI 2 "nonmemory_operand" "an,I")]
UNSPEC_VEC_EXTRACT))] UNSPEC_VEC_EXTRACT))]
"TARGET_VX "TARGET_VX
&& (!CONST_INT_P (operands[2]) && (!CONST_INT_P (operands[2])
...@@ -404,7 +404,7 @@ ...@@ -404,7 +404,7 @@
(define_insn "*vec_splats<mode>" (define_insn "*vec_splats<mode>"
[(set (match_operand:V_HW 0 "register_operand" "=v,v,v,v") [(set (match_operand:V_HW 0 "register_operand" "=v,v,v,v")
(vec_duplicate:V_HW (match_operand:<non_vec> 1 "general_operand" "QR,K,v,d")))] (vec_duplicate:V_HW (match_operand:<non_vec> 1 "general_operand" " R,K,v,d")))]
"TARGET_VX" "TARGET_VX"
"@ "@
vlrep<bhfgq>\t%v0,%1 vlrep<bhfgq>\t%v0,%1
......
gcc/config/s390/vx-builtins.md
...@@ -70,7 +70,7 @@ ...@@ -70,7 +70,7 @@
[(set (match_operand:V_HW_32_64 0 "register_operand" "=v") [(set (match_operand:V_HW_32_64 0 "register_operand" "=v")
(unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0") (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0")
(match_operand:<tointvec> 2 "register_operand" "v") (match_operand:<tointvec> 2 "register_operand" "v")
(match_operand:BLK 3 "memory_operand" "QR") (match_operand:BLK 3 "memory_operand" "R")
(match_operand:QI 4 "const_mask_operand" "C")] (match_operand:QI 4 "const_mask_operand" "C")]
UNSPEC_VEC_GATHER))] UNSPEC_VEC_GATHER))]
"TARGET_VX && UINTVAL (operands[4]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)" "TARGET_VX && UINTVAL (operands[4]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
...@@ -170,7 +170,7 @@ ...@@ -170,7 +170,7 @@
(define_insn "vec_insert_and_zero<mode>" (define_insn "vec_insert_and_zero<mode>"
[(set (match_operand:V_HW 0 "register_operand" "=v") [(set (match_operand:V_HW 0 "register_operand" "=v")
(unspec:V_HW [(match_operand:<non_vec> 1 "memory_operand" "QR")] (unspec:V_HW [(match_operand:<non_vec> 1 "memory_operand" "R")]
UNSPEC_VEC_INSERT_AND_ZERO))] UNSPEC_VEC_INSERT_AND_ZERO))]
"TARGET_VX" "TARGET_VX"
"vllez<bhfgq>\t%v0,%1" "vllez<bhfgq>\t%v0,%1"
...@@ -178,7 +178,7 @@ ...@@ -178,7 +178,7 @@
(define_insn "vlbb" (define_insn "vlbb"
[(set (match_operand:V16QI 0 "register_operand" "=v") [(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:BLK 1 "memory_operand" "QR") (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "R")
(match_operand:QI 2 "const_mask_operand" "C")] (match_operand:QI 2 "const_mask_operand" "C")]
UNSPEC_VEC_LOAD_BNDRY))] UNSPEC_VEC_LOAD_BNDRY))]
"TARGET_VX && UINTVAL (operands[2]) < 7" "TARGET_VX && UINTVAL (operands[2]) < 7"
......
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