i386.c: Commit forgotten hunk in previous patch.

	* i386.c: Commit forgotten hunk in previous patch.
	(regclass_map): Add extended registers.
	(dbx_register_map): Add missing frame register.

From-SVN: r40413

gcc/ChangeLog

+Mon Mar 12 16:27:56 CET 2001  Jan Hubicka  <jh@suse.cz>
+
+	* i386.c: Commit forgotten hunk in previous patch.
+	(regclass_map): Add extended registers.
+	(dbx_register_map): Add missing frame register.
+
 Mon Mar 12 15:41:08 CET 2001  Jan Hubicka  <jh@suse.cz>
 
 	* i386.md (all XFmode patterns except swapxf): Disable for 64bit.

gcc/config/i386/i386.c

@@ -339,18 +339,24 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
   SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
   SSE_REGS, SSE_REGS,
   MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
-  MMX_REGS, MMX_REGS
+  MMX_REGS, MMX_REGS,
+  NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
+  NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
+  SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
+  SSE_REGS, SSE_REGS,
 };
 
-/* The "default" register map.  */
+/* The "default" register map used in 32bit mode.  */
 
 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
 {
   0, 2, 1, 3, 6, 7, 4, 5,		/* general regs */
   12, 13, 14, 15, 16, 17, 18, 19,	/* fp regs */
-  -1, -1, -1, -1,			/* arg, flags, fpsr, dir */
+  -1, -1, -1, -1, -1,			/* arg, flags, fpsr, dir, frame */
   21, 22, 23, 24, 25, 26, 27, 28,	/* SSE */
   29, 30, 31, 32, 33, 34, 35, 36,       /* MMX */
+  -1, -1, -1, -1, -1, -1, -1, -1,	/* extended integer registers */
+  -1, -1, -1, -1, -1, -1, -1, -1,	/* extended SSE registers */
 };
 
 /* The "default" register map used in 64bit mode.  */

gcc/config/i386/i386.md

@@ -4021,7 +4021,7 @@
   [(set_attr "type" "fmov,multi")
    (set_attr "mode" "DF")])
 
-(define_insn "*truncxfdf2_2"
+(define_insn "*trunctfdf2_2"
   [(set (match_operand:DF 0 "memory_operand" "=m")
 	(float_truncate:DF
 	  (match_operand:TF 1 "register_operand" "f")))]
@@ -7955,18 +7955,19 @@
 ;; than 31.
 
 (define_expand "ashldi3"
-  [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
-		   (ashift:DI (match_operand:DI 1 "register_operand" "0")
-			      (match_operand:QI 2 "nonmemory_operand" "Jc")))
+  [(parallel [(set (match_operand:DI 0 "register_operand" "")
+		   (ashift:DI (match_operand:DI 1 "register_operand" "")
+			      (match_operand:QI 2 "nonmemory_operand" "")))
 	      (clobber (reg:CC 17))])]
   ""
   "
 {
-  if (TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
+  if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
     {
       emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
       DONE;
     }
+  ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;
 }")
 
 (define_insn "ashldi3_1"
@@ -8096,12 +8097,7 @@
       return \"add{l}\\t{%0, %0|%0, %0}\";
 
     case TYPE_LEA:
-      if (GET_CODE (operands[2]) != CONST_INT
-	  || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
-	abort ();
-      operands[1] = gen_rtx_MULT (SImode, operands[1],
-				  GEN_INT (1 << INTVAL (operands[2])));
-      return \"lea{l}\\t{%a1, %0|%0, %a1}\";
+      return \"#\";
 
     default:
       if (REG_P (operands[2]))
@@ -8694,7 +8690,7 @@
   "sar{w}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])
 
@@ -8727,7 +8723,7 @@
   "sar{w}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])
 
@@ -8766,7 +8762,7 @@
   "sar{b}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])
 
@@ -8799,7 +8795,7 @@
   "sar{b}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])
 
@@ -8967,7 +8963,7 @@
   "shr{w}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])
 
@@ -9039,7 +9035,7 @@
   "shr{b}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])
 
@@ -9147,7 +9143,7 @@
   "rol{w}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])
 
@@ -9181,7 +9177,7 @@
   "rol{b}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])
 
@@ -9249,7 +9245,7 @@
   "ror{w}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])
 
@@ -9283,7 +9279,7 @@
   "ror{b}\\t%0"
   [(set_attr "type" "ishift")
    (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+     (if_then_else (match_operand 0 "register_operand" "") 
 	(const_string "2")
 	(const_string "*")))])