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riscv-gcc-1
Commit 3cb999d8 by David Edelsohn Committed by David Edelsohn
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aix43.h (ASM_CPU_SPEC, [...]): Add rs64a and PPC630. 

	* aix43.h (ASM_CPU_SPEC, CPP_CPU_SPEC): Add rs64a and PPC630.
	* rs6000.c (processor_target_table): Add powerpc64, rs64a, and PPC630.
	(rs6000_cpu): Choose between 32-bit and 64-bit default processors.
	(secndary_reload_class): Make TARGET_ELF conditional compile.
	(print_operand_address): Similar.
	(output_toc): Print all values as hex.
	(get_issue_rate): Rearrange and add RS64A and PPC630.
	* rs6000.h (processor_type): Add RS64A and PPC630.
	(PROCESSOR_POWERPC): Change to PROCESSOR_750.
	(PROCESSOR_POWERPC64): New.
	(PROMOTE_MODE): Use word_mode.
	(RTX_COSTS): Add RS64A and PPC630.
	* rs6000.md (scheduling information): Add lmul and ldiv
	representing 64-bit integer multiply and divide.  Add rs64a and
	PPC630 information.
	(ashldi3): Add support for "rldic" instruction.
	* sysv4.h (PROCESSOR_DEFAULT): Change to PROCESSOR_750.

From-SVN: r28300
parent d3ec6b06
Showing with 277 additions and 86 deletions
gcc/ChangeLog
Tue Jul 27 16:05:52 1999 David Edelsohn <edelsohn@gnu.org>
* aix43.h (ASM_CPU_SPEC, CPP_CPU_SPEC): Add rs64a and PPC630.
* rs6000.c (processor_target_table): Add powerpc64, rs64a, and PPC630.
(rs6000_cpu): Choose between 32-bit and 64-bit default processors.
(secndary_reload_class): Make TARGET_ELF conditional compile.
(print_operand_address): Similar.
(output_toc): Print all values as hex.
(get_issue_rate): Rearrange and add RS64A and PPC630.
* rs6000.h (processor_type): Add RS64A and PPC630.
(PROCESSOR_POWERPC64): New.
(PROMOTE_MODE): Use word_mode.
(RTX_COSTS): Add RS64A and PPC630.
* rs6000.md (scheduling information): Add lmul and ldiv
representing 64-bit integer multiply and divide. Add rs64a and
PPC630 information.
(ashldi3): Add support for "rldic" instruction.
* sysv4.h (PROCESSOR_DEFAULT): Change to PROCESSOR_750.
Tue Jul 27 15:31:53 1999 Vladimir Makarov <vmakarov@toad.to.cygnus.com> Tue Jul 27 15:31:53 1999 Vladimir Makarov <vmakarov@toad.to.cygnus.com>
* config/sparc/sparc.c (sparc_override_options): Enable SPARCLITE * config/sparc/sparc.c (sparc_override_options): Enable SPARCLITE
......
gcc/config/rs6000/aix43.h
...@@ -81,6 +81,7 @@ do { \ ...@@ -81,6 +81,7 @@ do { \
%{mcpu=rios2: -mpwr2} \ %{mcpu=rios2: -mpwr2} \
%{mcpu=rsc: -mpwr} \ %{mcpu=rsc: -mpwr} \
%{mcpu=rsc1: -mpwr} \ %{mcpu=rsc1: -mpwr} \
%{mcpu=rs64a: -mppc} \
%{mcpu=403: -mppc} \ %{mcpu=403: -mppc} \
%{mcpu=505: -mppc} \ %{mcpu=505: -mppc} \
%{mcpu=601: -m601} \ %{mcpu=601: -m601} \
...@@ -90,6 +91,7 @@ do { \ ...@@ -90,6 +91,7 @@ do { \
%{mcpu=604: -m604} \ %{mcpu=604: -m604} \
%{mcpu=604e: -m604} \ %{mcpu=604e: -m604} \
%{mcpu=620: -mppc} \ %{mcpu=620: -mppc} \
%{mcpu=630: -mppc} \
%{mcpu=821: -mppc} \ %{mcpu=821: -mppc} \
%{mcpu=860: -mppc}" %{mcpu=860: -mppc}"
...@@ -125,6 +127,7 @@ do { \ ...@@ -125,6 +127,7 @@ do { \
%{mcpu=rios2: -D_ARCH_PWR2} \ %{mcpu=rios2: -D_ARCH_PWR2} \
%{mcpu=rsc: -D_ARCH_PWR} \ %{mcpu=rsc: -D_ARCH_PWR} \
%{mcpu=rsc1: -D_ARCH_PWR} \ %{mcpu=rsc1: -D_ARCH_PWR} \
%{mcpu=rs64a: -D_ARCH_PPC} \
%{mcpu=403: -D_ARCH_PPC} \ %{mcpu=403: -D_ARCH_PPC} \
%{mcpu=505: -D_ARCH_PPC} \ %{mcpu=505: -D_ARCH_PPC} \
%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \ %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
...@@ -133,6 +136,7 @@ do { \ ...@@ -133,6 +136,7 @@ do { \
%{mcpu=603e: -D_ARCH_PPC} \ %{mcpu=603e: -D_ARCH_PPC} \
%{mcpu=604: -D_ARCH_PPC} \ %{mcpu=604: -D_ARCH_PPC} \
%{mcpu=620: -D_ARCH_PPC} \ %{mcpu=620: -D_ARCH_PPC} \
%{mcpu=630: -D_ARCH_PPC} \
%{mcpu=821: -D_ARCH_PPC} \ %{mcpu=821: -D_ARCH_PPC} \
%{mcpu=860: -D_ARCH_PPC}" %{mcpu=860: -D_ARCH_PPC}"
......
gcc/config/rs6000/rs6000.c
...@@ -186,6 +186,9 @@ rs6000_override_options (default_cpu) ...@@ -186,6 +186,9 @@ rs6000_override_options (default_cpu)
{"powerpc", PROCESSOR_POWERPC, {"powerpc", PROCESSOR_POWERPC,
MASK_POWERPC | MASK_NEW_MNEMONICS, MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"powerpc64", PROCESSOR_POWERPC64,
MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS},
{"rios", PROCESSOR_RIOS1, {"rios", PROCESSOR_RIOS1,
MASK_POWER | MASK_MULTIPLE | MASK_STRING, MASK_POWER | MASK_MULTIPLE | MASK_STRING,
MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
...@@ -201,6 +204,9 @@ rs6000_override_options (default_cpu) ...@@ -201,6 +204,9 @@ rs6000_override_options (default_cpu)
{"rios2", PROCESSOR_RIOS2, {"rios2", PROCESSOR_RIOS2,
MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
POWERPC_MASKS | MASK_NEW_MNEMONICS}, POWERPC_MASKS | MASK_NEW_MNEMONICS},
{"rs64a", PROCESSOR_RS64A,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS},
{"401", PROCESSOR_PPC403, {"401", PROCESSOR_PPC403,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
...@@ -234,6 +240,9 @@ rs6000_override_options (default_cpu) ...@@ -234,6 +240,9 @@ rs6000_override_options (default_cpu)
{"620", PROCESSOR_PPC620, {"620", PROCESSOR_PPC620,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT}, POWER_MASKS | MASK_PPC_GPOPT},
{"630", PROCESSOR_PPC630,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT},
{"740", PROCESSOR_PPC750, {"740", PROCESSOR_PPC750,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
...@@ -262,7 +271,7 @@ rs6000_override_options (default_cpu) ...@@ -262,7 +271,7 @@ rs6000_override_options (default_cpu)
/* Identify the processor type */ /* Identify the processor type */
rs6000_select[0].string = default_cpu; rs6000_select[0].string = default_cpu;
rs6000_cpu = PROCESSOR_DEFAULT; rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++) for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++)
{ {
...@@ -1072,7 +1081,7 @@ reg_or_mem_operand (op, mode) ...@@ -1072,7 +1081,7 @@ reg_or_mem_operand (op, mode)
} }
/* Return 1 if the operand is a general register or memory operand without /* Return 1 if the operand is a general register or memory operand without
pre-inc or pre_dec which produces invalid form of PowerPC lwa pre_inc or pre_dec which produces invalid form of PowerPC lwa
instruction. */ instruction. */
int int
...@@ -2355,15 +2364,16 @@ secondary_reload_class (class, mode, in) ...@@ -2355,15 +2364,16 @@ secondary_reload_class (class, mode, in)
{ {
int regno; int regno;
#if TARGET_ELF
/* We can not copy a symbolic operand directly into anything other than /* We can not copy a symbolic operand directly into anything other than
BASE_REGS for TARGET_ELF. So indicate that a register from BASE_REGS BASE_REGS for TARGET_ELF. So indicate that a register from BASE_REGS
is needed as an intermediate register. */ is needed as an intermediate register. */
if (TARGET_ELF if (class != BASE_REGS
&& class != BASE_REGS
&& (GET_CODE (in) == SYMBOL_REF && (GET_CODE (in) == SYMBOL_REF
|| GET_CODE (in) == LABEL_REF || GET_CODE (in) == LABEL_REF
|| GET_CODE (in) == CONST)) || GET_CODE (in) == CONST))
return BASE_REGS; return BASE_REGS;
#endif
if (GET_CODE (in) == REG) if (GET_CODE (in) == REG)
{ {
...@@ -2469,10 +2479,11 @@ rs6000_got_register (value) ...@@ -2469,10 +2479,11 @@ rs6000_got_register (value)
/* The second flow pass currently (June 1999) can't update regs_ever_live /* The second flow pass currently (June 1999) can't update regs_ever_live
without disturbing other parts of the compiler, so update it here to without disturbing other parts of the compiler, so update it here to
make the prolog/epilogue code happy. */ make the prolog/epilogue code happy. */
if (no_new_pseudos && !regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
current_function_uses_pic_offset_table = 1; current_function_uses_pic_offset_table = 1;
return pic_offset_table_rtx; return pic_offset_table_rtx;
} }
...@@ -3211,12 +3222,14 @@ print_operand_address (file, x) ...@@ -3211,12 +3222,14 @@ print_operand_address (file, x)
} }
else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM #if TARGET_ELF
&& GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1))) else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
&& CONSTANT_P (XEXP (x, 1)))
{ {
output_addr_const (file, XEXP (x, 1)); output_addr_const (file, XEXP (x, 1));
fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
} }
#endif
else else
abort (); abort ();
} }
...@@ -4882,10 +4895,10 @@ output_toc (file, x, labelno) ...@@ -4882,10 +4895,10 @@ output_toc (file, x, labelno)
else else
{ {
if (TARGET_MINIMAL_TOC) if (TARGET_MINIMAL_TOC)
fprintf (file, "\t.long %ld\n\t.long %ld\n", fprintf (file, "\t.long 0x%lx\n\t.long 0x%lx\n",
(long)high, (long)low); (long)high, (long)low);
else else
fprintf (file, "\t.tc ID_%lx_%lx[TC],%ld,%ld\n", fprintf (file, "\t.tc ID_%lx_%lx[TC],0x%lx,0x%lx\n",
(long)high, (long)low, (long)high, (long)low); (long)high, (long)low, (long)high, (long)low);
return; return;
} }
...@@ -5259,7 +5272,8 @@ rs6000_adjust_priority (insn, priority) ...@@ -5259,7 +5272,8 @@ rs6000_adjust_priority (insn, priority)
case TYPE_IMUL: case TYPE_IMUL:
case TYPE_IDIV: case TYPE_IDIV:
fprintf (stderr, "priority was %#x (%d) before adjustment\n", priority, priority); fprintf (stderr, "priority was %#x (%d) before adjustment\n",
priority, priority);
if (priority >= 0 && priority < 0x01000000) if (priority >= 0 && priority < 0x01000000)
priority >>= 3; priority >>= 3;
break; break;
...@@ -5274,21 +5288,18 @@ rs6000_adjust_priority (insn, priority) ...@@ -5274,21 +5288,18 @@ rs6000_adjust_priority (insn, priority)
int get_issue_rate() int get_issue_rate()
{ {
switch (rs6000_cpu_attr) { switch (rs6000_cpu_attr) {
case CPU_RIOS1: case CPU_RIOS1: /* ? */
return 3; /* ? */ case CPU_RS64A:
case CPU_RIOS2: case CPU_PPC601: /* ? */
return 4; return 3;
case CPU_PPC601:
return 3; /* ? */
case CPU_PPC603: case CPU_PPC603:
return 2;
case CPU_PPC750: case CPU_PPC750:
return 2; return 2;
case CPU_RIOS2:
case CPU_PPC604: case CPU_PPC604:
return 4;
case CPU_PPC604E: case CPU_PPC604E:
return 4;
case CPU_PPC620: case CPU_PPC620:
case CPU_PPC630:
return 4; return 4;
default: default:
return 1; return 1;
...@@ -5518,9 +5529,9 @@ rs6000_valid_type_attribute_p (type, attributes, identifier, args) ...@@ -5518,9 +5529,9 @@ rs6000_valid_type_attribute_p (type, attributes, identifier, args)
if (is_attribute_p ("dllexport", identifier)) if (is_attribute_p ("dllexport", identifier))
return (args == NULL_TREE); return (args == NULL_TREE);
/* Exception attribute allows the user to specify 1-2 strings or identifiers /* Exception attribute allows the user to specify 1-2 strings
that will fill in the 3rd and 4th fields of the structured exception or identifiers that will fill in the 3rd and 4th fields
table. */ of the structured exception table. */
if (is_attribute_p ("exception", identifier)) if (is_attribute_p ("exception", identifier))
{ {
int i; int i;
...@@ -5565,6 +5576,7 @@ void ...@@ -5565,6 +5576,7 @@ void
rs6000_set_default_type_attributes (type) rs6000_set_default_type_attributes (type)
tree type ATTRIBUTE_UNUSED; tree type ATTRIBUTE_UNUSED;
{ {
return;
} }
/* Return a dll import reference corresponding to a call's SYMBOL_REF */ /* Return a dll import reference corresponding to a call's SYMBOL_REF */
...@@ -5590,13 +5602,15 @@ rs6000_dll_import_ref (call_ref) ...@@ -5590,13 +5602,15 @@ rs6000_dll_import_ref (call_ref)
strcat (p, call_name); strcat (p, call_name);
node = get_identifier (p); node = get_identifier (p);
reg1 = force_reg (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node))); reg1 = force_reg (Pmode, gen_rtx_SYMBOL_REF (VOIDmode,
IDENTIFIER_POINTER (node)));
emit_move_insn (reg2, gen_rtx_MEM (Pmode, reg1)); emit_move_insn (reg2, gen_rtx_MEM (Pmode, reg1));
return reg2; return reg2;
} }
/* Return a reference suitable for calling a function with the longcall attribute. */ /* Return a reference suitable for calling a function with the
longcall attribute. */
struct rtx_def * struct rtx_def *
rs6000_longcall_ref (call_ref) rs6000_longcall_ref (call_ref)
rtx call_ref; rtx call_ref;
...@@ -5666,25 +5680,27 @@ rs6000_select_section (decl, reloc) ...@@ -5666,25 +5680,27 @@ rs6000_select_section (decl, reloc)
else if (TREE_CODE (decl) == VAR_DECL) else if (TREE_CODE (decl) == VAR_DECL)
{ {
if ((flag_pic && reloc) if ((flag_pic && reloc)
|| !TREE_READONLY (decl) || ! TREE_READONLY (decl)
|| TREE_SIDE_EFFECTS (decl) || TREE_SIDE_EFFECTS (decl)
|| !DECL_INITIAL (decl) || ! DECL_INITIAL (decl)
|| (DECL_INITIAL (decl) != error_mark_node || (DECL_INITIAL (decl) != error_mark_node
&& !TREE_CONSTANT (DECL_INITIAL (decl)))) && ! TREE_CONSTANT (DECL_INITIAL (decl))))
{ {
if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value)) if (rs6000_sdata != SDATA_NONE && (size > 0)
&& (size <= g_switch_value))
sdata_section (); sdata_section ();
else else
data_section (); data_section ();
} }
else else
{ {
if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value)) if (rs6000_sdata != SDATA_NONE && (size > 0)
&& (size <= g_switch_value))
{ {
if (rs6000_sdata == SDATA_EABI) if (rs6000_sdata == SDATA_EABI)
sdata2_section (); sdata2_section ();
else else
sdata_section (); /* System V doesn't have .sdata2/.sbss2 */ sdata_section (); /* System V doesn't have .sdata2/.sbss2 */
} }
else else
const_section (); const_section ();
...@@ -5695,7 +5711,6 @@ rs6000_select_section (decl, reloc) ...@@ -5695,7 +5711,6 @@ rs6000_select_section (decl, reloc)
} }
/* If we are referencing a function that is static or is known to be /* If we are referencing a function that is static or is known to be
in this file, make the SYMBOL_REF special. We can use this to indicate in this file, make the SYMBOL_REF special. We can use this to indicate
that we can branch to this function without emitting a no-op after the that we can branch to this function without emitting a no-op after the
...@@ -5746,12 +5761,18 @@ rs6000_encode_section_info (decl) ...@@ -5746,12 +5761,18 @@ rs6000_encode_section_info (decl)
if ((size > 0 && size <= g_switch_value) if ((size > 0 && size <= g_switch_value)
|| (name || (name
&& ((len == sizeof (".sdata")-1 && strcmp (name, ".sdata") == 0) && ((len == sizeof (".sdata")-1
|| (len == sizeof (".sdata2")-1 && strcmp (name, ".sdata2") == 0) && strcmp (name, ".sdata") == 0)
|| (len == sizeof (".sbss")-1 && strcmp (name, ".sbss") == 0) || (len == sizeof (".sdata2")-1
|| (len == sizeof (".sbss2")-1 && strcmp (name, ".sbss2") == 0) && strcmp (name, ".sdata2") == 0)
|| (len == sizeof (".PPC.EMB.sdata0")-1 && strcmp (name, ".PPC.EMB.sdata0") == 0) || (len == sizeof (".sbss")-1
|| (len == sizeof (".PPC.EMB.sbss0")-1 && strcmp (name, ".PPC.EMB.sbss0") == 0)))) && strcmp (name, ".sbss") == 0)
|| (len == sizeof (".sbss2")-1
&& strcmp (name, ".sbss2") == 0)
|| (len == sizeof (".PPC.EMB.sdata0")-1
&& strcmp (name, ".PPC.EMB.sdata0") == 0)
|| (len == sizeof (".PPC.EMB.sbss0")-1
&& strcmp (name, ".PPC.EMB.sbss0") == 0))))
{ {
rtx sym_ref = XEXP (DECL_RTL (decl), 0); rtx sym_ref = XEXP (DECL_RTL (decl), 0);
char *str = permalloc (2 + strlen (XSTR (sym_ref, 0))); char *str = permalloc (2 + strlen (XSTR (sym_ref, 0)));
......
gcc/config/rs6000/rs6000.h
...@@ -400,6 +400,7 @@ enum processor_type ...@@ -400,6 +400,7 @@ enum processor_type
{ {
PROCESSOR_RIOS1, PROCESSOR_RIOS1,
PROCESSOR_RIOS2, PROCESSOR_RIOS2,
PROCESSOR_RS64A,
PROCESSOR_MPCCORE, PROCESSOR_MPCCORE,
PROCESSOR_PPC403, PROCESSOR_PPC403,
PROCESSOR_PPC601, PROCESSOR_PPC601,
...@@ -407,6 +408,7 @@ enum processor_type ...@@ -407,6 +408,7 @@ enum processor_type
PROCESSOR_PPC604, PROCESSOR_PPC604,
PROCESSOR_PPC604e, PROCESSOR_PPC604e,
PROCESSOR_PPC620, PROCESSOR_PPC620,
PROCESSOR_PPC630,
PROCESSOR_PPC750 PROCESSOR_PPC750
}; };
...@@ -416,12 +418,14 @@ extern enum processor_type rs6000_cpu; ...@@ -416,12 +418,14 @@ extern enum processor_type rs6000_cpu;
#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
/* Define generic processor types based upon current deployment. */ /* Define generic processor types based upon current deployment. */
#define PROCESSOR_COMMON PROCESSOR_PPC601 #define PROCESSOR_COMMON PROCESSOR_PPC601
#define PROCESSOR_POWER PROCESSOR_RIOS1 #define PROCESSOR_POWER PROCESSOR_RIOS1
#define PROCESSOR_POWERPC PROCESSOR_PPC604 #define PROCESSOR_POWERPC PROCESSOR_PPC604
#define PROCESSOR_POWERPC64 PROCESSOR_RS64A
/* Define the default processor. This is overridden by other tm.h files. */ /* Define the default processor. This is overridden by other tm.h files. */
#define PROCESSOR_DEFAULT PROCESSOR_RIOS1 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
/* Specify the dialect of assembler to use. New mnemonics is dialect one /* Specify the dialect of assembler to use. New mnemonics is dialect one
and the old mnemonics are dialect zero. */ and the old mnemonics are dialect zero. */
...@@ -511,7 +515,7 @@ extern int rs6000_debug_arg; /* debug argument handling */ ...@@ -511,7 +515,7 @@ extern int rs6000_debug_arg; /* debug argument handling */
#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \ if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
(MODE) = (! TARGET_POWERPC64 ? SImode : DImode); (MODE) = word_mode;
/* Define this if function arguments should also be promoted using the above /* Define this if function arguments should also be promoted using the above
procedure. */ procedure. */
...@@ -1926,7 +1930,7 @@ typedef struct rs6000_args ...@@ -1926,7 +1930,7 @@ typedef struct rs6000_args
#define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \ #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
(TARGET_ELF \ (TARGET_ELF \
&& !flag_pic && !TARGET_TOC \ && ! flag_pic && ! TARGET_TOC \
&& (MODE) != DImode \ && (MODE) != DImode \
&& (MODE) != TImode \ && (MODE) != TImode \
&& (TARGET_HARD_FLOAT || (MODE) != DFmode) \ && (TARGET_HARD_FLOAT || (MODE) != DFmode) \
...@@ -2307,6 +2311,12 @@ do { \ ...@@ -2307,6 +2311,12 @@ do { \
? COSTS_N_INSNS (5) \ ? COSTS_N_INSNS (5) \
: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \ ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
case PROCESSOR_RS64A: \
return (GET_CODE (XEXP (X, 1)) != CONST_INT \
? GET_MODE (XEXP (X, 1)) != DImode \
? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
? COSTS_N_INSNS (12) : COSTS_N_INSNS (14)); \
case PROCESSOR_RIOS2: \ case PROCESSOR_RIOS2: \
case PROCESSOR_MPCCORE: \ case PROCESSOR_MPCCORE: \
case PROCESSOR_PPC604e: \ case PROCESSOR_PPC604e: \
...@@ -2321,8 +2331,14 @@ do { \ ...@@ -2321,8 +2331,14 @@ do { \
? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \ ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
case PROCESSOR_PPC403: \ case PROCESSOR_PPC403: \
case PROCESSOR_PPC604: \ case PROCESSOR_PPC604: \
case PROCESSOR_PPC620: \
return COSTS_N_INSNS (4); \ return COSTS_N_INSNS (4); \
case PROCESSOR_PPC620: \
case PROCESSOR_PPC630: \
return (GET_CODE (XEXP (X, 1)) != CONST_INT \
? GET_MODE (XEXP (X, 1)) != DImode \
? COSTS_N_INSNS (4) : COSTS_N_INSNS (7) \
: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
} \ } \
case DIV: \ case DIV: \
case MOD: \ case MOD: \
...@@ -2338,6 +2354,10 @@ do { \ ...@@ -2338,6 +2354,10 @@ do { \
return COSTS_N_INSNS (19); \ return COSTS_N_INSNS (19); \
case PROCESSOR_RIOS2: \ case PROCESSOR_RIOS2: \
return COSTS_N_INSNS (13); \ return COSTS_N_INSNS (13); \
case PROCESSOR_RS64A: \
return (GET_MODE (XEXP (X, 1)) != DImode \
? COSTS_N_INSNS (65) \
: COSTS_N_INSNS (67)); \
case PROCESSOR_MPCCORE: \ case PROCESSOR_MPCCORE: \
return COSTS_N_INSNS (6); \ return COSTS_N_INSNS (6); \
case PROCESSOR_PPC403: \ case PROCESSOR_PPC403: \
...@@ -2348,8 +2368,12 @@ do { \ ...@@ -2348,8 +2368,12 @@ do { \
return COSTS_N_INSNS (37); \ return COSTS_N_INSNS (37); \
case PROCESSOR_PPC604: \ case PROCESSOR_PPC604: \
case PROCESSOR_PPC604e: \ case PROCESSOR_PPC604e: \
case PROCESSOR_PPC620: \
return COSTS_N_INSNS (20); \ return COSTS_N_INSNS (20); \
case PROCESSOR_PPC620: \
case PROCESSOR_PPC630: \
return (GET_MODE (XEXP (X, 1)) != DImode \
? COSTS_N_INSNS (21) \
: COSTS_N_INSNS (37)); \
case PROCESSOR_PPC750: \ case PROCESSOR_PPC750: \
return COSTS_N_INSNS (19); \ return COSTS_N_INSNS (19); \
} \ } \
......
gcc/config/rs6000/rs6000.md
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
;; Define an insn type attribute. This is used in function unit delay ;; Define an insn type attribute. This is used in function unit delay
;; computations. ;; computations.
(define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
(const_string "integer")) (const_string "integer"))
;; Length (in bytes). ;; Length (in bytes).
...@@ -40,7 +40,7 @@ ...@@ -40,7 +40,7 @@
;; Processor type -- this attribute must exactly match the processor_type ;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h. ;; enumeration in rs6000.h.
(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750" (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"
(const (symbol_ref "rs6000_cpu_attr"))) (const (symbol_ref "rs6000_cpu_attr")))
; (define_function_unit NAME MULTIPLICITY SIMULTANEITY ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
...@@ -50,12 +50,12 @@ ...@@ -50,12 +50,12 @@
; (POWER and 601 use Integer Unit) ; (POWER and 601 use Integer Unit)
(define_function_unit "lsu" 1 0 (define_function_unit "lsu" 1 0
(and (eq_attr "type" "load") (and (eq_attr "type" "load")
(eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750")) (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
2 1) 2 1)
(define_function_unit "lsu" 1 0 (define_function_unit "lsu" 1 0
(and (eq_attr "type" "store,fpstore") (and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750")) (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
1 1) 1 1)
(define_function_unit "lsu" 1 0 (define_function_unit "lsu" 1 0
...@@ -65,7 +65,7 @@ ...@@ -65,7 +65,7 @@
(define_function_unit "lsu" 1 0 (define_function_unit "lsu" 1 0
(and (eq_attr "type" "fpload") (and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc604,ppc604e,ppc620")) (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
3 1) 3 1)
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
...@@ -103,10 +103,10 @@ ...@@ -103,10 +103,10 @@
(eq_attr "cpu" "rios2")) (eq_attr "cpu" "rios2"))
1 1) 1 1)
; Integer Unit (RIOS1, PPC601, PPC603) ; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
(and (eq_attr "type" "integer") (and (eq_attr "type" "integer")
(eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603")) (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603"))
1 1) 1 1)
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
...@@ -120,12 +120,32 @@ ...@@ -120,12 +120,32 @@
5 5) 5 5)
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "rs64a"))
20 14)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "lmul")
(eq_attr "cpu" "rs64a"))
34 34)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv") (and (eq_attr "type" "idiv")
(eq_attr "cpu" "rios1")) (eq_attr "cpu" "rios1"))
19 19) 19 19)
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv") (and (eq_attr "type" "idiv")
(eq_attr "cpu" "rs64a"))
66 66)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "ldiv")
(eq_attr "cpu" "rs64a"))
66 66)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc403")) (eq_attr "cpu" "ppc403"))
33 33) 33 33)
...@@ -186,24 +206,49 @@ ...@@ -186,24 +206,49 @@
; from/to spr). ; from/to spr).
(define_function_unit "iu2" 2 0 (define_function_unit "iu2" 2 0
(and (eq_attr "type" "integer") (and (eq_attr "type" "integer")
(eq_attr "cpu" "ppc604,ppc604e,ppc620")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
1 1) 1 1)
(define_function_unit "imuldiv" 1 0 (define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul") (and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc604,ppc620")) (eq_attr "cpu" "ppc604"))
4 2) 4 2)
(define_function_unit "imuldiv" 1 0 (define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul") (and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc620,ppc630"))
5 3)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "lmul")
(eq_attr "cpu" "ppc620,ppc630"))
5 3)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc604e")) (eq_attr "cpu" "ppc604e"))
2 1) 2 1)
(define_function_unit "imuldiv" 1 0 (define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv") (and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc604,ppc604e,ppc620")) (eq_attr "cpu" "ppc604,ppc604e"))
20 19) 20 19)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc620"))
37 36)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc630"))
21 20)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "ldiv")
(eq_attr "cpu" "ppc620,ppc630"))
37 36)
; PPC750 has two integer units: a primary one which can perform all ; PPC750 has two integer units: a primary one which can perform all
; operations and a secondary one which is fed in lock step with the first ; operations and a secondary one which is fed in lock step with the first
; and can perform "simple" integer operations. ; and can perform "simple" integer operations.
...@@ -243,7 +288,7 @@ ...@@ -243,7 +288,7 @@
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
(and (eq_attr "type" "compare,delayed_compare") (and (eq_attr "type" "compare,delayed_compare")
(eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
3 1) 3 1)
(define_function_unit "iu2" 2 0 (define_function_unit "iu2" 2 0
...@@ -253,7 +298,7 @@ ...@@ -253,7 +298,7 @@
(define_function_unit "iu2" 2 0 (define_function_unit "iu2" 2 0
(and (eq_attr "type" "compare,delayed_compare") (and (eq_attr "type" "compare,delayed_compare")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc750")) (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750"))
1 1) 1 1)
; fp compare uses fp unit ; fp compare uses fp unit
...@@ -265,7 +310,7 @@ ...@@ -265,7 +310,7 @@
; rios1 and rios2 have different fpcompare delays ; rios1 and rios2 have different fpcompare delays
(define_function_unit "fpu2" 2 0 (define_function_unit "fpu2" 2 0
(and (eq_attr "type" "fpcompare") (and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "rios2")) (eq_attr "cpu" "rios2,ppc630"))
5 1) 5 1)
; on ppc601 and ppc603, fpcompare takes also 2 cycles from ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
...@@ -280,7 +325,7 @@ ...@@ -280,7 +325,7 @@
; fp compare uses fp unit ; fp compare uses fp unit
(define_function_unit "fpu" 1 0 (define_function_unit "fpu" 1 0
(and (eq_attr "type" "fpcompare") (and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
5 1) 5 1)
(define_function_unit "fpu" 1 0 (define_function_unit "fpu" 1 0
...@@ -290,12 +335,12 @@ ...@@ -290,12 +335,12 @@
(define_function_unit "bpu" 1 0 (define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtjmpr") (and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "rios1,rios2")) (eq_attr "cpu" "rios1,rios2,rs64a"))
5 1) 5 1)
(define_function_unit "bpu" 1 0 (define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtjmpr") (and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
4 1) 4 1)
; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
...@@ -315,8 +360,8 @@ ...@@ -315,8 +360,8 @@
(define_function_unit "fpu" 1 0 (define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp") (and (eq_attr "type" "fp")
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "rs64a,mpccore"))
4 4) 4 2)
(define_function_unit "fpu" 1 0 (define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp") (and (eq_attr "type" "fp")
...@@ -325,11 +370,16 @@ ...@@ -325,11 +370,16 @@
(define_function_unit "fpu" 1 0 (define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp") (and (eq_attr "type" "fp")
(eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750")) (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620"))
3 1) 3 1)
(define_function_unit "fpu" 1 0 (define_function_unit "fpu" 1 0
(and (eq_attr "type" "dmul") (and (eq_attr "type" "dmul")
(eq_attr "cpu" "rs64a"))
7 2)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "mpccore")) (eq_attr "cpu" "mpccore"))
5 5) 5 5)
...@@ -356,6 +406,11 @@ ...@@ -356,6 +406,11 @@
(define_function_unit "fpu" 1 0 (define_function_unit "fpu" 1 0
(and (eq_attr "type" "sdiv") (and (eq_attr "type" "sdiv")
(eq_attr "cpu" "rs64a"))
31 31)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc601")) (eq_attr "cpu" "ppc601"))
17 17) 17 17)
...@@ -376,7 +431,7 @@ ...@@ -376,7 +431,7 @@
(define_function_unit "fpu" 1 0 (define_function_unit "fpu" 1 0
(and (eq_attr "type" "ddiv") (and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620,ppc750")) (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620"))
31 31) 31 31)
(define_function_unit "fpu" 1 0 (define_function_unit "fpu" 1 0
...@@ -401,20 +456,50 @@ ...@@ -401,20 +456,50 @@
2 1) 2 1)
(define_function_unit "fpu2" 2 0 (define_function_unit "fpu2" 2 0
(and (eq_attr "type" "fp")
(eq_attr "cpu" "ppc630"))
3 1)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "dmul") (and (eq_attr "type" "dmul")
(eq_attr "cpu" "rios2")) (eq_attr "cpu" "rios2"))
2 1) 2 1)
(define_function_unit "fpu2" 2 0 (define_function_unit "fpu2" 2 0
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc630"))
3 1)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "sdiv,ddiv") (and (eq_attr "type" "sdiv,ddiv")
(eq_attr "cpu" "rios2")) (eq_attr "cpu" "rios2"))
17 17) 17 17)
(define_function_unit "fpu2" 2 0 (define_function_unit "fpu2" 2 0
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc630"))
17 17)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc630"))
21 21)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "ssqrt,dsqrt") (and (eq_attr "type" "ssqrt,dsqrt")
(eq_attr "cpu" "rios2")) (eq_attr "cpu" "rios2"))
26 26) 26 26)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "ppc630"))
18 18)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "ppc630"))
26 26)
;; Start with fixed-point load and store insns. Here we put only the more ;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later. ;; complex forms. Basic data transfer is done later.
...@@ -5037,7 +5122,7 @@ ...@@ -5037,7 +5122,7 @@
(match_operand:DI 2 "gpc_reg_operand" "r")))] (match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"mulld %0,%1,%2" "mulld %0,%1,%2"
[(set_attr "type" "imul")]) [(set_attr "type" "lmul")])
(define_insn "smuldi3_highpart" (define_insn "smuldi3_highpart"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
...@@ -5049,7 +5134,7 @@ ...@@ -5049,7 +5134,7 @@
(const_int 64))))] (const_int 64))))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"mulhd %0,%1,%2" "mulhd %0,%1,%2"
[(set_attr "type" "imul")]) [(set_attr "type" "lmul")])
(define_insn "umuldi3_highpart" (define_insn "umuldi3_highpart"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
...@@ -5061,7 +5146,7 @@ ...@@ -5061,7 +5146,7 @@
(const_int 64))))] (const_int 64))))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"mulhdu %0,%1,%2" "mulhdu %0,%1,%2"
[(set_attr "type" "imul")]) [(set_attr "type" "lmul")])
(define_expand "divdi3" (define_expand "divdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "") [(set (match_operand:DI 0 "gpc_reg_operand" "")
...@@ -5137,7 +5222,7 @@ ...@@ -5137,7 +5222,7 @@
(match_operand:DI 2 "gpc_reg_operand" "r")))] (match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"divd %0,%1,%2" "divd %0,%1,%2"
[(set_attr "type" "idiv")]) [(set_attr "type" "ldiv")])
(define_insn "udivdi3" (define_insn "udivdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
...@@ -5145,7 +5230,7 @@ ...@@ -5145,7 +5230,7 @@
(match_operand:DI 2 "gpc_reg_operand" "r")))] (match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"divdu %0,%1,%2" "divdu %0,%1,%2"
[(set_attr "type" "idiv")]) [(set_attr "type" "ldiv")])
(define_insn "rotldi3" (define_insn "rotldi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
...@@ -5357,6 +5442,42 @@ ...@@ -5357,6 +5442,42 @@
"sld%I2. %0,%1,%H2" "sld%I2. %0,%1,%H2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:DI 3 "mask64_operand" "S")))]
"((GET_CODE (operands[3]) == CONST_INT
? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
"rldic %0,%1,%H2,%S3")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:DI 3 "mask64_operand" "S"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=r"))]
"((GET_CODE (operands[3]) == CONST_INT
? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
"rldic. %0,%1,%H2,%S3"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:DI 3 "mask64_operand" "S"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"((GET_CODE (operands[3]) == CONST_INT
? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
"rldic. %0,%1,%H2,%S3"
[(set_attr "type" "delayed_compare")])
(define_expand "lshrdi3" (define_expand "lshrdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "") [(set (match_operand:DI 0 "gpc_reg_operand" "")
(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
...@@ -6433,12 +6554,12 @@ ...@@ -6433,12 +6554,12 @@
else else
return \"mr %0,%1\;mr %L0,%L1\"; return \"mr %0,%1\;mr %L0,%L1\";
case 1: case 1:
/* If the low-address word is used in the address, we must load it /* If the low-address word is used in the address, we must load
last. Otherwise, load it first. Note that we cannot have it last. Otherwise, load it first. Note that we cannot have
auto-increment in that case since the address register is known to be auto-increment in that case since the address register is
dead. */ known to be dead. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
operands [1], 0)) operands[1], 0))
return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
else else
return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
...@@ -6588,7 +6709,7 @@ ...@@ -6588,7 +6709,7 @@
auto-increment in that case since the address register is known to be auto-increment in that case since the address register is known to be
dead. */ dead. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
operands [1], 0)) operands[1], 0))
return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
else else
return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
...@@ -6962,7 +7083,7 @@ ...@@ -6962,7 +7083,7 @@
auto-increment in that case since the address register is known to be auto-increment in that case since the address register is known to be
dead. */ dead. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
operands [1], 0)) operands[1], 0))
return \"ld %L0,%L1\;ld %0,%1\"; return \"ld %L0,%L1\;ld %0,%1\";
else else
return \"ld%U1 %0,%1\;ld %L0,%L1\"; return \"ld%U1 %0,%1\;ld %L0,%L1\";
...@@ -10234,10 +10355,11 @@ ...@@ -10234,10 +10355,11 @@
}") }")
(define_expand "ctrsi" (define_expand "ctrsi"
[(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "") [(parallel [(set (pc)
(const_int 1)) (if_then_else (ne (match_operand:SI 0 "register_operand" "")
(label_ref (match_operand 1 "" "")) (const_int 1))
(pc))) (label_ref (match_operand 1 "" ""))
(pc)))
(set (match_dup 0) (set (match_dup 0)
(plus:SI (match_dup 0) (plus:SI (match_dup 0)
(const_int -1))) (const_int -1)))
...@@ -10247,10 +10369,11 @@ ...@@ -10247,10 +10369,11 @@
"") "")
(define_expand "ctrdi" (define_expand "ctrdi"
[(parallel [(set (pc) (if_then_else (ne (match_operand:DI 0 "register_operand" "") [(parallel [(set (pc)
(const_int 1)) (if_then_else (ne (match_operand:DI 0 "register_operand" "")
(label_ref (match_operand 1 "" "")) (const_int 1))
(pc))) (label_ref (match_operand 1 "" ""))
(pc)))
(set (match_dup 0) (set (match_dup 0)
(plus:DI (match_dup 0) (plus:DI (match_dup 0)
(const_int -1))) (const_int -1)))
......
gcc/config/rs6000/sysv4.h
...@@ -276,7 +276,7 @@ do { \ ...@@ -276,7 +276,7 @@ do { \
#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS) #define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS)
#undef PROCESSOR_DEFAULT #undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC601 #define PROCESSOR_DEFAULT PROCESSOR_PPC750
/* System V.4 uses register 13 as a pointer to the small data area, /* System V.4 uses register 13 as a pointer to the small data area,
so it is not available to the normal user. */ so it is not available to the normal user. */
......
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