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riscv-gcc-1
Commit 3cac0a21 by Philippe De Muyter Committed by Jeff Law
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m68k.md (ashldi_const): Allow shift count in range ]32,63]. 

        * m68k/m68k.md (ashldi_const): Allow shift count in range ]32,63].
        (ashldi3): Allow constant shift count in range ]32,63].
        (ashrdi_const, ashrid3, lshrdi_const, lshrdi3): Likewise.

From-SVN: r18784
parent 4da05956
Showing with 55 additions and 22 deletions
gcc/ChangeLog
Mon Mar 23 23:26:42 1998 Philippe De Muyter <phdm@macqel.be>
* m68k/m68k.md (ashldi_const): Allow shift count in range ]32,63].
(ashldi3): Allow constant shift count in range ]32,63].
(ashrdi_const, ashrid3, lshrdi_const, lshrdi3): Likewise.
1998-03-22 Mark Mitchell <mmitchell@usa.net> 1998-03-22 Mark Mitchell <mmitchell@usa.net>
* tree.h (IS_EXPR_CODE_CLASS): New macro. * tree.h (IS_EXPR_CODE_CLASS): New macro.
......
gcc/config/m68k/m68k.md
...@@ -4458,9 +4458,9 @@ ...@@ -4458,9 +4458,9 @@
[(set (match_operand:DI 0 "general_operand" "=d") [(set (match_operand:DI 0 "general_operand" "=d")
(ashift:DI (match_operand:DI 1 "general_operand" "0") (ashift:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))] (match_operand 2 "const_int_operand" "n")))]
"(INTVAL (operands[2]) == 1 "((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)" || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
"* "*
{ {
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
...@@ -4470,10 +4470,19 @@ ...@@ -4470,10 +4470,19 @@
return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\"; return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
else if (INTVAL (operands[2]) == 16) else if (INTVAL (operands[2]) == 16)
return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\"; return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
else if (INTVAL (operands[2]) == 48)
return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
else if (INTVAL (operands[2]) == 2) else if (INTVAL (operands[2]) == 2)
return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\"; return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
else/* if (INTVAL (operands[2]) == 3)*/ else if (INTVAL (operands[2]) == 3)
return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\"; return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
else /* 32 < INTVAL (operands[2]) <= 63 */
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 32);
output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
\"moveq %2,%0\;asl%.l %0,%1\", operands);
return \"mov%.l %1,%0\;moveq %#0,%1\";
}
} ") } ")
(define_expand "ashldi3" (define_expand "ashldi3"
...@@ -4484,9 +4493,9 @@ ...@@ -4484,9 +4493,9 @@
" "
{ {
if (GET_CODE (operands[2]) != CONST_INT if (GET_CODE (operands[2]) != CONST_INT
|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3)) && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
FAIL; FAIL;
} ") } ")
...@@ -4650,10 +4659,10 @@ ...@@ -4650,10 +4659,10 @@
(ashiftrt:DI (match_operand:DI 1 "general_operand" "0") (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))] (match_operand 2 "const_int_operand" "n")))]
"!TARGET_5200 "!TARGET_5200
&& ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 31 || INTVAL (operands[2]) == 31
|| INTVAL (operands[2]) == 63))" || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
"* "*
{ {
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
...@@ -4666,12 +4675,23 @@ ...@@ -4666,12 +4675,23 @@
return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\"; return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
else if (INTVAL (operands[2]) == 16) else if (INTVAL (operands[2]) == 16)
return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\"; return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
else if (INTVAL (operands[2]) == 48)
return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
else if (INTVAL (operands[2]) == 31) else if (INTVAL (operands[2]) == 31)
return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\"; return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
else if (INTVAL (operands[2]) == 2) else if (INTVAL (operands[2]) == 2)
return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\"; return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
else/* if (INTVAL (operands[2]) == 3)*/ else if (INTVAL (operands[2]) == 3)
return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\"; return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
else /* 32 < INTVAL (operands[2]) <= 63 */
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 32);
output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
\"moveq %2,%1\;asr%.l %1,%0\", operands);
output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
}
} ") } ")
(define_expand "ashrdi3" (define_expand "ashrdi3"
...@@ -4682,10 +4702,9 @@ ...@@ -4682,10 +4702,9 @@
" "
{ {
if (GET_CODE (operands[2]) != CONST_INT if (GET_CODE (operands[2]) != CONST_INT
|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
&& INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 31 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
&& INTVAL (operands[2]) != 32 && INTVAL (operands[2]) != 63))
FAIL; FAIL;
} ") } ")
...@@ -4811,9 +4830,9 @@ ...@@ -4811,9 +4830,9 @@
(lshiftrt:DI (match_operand:DI 1 "general_operand" "0") (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))] (match_operand 2 "const_int_operand" "n")))]
"!TARGET_5200 "!TARGET_5200
&& ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))" || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
"* "*
{ {
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
...@@ -4826,10 +4845,19 @@ ...@@ -4826,10 +4845,19 @@
return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\"; return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
else if (INTVAL (operands[2]) == 16) else if (INTVAL (operands[2]) == 16)
return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\"; return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
else if (INTVAL (operands[2]) == 48)
return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
else if (INTVAL (operands[2]) == 2) else if (INTVAL (operands[2]) == 2)
return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\"; return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
else /*if (INTVAL (operands[2]) == 3)*/ else if (INTVAL (operands[2]) == 3)
return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\"; return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
else /* 32 < INTVAL (operands[2]) <= 63 */
{
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 32);
output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
\"moveq %2,%1\;lsr%.l %1,%0\", operands);
return \"mov%.l %0,%1\;moveq %#0,%0\";
}
} ") } ")
(define_expand "lshrdi3" (define_expand "lshrdi3"
...@@ -4840,10 +4868,9 @@ ...@@ -4840,10 +4868,9 @@
" "
{ {
if (GET_CODE (operands[2]) != CONST_INT if (GET_CODE (operands[2]) != CONST_INT
|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
&& INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
&& INTVAL (operands[2]) != 63))
FAIL; FAIL;
} ") } ")
......
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