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Commit 3bc8b61e by David S. Miller Committed by David S. Miller
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sparc.c (ultra_code_from_mask, [...]): New functions to describe UltraSPARC… 

sparc.c (ultra_code_from_mask, [...]): New functions to describe UltraSPARC pipeline exactly to Haifa.

	* config/sparc/sparc.c (ultra_code_from_mask,
	ultra_cmove_results_ready_p, ultra_fpmode_conflict_exists,
	ultra_find_type, ultra_schedule_insn, ultra_flush_pipeline,
	ultrasparc_sched_init, ultrasparc_variable_issue,
	ultra_rescan_pipeline_state, ultrasparc_sched_reorder): New
	functions to describe UltraSPARC pipeline exactly to Haifa.
	(ultrasparc_adjust_cost): Indicate IMUL type insns have zero cost,
	as there is nothing the scheduler can do about it.  Indicate that
	REG_DEP_OUTPUT's collide.  Fixup formatting.
	* config/sparc/sparc.h (RTX_COSTS): Fixup integer multiply and
	divide costs on Ultra for DImode.
	(MD_SCHED_INIT, MD_SCHED_REORDER, MD_SCHED_VARIABLE_ISSUE):
	Define.
	* config/sparc/sparc.md (ieu_unnamed function unit): Rename to
	ieuN and add call_no_delay_slot to type list.
	(cti function unit): New unit for branches on UltraSPARC.
	(subx/addx insns): Set type to misc.
	(sidi zero/sign extension insns on arch64): Set type to shift.
	(sign_extendhidi2_insn): Set type to sload.

From-SVN: r21767
parent a6c2a102
Showing with 107 additions and 36 deletions
gcc/ChangeLog
Sun Aug 16 17:37:06 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
* config/sparc/sparc.c (ultra_code_from_mask,
ultra_cmove_results_ready_p, ultra_fpmode_conflict_exists,
ultra_find_type, ultra_schedule_insn, ultra_flush_pipeline,
ultrasparc_sched_init, ultrasparc_variable_issue,
ultra_rescan_pipeline_state, ultrasparc_sched_reorder): New
functions to describe UltraSPARC pipeline exactly to Haifa.
(ultrasparc_adjust_cost): Indicate IMUL type insns have zero cost,
as there is nothing the scheduler can do about it. Indicate that
REG_DEP_OUTPUT's collide. Fixup formatting.
* config/sparc/sparc.h (RTX_COSTS): Fixup integer multiply and
divide costs on Ultra for DImode.
(MD_SCHED_INIT, MD_SCHED_REORDER, MD_SCHED_VARIABLE_ISSUE):
Define.
* config/sparc/sparc.md (ieu_unnamed function unit): Rename to
ieuN and add call_no_delay_slot to type list.
(cti function unit): New unit for branches on UltraSPARC.
(subx/addx insns): Set type to misc.
(sidi zero/sign extension insns on arch64): Set type to shift.
(sign_extendhidi2_insn): Set type to sload.
Sun Aug 16 13:52:00 1998 David Edelsohn <edelsohn@mhpcc.edu> Sun Aug 16 13:52:00 1998 David Edelsohn <edelsohn@mhpcc.edu>
* rs6000.c (rs6000_stack_info): Use if == 0 for sizes. * rs6000.c (rs6000_stack_info): Use if == 0 for sizes.
......
gcc/config/sparc/sparc.h
...@@ -2704,11 +2704,17 @@ extern struct rtx_def *legitimize_pic_address (); ...@@ -2704,11 +2704,17 @@ extern struct rtx_def *legitimize_pic_address ();
#define RTX_COSTS(X,CODE,OUTER_CODE) \ #define RTX_COSTS(X,CODE,OUTER_CODE) \
case MULT: \ case MULT: \
if (sparc_cpu == PROCESSOR_ULTRASPARC) \
return (GET_MODE (X) == DImode ? \
COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
case DIV: \ case DIV: \
case UDIV: \ case UDIV: \
case MOD: \ case MOD: \
case UMOD: \ case UMOD: \
if (sparc_cpu == PROCESSOR_ULTRASPARC) \
return (GET_MODE (X) == DImode ? \
COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
return COSTS_N_INSNS (25); \ return COSTS_N_INSNS (25); \
/* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
so that cse will favor the latter. */ \ so that cse will favor the latter. */ \
...@@ -2723,9 +2729,28 @@ extern struct rtx_def *legitimize_pic_address (); ...@@ -2723,9 +2729,28 @@ extern struct rtx_def *legitimize_pic_address ();
if (sparc_cpu == PROCESSOR_SUPERSPARC) \ if (sparc_cpu == PROCESSOR_SUPERSPARC) \
(COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST); \ (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST); \
else if (sparc_cpu == PROCESSOR_ULTRASPARC) \ else if (sparc_cpu == PROCESSOR_ULTRASPARC) \
(COST) = ultrasparc_adjust_cost (INSN, LINK, DEP, COST); \ (COST) = ultrasparc_adjust_cost (INSN, LINK, DEP, \
last_scheduled_insn, COST);\
else else
extern void ultrasparc_sched_reorder ();
extern void ultrasparc_sched_init ();
extern int ultrasparc_variable_issue ();
#define MD_SCHED_INIT(DUMP, SCHED_VERBOSE) \
if (sparc_cpu == PROCESSOR_ULTRASPARC) \
ultrasparc_sched_init (DUMP, SCHED_VERBOSE)
#define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY) \
if (sparc_cpu == PROCESSOR_ULTRASPARC) \
ultrasparc_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY)
#define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
if (sparc_cpu == PROCESSOR_ULTRASPARC) \
(CAN_ISSUE_MORE) = ultrasparc_variable_issue (INSN); \
else \
(CAN_ISSUE_MORE)--
/* Conditional branches with empty delay slots have a length of two. */ /* Conditional branches with empty delay slots have a length of two. */
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \ #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
if (GET_CODE (INSN) == CALL_INSN \ if (GET_CODE (INSN) == CALL_INSN \
......
gcc/config/sparc/sparc.md
...@@ -398,9 +398,9 @@ ...@@ -398,9 +398,9 @@
(eq_attr "type" "store,fpstore")) (eq_attr "type" "store,fpstore"))
1 1) 1 1)
(define_function_unit "ieu_unnamed" 2 0 (define_function_unit "ieuN" 2 0
(and (eq_attr "cpu" "ultrasparc") (and (eq_attr "cpu" "ultrasparc")
(eq_attr "type" "ialu,binary,move,unary,shift,cmove,compare,call")) (eq_attr "type" "ialu,binary,move,unary,shift,compare,call,call_no_delay_slot,uncond_branch"))
1 1) 1 1)
(define_function_unit "ieu0" 1 0 (define_function_unit "ieu0" 1 0
...@@ -415,7 +415,12 @@ ...@@ -415,7 +415,12 @@
(define_function_unit "ieu1" 1 0 (define_function_unit "ieu1" 1 0
(and (eq_attr "cpu" "ultrasparc") (and (eq_attr "cpu" "ultrasparc")
(eq_attr "type" "compare,call,uncond_branch")) (eq_attr "type" "compare,call,call_no_delay_slot,uncond_branch"))
1 1)
(define_function_unit "cti" 1 0
(and (eq_attr "cpu" "ultrasparc")
(eq_attr "type" "branch"))
1 1) 1 1)
;; Timings; throughput/latency ;; Timings; throughput/latency
...@@ -1416,7 +1421,7 @@ ...@@ -1416,7 +1421,7 @@
(match_operand:SI 1 "arith_operand" "rI")))] (match_operand:SI 1 "arith_operand" "rI")))]
"! TARGET_LIVE_G0" "! TARGET_LIVE_G0"
"subx\\t%%g0, %1, %0" "subx\\t%%g0, %1, %0"
[(set_attr "type" "unary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*neg_sltu_plus_x" (define_insn "*neg_sltu_plus_x"
...@@ -1425,7 +1430,7 @@ ...@@ -1425,7 +1430,7 @@
(match_operand:SI 1 "arith_operand" "rI"))))] (match_operand:SI 1 "arith_operand" "rI"))))]
"! TARGET_LIVE_G0" "! TARGET_LIVE_G0"
"subx\\t%%g0, %1, %0" "subx\\t%%g0, %1, %0"
[(set_attr "type" "unary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*sgeu_insn" (define_insn "*sgeu_insn"
...@@ -1454,7 +1459,7 @@ ...@@ -1454,7 +1459,7 @@
(match_operand:SI 1 "arith_operand" "rI")))] (match_operand:SI 1 "arith_operand" "rI")))]
"! TARGET_LIVE_G0" "! TARGET_LIVE_G0"
"addx\\t%%g0, %1, %0" "addx\\t%%g0, %1, %0"
[(set_attr "type" "unary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*sltu_plus_x_plus_y" (define_insn "*sltu_plus_x_plus_y"
...@@ -1464,7 +1469,7 @@ ...@@ -1464,7 +1469,7 @@
(match_operand:SI 2 "arith_operand" "rI"))))] (match_operand:SI 2 "arith_operand" "rI"))))]
"" ""
"addx\\t%1, %2, %0" "addx\\t%1, %2, %0"
[(set_attr "type" "binary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*x_minus_sltu" (define_insn "*x_minus_sltu"
...@@ -1473,7 +1478,7 @@ ...@@ -1473,7 +1478,7 @@
(ltu:SI (reg:CC 100) (const_int 0))))] (ltu:SI (reg:CC 100) (const_int 0))))]
"" ""
"subx\\t%1, 0, %0" "subx\\t%1, 0, %0"
[(set_attr "type" "unary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
;; ??? Combine should canonicalize these next two to the same pattern. ;; ??? Combine should canonicalize these next two to the same pattern.
...@@ -1484,7 +1489,7 @@ ...@@ -1484,7 +1489,7 @@
(ltu:SI (reg:CC 100) (const_int 0))))] (ltu:SI (reg:CC 100) (const_int 0))))]
"" ""
"subx\\t%r1, %2, %0" "subx\\t%r1, %2, %0"
[(set_attr "type" "binary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*x_minus_sltu_plus_y" (define_insn "*x_minus_sltu_plus_y"
...@@ -1494,7 +1499,7 @@ ...@@ -1494,7 +1499,7 @@
(match_operand:SI 2 "arith_operand" "rI"))))] (match_operand:SI 2 "arith_operand" "rI"))))]
"" ""
"subx\\t%r1, %2, %0" "subx\\t%r1, %2, %0"
[(set_attr "type" "binary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*sgeu_plus_x" (define_insn "*sgeu_plus_x"
...@@ -1503,7 +1508,7 @@ ...@@ -1503,7 +1508,7 @@
(match_operand:SI 1 "register_operand" "r")))] (match_operand:SI 1 "register_operand" "r")))]
"" ""
"subx\\t%1, -1, %0" "subx\\t%1, -1, %0"
[(set_attr "type" "unary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*x_minus_sgeu" (define_insn "*x_minus_sgeu"
...@@ -1512,7 +1517,7 @@ ...@@ -1512,7 +1517,7 @@
(geu:SI (reg:CC 100) (const_int 0))))] (geu:SI (reg:CC 100) (const_int 0))))]
"" ""
"addx\\t%1, -1, %0" "addx\\t%1, -1, %0"
[(set_attr "type" "unary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_split (define_split
...@@ -2167,7 +2172,8 @@ ...@@ -2167,7 +2172,8 @@
(unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))] (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
"flag_pic" "flag_pic"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "movsi_high_pic" (define_insn "movsi_high_pic"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -2212,7 +2218,8 @@ ...@@ -2212,7 +2218,8 @@
(match_operand:SI 3 "" "")] 5)))] (match_operand:SI 3 "" "")] 5)))]
"flag_pic" "flag_pic"
"or\\t%1, %%lo(%a3-(%a2-.)), %0" "or\\t%1, %%lo(%a3-(%a2-.)), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_expand "movdi" (define_expand "movdi"
[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "") [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
...@@ -2394,7 +2401,8 @@ ...@@ -2394,7 +2401,8 @@
(unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))] (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))]
"TARGET_ARCH64 && flag_pic" "TARGET_ARCH64 && flag_pic"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "*pic_sethi_di" (define_insn "*pic_sethi_di"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2426,7 +2434,8 @@ ...@@ -2426,7 +2434,8 @@
(match_operand:DI 2 "symbolic_operand" "")))] (match_operand:DI 2 "symbolic_operand" "")))]
"TARGET_CM_MEDLOW" "TARGET_CM_MEDLOW"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "seth44" (define_insn "seth44"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2451,7 +2460,8 @@ ...@@ -2451,7 +2460,8 @@
(match_operand:DI 2 "symbolic_operand" "")))] (match_operand:DI 2 "symbolic_operand" "")))]
"TARGET_CM_MEDMID" "TARGET_CM_MEDMID"
"or\\t%1, %%l44(%a2), %0" "or\\t%1, %%l44(%a2), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "sethh" (define_insn "sethh"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2475,7 +2485,8 @@ ...@@ -2475,7 +2485,8 @@
(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))] (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))]
"TARGET_CM_MEDANY" "TARGET_CM_MEDANY"
"or\\t%1, %%hm(%a2), %0" "or\\t%1, %%hm(%a2), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "setlo" (define_insn "setlo"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2483,7 +2494,8 @@ ...@@ -2483,7 +2494,8 @@
(match_operand:DI 2 "symbolic_operand" "")))] (match_operand:DI 2 "symbolic_operand" "")))]
"TARGET_CM_MEDANY" "TARGET_CM_MEDANY"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "embmedany_sethi" (define_insn "embmedany_sethi"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2499,7 +2511,8 @@ ...@@ -2499,7 +2511,8 @@
(match_operand:DI 2 "data_segment_operand" "")))] (match_operand:DI 2 "data_segment_operand" "")))]
"TARGET_CM_EMBMEDANY" "TARGET_CM_EMBMEDANY"
"add\\t%1, %%lo(%a2), %0" "add\\t%1, %%lo(%a2), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "embmedany_brsum" (define_insn "embmedany_brsum"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2530,7 +2543,8 @@ ...@@ -2530,7 +2543,8 @@
(unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))] (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))]
"TARGET_CM_EMBMEDANY" "TARGET_CM_EMBMEDANY"
"or\\t%1, %%ulo(%a2), %0" "or\\t%1, %%ulo(%a2), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "embmedany_textlo" (define_insn "embmedany_textlo"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
...@@ -2538,7 +2552,8 @@ ...@@ -2538,7 +2552,8 @@
(match_operand:DI 2 "text_segment_operand" "")))] (match_operand:DI 2 "text_segment_operand" "")))]
"TARGET_CM_EMBMEDANY" "TARGET_CM_EMBMEDANY"
"or\\t%1, %%lo(%a2), %0" "or\\t%1, %%lo(%a2), %0"
[(set_attr "length" "1")]) [(set_attr "type" "ialu")
(set_attr "length" "1")])
;; Now some patterns to help reload out a bit. ;; Now some patterns to help reload out a bit.
(define_expand "reload_indi" (define_expand "reload_indi"
...@@ -3797,7 +3812,7 @@ ...@@ -3797,7 +3812,7 @@
"@ "@
srl\\t%1, 0, %0 srl\\t%1, 0, %0
lduw\\t%1, %0" lduw\\t%1, %0"
[(set_attr "type" "unary,load") [(set_attr "type" "shift,load")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*zero_extendsidi2_insn_sp32" (define_insn "*zero_extendsidi2_insn_sp32"
...@@ -4090,7 +4105,7 @@ ...@@ -4090,7 +4105,7 @@
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"ldsh\\t%1, %0" "ldsh\\t%1, %0"
[(set_attr "type" "load") [(set_attr "type" "sload")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_expand "extendsidi2" (define_expand "extendsidi2"
...@@ -4106,7 +4121,7 @@ ...@@ -4106,7 +4121,7 @@
"@ "@
sra\\t%1, 0, %0 sra\\t%1, 0, %0
ldsw\\t%1, %0" ldsw\\t%1, %0"
[(set_attr "type" "unary,sload") [(set_attr "type" "shift,sload")
(set_attr "length" "1")]) (set_attr "length" "1")])
;; Special pattern for optimizing bit-field compares. This is needed ;; Special pattern for optimizing bit-field compares. This is needed
...@@ -4469,7 +4484,7 @@ ...@@ -4469,7 +4484,7 @@
(ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
"TARGET_ARCH64" "TARGET_ARCH64"
"addx\\t%r1, %2, %0" "addx\\t%r1, %2, %0"
[(set_attr "type" "unary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "subx" (define_insn "subx"
...@@ -4479,7 +4494,7 @@ ...@@ -4479,7 +4494,7 @@
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
"" ""
"subx\\t%r1, %2, %0" "subx\\t%r1, %2, %0"
[(set_attr "type" "unary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*subx_extend_sp64" (define_insn "*subx_extend_sp64"
...@@ -4489,7 +4504,7 @@ ...@@ -4489,7 +4504,7 @@
(ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
"TARGET_ARCH64" "TARGET_ARCH64"
"subx\\t%r1, %2, %0" "subx\\t%r1, %2, %0"
[(set_attr "type" "unary") [(set_attr "type" "misc")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "*subx_extend" (define_insn "*subx_extend"
...@@ -4547,7 +4562,9 @@ ...@@ -4547,7 +4562,9 @@
(plus:DI (match_operand:DI 1 "arith_double_operand" "%r") (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI")))] (match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64" "TARGET_ARCH64"
"add\\t%1, %2, %0") "add\\t%1, %2, %0"
[(set_attr "type" "binary")
(set_attr "length" "1")])
(define_insn "addsi3" (define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d") [(set (match_operand:SI 0 "register_operand" "=r,d")
...@@ -7016,7 +7033,9 @@ ...@@ -7016,7 +7033,9 @@
(define_insn "nop" (define_insn "nop"
[(const_int 0)] [(const_int 0)]
"" ""
"nop") "nop"
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_expand "indirect_jump" (define_expand "indirect_jump"
[(set (pc) (match_operand 0 "address_operand" "p"))] [(set (pc) (match_operand 0 "address_operand" "p"))]
...@@ -7096,7 +7115,8 @@ ...@@ -7096,7 +7115,8 @@
[(unspec_volatile [(const_int 0)] 1)] [(unspec_volatile [(const_int 0)] 1)]
"" ""
"* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";" "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";"
[(set_attr "type" "misc")]) [(set_attr "type" "misc")
(set_attr "length" "1")])
(define_insn "goto_handler_and_restore" (define_insn "goto_handler_and_restore"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "=r")] 2)] [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r")] 2)]
...@@ -7162,7 +7182,8 @@ ...@@ -7162,7 +7182,8 @@
[(unspec_volatile [(match_operand 0 "memory_operand" "m")] 4)] [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 4)]
"" ""
"* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";" "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";"
[(set_attr "type" "misc")]) [(set_attr "type" "misc")
(set_attr "length" "1")])
;; find first set. ;; find first set.
...@@ -7527,7 +7548,8 @@ ...@@ -7527,7 +7548,8 @@
[(trap_if (const_int 1) (const_int 5))] [(trap_if (const_int 1) (const_int 5))]
"" ""
"ta\\t5" "ta\\t5"
[(set_attr "type" "misc")]) [(set_attr "type" "misc")
(set_attr "length" "1")])
(define_expand "conditional_trap" (define_expand "conditional_trap"
[(trap_if (match_operator 0 "noov_compare_op" [(trap_if (match_operator 0 "noov_compare_op"
...@@ -7543,12 +7565,14 @@ ...@@ -7543,12 +7565,14 @@
(match_operand:SI 1 "arith_operand" "rM"))] (match_operand:SI 1 "arith_operand" "rM"))]
"" ""
"t%C0\\t%1" "t%C0\\t%1"
[(set_attr "type" "misc")]) [(set_attr "type" "misc")
(set_attr "length" "1")])
(define_insn "" (define_insn ""
[(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)]) [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)])
(match_operand:SI 1 "arith_operand" "rM"))] (match_operand:SI 1 "arith_operand" "rM"))]
"TARGET_V9" "TARGET_V9"
"t%C0\\t%%xcc, %1" "t%C0\\t%%xcc, %1"
[(set_attr "type" "misc")]) [(set_attr "type" "misc")
(set_attr "length" "1")])
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