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riscv-gcc-1
Commit 3b572406 by Richard Henderson Committed by Richard Henderson
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ia64-protos.h (process_for_unwind_directive): Declare. 

	* config/ia64/ia64-protos.h (process_for_unwind_directive): Declare.
	(ia64_file_start): Declare.
	* config/ia64/ia64.h (ADDL_REGNO_P): Don't compare unsigned against 0.
	(GR_REGNO_P): Likewise.
	* config/ia64/ia64.c: Many prototypes.
	(ia64_reg_numbers): Constify.
	(ia64_input_reg_names, ia64_local_reg_names): Likewise.
	(ia64_section_threshold): Make unsigned.
	(ia64_print_operand): Constify.
	(fix_range): Constify.
	(ia64_init_builtins): Don't compare signed vs unsigned.
	(ia64_expand_builtin): Likewise.

	* config/ia64/ia64.h (EXTRA_CONSTRAINT): New.
	(CONSTRAINT_OK_FOR_Q): New.
	* config/ia64/ia64.md (movdi_internal): Use Q for fp<->mem.
	(movsf_internal, movdf_internal): Likewise.
	(cmovdi_internal): Rewrite so that constraints and predicates match;
	simplify splitters.
	(cmovsi_internal): Likewise.

	* config/ia64/ia64.h (ASM_SPEC): Add -x for gas.
	(ASM_FILE_START): New.
	* config/ia64/ia64.c (ia64_file_start): New.
	(rtx_needs_barrier): Handle pred.rel.mutex.
	(emit_predicate_relation_info): New.
	* config/ia64/ia64.md (pred_rel_mutex): New.
	* config/ia64/linux.h (ASM_SPEC): Define.
	* config/ia64/sysv4.h (ASM_FILE_START): Define.

	* config/ia64/ia64.c (ia64_encode_section_info): Fix thinko
	filtering global register variables.

From-SVN: r34589
parent 5538e30f
Showing with 129 additions and 118 deletions
gcc/ChangeLog
2000-06-18 Richard Henderson <rth@cygnus.com>
* config/ia64/ia64-protos.h (process_for_unwind_directive): Declare.
(ia64_file_start): Declare.
* config/ia64/ia64.h (ADDL_REGNO_P): Don't compare unsigned against 0.
(GR_REGNO_P): Likewise.
* config/ia64/ia64.c: Many prototypes.
(ia64_reg_numbers): Constify.
(ia64_input_reg_names, ia64_local_reg_names): Likewise.
(ia64_section_threshold): Make unsigned.
(ia64_print_operand): Constify.
(fix_range): Constify.
(ia64_init_builtins): Don't compare signed vs unsigned.
(ia64_expand_builtin): Likewise.
* config/ia64/ia64.h (EXTRA_CONSTRAINT): New.
(CONSTRAINT_OK_FOR_Q): New.
* config/ia64/ia64.md (movdi_internal): Use Q for fp<->mem.
(movsf_internal, movdf_internal): Likewise.
(cmovdi_internal): Rewrite so that constraints and predicates match;
simplify splitters.
(cmovsi_internal): Likewise.
* config/ia64/ia64.h (ASM_SPEC): Add -x for gas.
(ASM_FILE_START): New.
* config/ia64/ia64.c (ia64_file_start): New.
(rtx_needs_barrier): Handle pred.rel.mutex.
(emit_predicate_relation_info): New.
* config/ia64/ia64.md (pred_rel_mutex): New.
* config/ia64/linux.h (ASM_SPEC): Define.
* config/ia64/sysv4.h (ASM_FILE_START): Define.
* config/ia64/ia64.c (ia64_encode_section_info): Fix thinko
filtering global register variables.
2000-06-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* c-common.c (add_c_tree_codes): Fix definition for traditional C.
......
gcc/config/ia64/ia64-protos.h
......@@ -61,6 +61,7 @@ extern enum reg_class ia64_secondary_reload_class PARAMS((enum reg_class,
enum machine_mode,
rtx));
extern void ia64_reorg PARAMS((rtx));
extern void process_for_unwind_directive PARAMS ((FILE *, rtx));
#endif /* RTX_CODE */
#ifdef TREE_CODE
......@@ -90,6 +91,7 @@ extern void ia64_encode_section_info PARAMS((tree));
#endif /* TREE_CODE */
extern int ia64_epilogue_uses PARAMS((int));
extern void ia64_file_start PARAMS((FILE *));
extern void ia64_expand_prologue PARAMS((void));
extern void ia64_expand_epilogue PARAMS((void));
extern void ia64_function_prologue PARAMS((FILE *, int));
......
gcc/config/ia64/ia64.h
......@@ -238,10 +238,10 @@ extern const char *ia64_fixed_range_string;
#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GNU_AS) != 0
/* GNU AS. */
#define ASM_SPEC "%{mno-gnu-as:-N so}"
#define ASM_SPEC "%{mno-gnu-as:-N so}%{!mno-gnu-as: -x}"
#else
/* Intel ias. */
#define ASM_SPEC "%{!mgnu-as:-N so}"
#define ASM_SPEC "%{!mgnu-as:-N so}%{mgnu-as: -x}"
#endif
/* A C string constant that tells the GNU CC driver program options to pass to
......@@ -543,8 +543,8 @@ while (0)
#define FIRST_PSEUDO_REGISTER 330
/* Ranges for the various kinds of registers. */
#define ADDL_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 3)
#define GR_REGNO_P(REGNO) ((REGNO) >= 0 && (REGNO) <= 127)
#define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
#define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
#define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
......@@ -1067,9 +1067,12 @@ enum reg_class
/* A C expression that defines the optional machine-dependent constraint
letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
types of operands, usually memory references, for the target machine. */
/* ??? This might be useful considering that we have already used all of the
integer constant contraint letters. */
/* #define EXTRA_CONSTRAINT(VALUE, C) */
#define CONSTRAINT_OK_FOR_Q(VALUE) \
(memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
#define EXTRA_CONSTRAINT(VALUE, C) \
((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) : 0)
/* Basic Stack Layout */
......@@ -1460,6 +1463,11 @@ do { \
#define FUNCTION_EPILOGUE(FILE, SIZE) \
ia64_function_epilogue (FILE, SIZE)
/* Output at beginning of assembler file. */
#define ASM_FILE_START(FILE) \
ia64_file_start (FILE)
/* A C compound statement that outputs the assembler code for a thunk function,
used to implement C++ virtual function calls with multiple inheritance. */
......
gcc/config/ia64/ia64.md
......@@ -80,6 +80,7 @@
;; 4 pfs_restore
;; 5 set_bsp
;; 6 pr_restore
;; 7 pred.rel.mutex
;; ::::::::::::::::::::
;; ::
......@@ -288,8 +289,8 @@
}")
(define_insn "*movdi_internal"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r, m, r,*f,*f,*f, m, r,*b")
(match_operand:DI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f, m,*f,*b,rO"))]
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r, m,r,*f,*f,*f,Q, r,*b")
(match_operand:DI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,Q,*f,*b,rO"))]
"! memory_operand (operands[0], DImode)
|| ! memory_operand (operands[1], DImode)"
"@
......@@ -301,8 +302,8 @@
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1
ldf8%O1 %0 = %1%P1
stf8%Q0 %0 = %1%P0
ldf8 %0 = %1%P1
stf8 %0 = %1%P0
mov %0 = %1
mov %0 = %r1"
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I")])
......@@ -392,8 +393,8 @@
}")
(define_insn "*movsf_internal"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
(match_operand:SF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"! memory_operand (operands[0], SFmode)
|| ! memory_operand (operands[1], SFmode)"
"@
......@@ -420,8 +421,8 @@
}")
(define_insn "*movdf_internal"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
(match_operand:DF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"! memory_operand (operands[0], DFmode)
|| ! memory_operand (operands[1], DFmode)"
"@
......@@ -447,6 +448,7 @@
operands[1] = copy_to_mode_reg (XFmode, operands[1]);
}")
;; ??? There's no easy way to mind volatile acquire/release semantics.
(define_insn "*movxf_internal"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,f, m")
(match_operand:XF 1 "general_operand" "fG,m,fG"))]
......@@ -2383,71 +2385,47 @@
;; ??? Add movXXcc patterns?
;; ??? The predicates don't match the constraints.
;; ??? r/c/m/m and m/c/r/r alternatives make sense, but won't work until the
;; predicates are fixed, because the define_splits won't recognize them.
;;
;; DImode if_then_else patterns.
;;
(define_insn "*cmovdi_internal"
[(set (match_operand:DI 0 "register_operand" "=r,r,m,r,r,m,r")
(define_insn_and_split "*cmovdi_internal"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=r,m,*f,Q,*b,r,m,*f,Q,*b,r,m,*f,Q,*b")
(if_then_else:DI
(match_operator:CC 4 "predicate_operator"
[(match_operand:CC 1 "register_operand" "c,c,c,c,c,c,c")
[(match_operand:CC 1 "register_operand"
"c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
(const_int 0)])
(match_operand:DI 2 "reg_or_22bit_operand" "0,0,0,rI,m,r,rI")
(match_operand:DI 3 "reg_or_22bit_operand" "rI,m,r,0,0,0,rI")))]
(match_operand:DI 2 "general_operand"
"0,0,0,0,0,rim*f*b,rO,rOQ,*f,r,rim*f*b,rO,rOQ,*f,r")
(match_operand:DI 3 "general_operand"
"rim*f*b,rO,rOQ,*f,r,0,0,0,0,0,rim*f*b,rO,rOQ,*f,r")))]
""
"#"
[(set_attr "type" "A,M,M,A,M,M,unknown")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(if_then_else:DI
(match_operator:CC 4 "predicate_operator"
[(match_operand:CC 1 "register_operand" "")
(const_int 0)])
(match_operand:DI 2 "reg_or_22bit_operand" "")
(match_operand:DI 3 "reg_or_22bit_operand" "")))]
"(reload_completed
&& (rtx_equal_p (operands[0], operands[2])
|| rtx_equal_p (operands[0], operands[3])))"
[(cond_exec
(match_dup 4)
(set (match_dup 0) (match_dup 2)))]
"reload_completed"
[(const_int 0)]
"
{
if (rtx_equal_p (operands[0], operands[2]))
rtx tmp;
if (! rtx_equal_p (operands[0], operands[2]))
{
operands[2] = operands[3];
operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
CCmode, operands[1], const0_rtx);
tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]);
tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp);
emit_insn (tmp);
}
}")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(if_then_else:DI
(match_operator:CC 4 "predicate_operator"
[(match_operand:CC 1 "register_operand" "")
(const_int 0)])
(match_operand:DI 2 "reg_or_22bit_operand" "")
(match_operand:DI 3 "reg_or_22bit_operand" "")))]
"reload_completed"
[(cond_exec
(match_dup 4)
(set (match_dup 0) (match_dup 2)))
(cond_exec
(match_dup 5)
(set (match_dup 0) (match_dup 3)))]
"
{
operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
if (! rtx_equal_p (operands[0], operands[3]))
{
tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
CCmode, operands[1], const0_rtx);
}")
tmp = gen_rtx_COND_EXEC (VOIDmode, tmp,
gen_rtx_SET (VOIDmode, operands[0],
operands[3]));
emit_insn (tmp);
}
DONE;
}"
[(set_attr "predicable" "no")])
;; Absolute value pattern.
......@@ -2461,7 +2439,8 @@
(match_operand:DI 3 "reg_or_22bit_operand" "0,rI")))]
""
"#"
[(set_attr "type" "A,unknown")])
[(set_attr "type" "A,unknown")
(set_attr "predicable" "no")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
......@@ -2503,62 +2482,41 @@
;; SImode if_then_else patterns.
;;
(define_insn "*cmovsi_internal"
[(set (match_operand:SI 0 "register_operand" "=r,r,m,r,r,m,r")
(define_insn_and_split "*cmovsi_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,*f,r,m,*f,r,m,*f")
(if_then_else:SI
(match_operator:CC 4 "predicate_operator"
[(match_operand:CC 1 "register_operand" "c,c,c,c,c,c,c")
[(match_operand:CC 1 "register_operand" "c,c,c,c,c,c,c,c,c")
(const_int 0)])
(match_operand:SI 2 "reg_or_22bit_operand" "0,0,0,rI,m,r,rI")
(match_operand:SI 3 "reg_or_22bit_operand" "rI,m,r,0,0,0,rI")))]
(match_operand:SI 2 "general_operand"
"0,0,0,rim*f,rO,rO,rim*f,rO,rO")
(match_operand:SI 3 "general_operand"
"rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
""
"#"
[(set_attr "type" "A,M,M,A,M,M,unknown")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(if_then_else:SI
(match_operator:CC 4 "predicate_operator"
[(match_operand:CC 1 "register_operand" "")
(const_int 0)])
(match_operand:SI 2 "reg_or_22bit_operand" "")
(match_operand:SI 3 "reg_or_22bit_operand" "")))]
"(reload_completed
&& (rtx_equal_p (operands[0], operands[2])
|| rtx_equal_p (operands[0], operands[3])))"
[(cond_exec
(match_dup 4)
(set (match_dup 0) (match_dup 2)))]
"reload_completed"
[(const_int 0)]
"
{
if (rtx_equal_p (operands[0], operands[2]))
rtx tmp;
if (! rtx_equal_p (operands[0], operands[2]))
{
operands[2] = operands[3];
operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
CCmode, operands[1], const0_rtx);
tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]);
tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp);
emit_insn (tmp);
}
}")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(if_then_else:SI
(match_operator:CC 4 "predicate_operator"
[(match_operand:CC 1 "register_operand" "")
(const_int 0)])
(match_operand:SI 2 "reg_or_22bit_operand" "")
(match_operand:SI 3 "reg_or_22bit_operand" "")))]
"reload_completed"
[(cond_exec
(match_dup 4)
(set (match_dup 0) (match_dup 2)))
(cond_exec
(match_dup 5)
(set (match_dup 0) (match_dup 3)))]
"
{
operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
if (! rtx_equal_p (operands[0], operands[3]))
{
tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
CCmode, operands[1], const0_rtx);
}")
tmp = gen_rtx_COND_EXEC (VOIDmode, tmp,
gen_rtx_SET (VOIDmode, operands[0],
operands[3]));
emit_insn (tmp);
}
DONE;
}"
[(set_attr "predicable" "no")])
(define_insn "*abssi2_internal"
[(set (match_operand:SI 0 "register_operand" "=r,r")
......@@ -2570,7 +2528,8 @@
(match_operand:SI 2 "reg_or_22bit_operand" "0,rI")))]
""
"#"
[(set_attr "type" "A,unknown")])
[(set_attr "type" "A,unknown")
(set_attr "predicable" "no")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
......@@ -3769,3 +3728,11 @@
(const_int 0)])]
""
"(%J0)")
(define_insn "pred_rel_mutex"
[(unspec_volatile [(match_operand:CC 0 "register_operand" "c")
(match_operand:CC 1 "register_operand" "c")] 7)]
""
".pred.rel.mutex %0,%1"
[(set_attr "type" "unknown")
(set_attr "predicable" "no")])
gcc/config/ia64/linux.h
......@@ -10,6 +10,7 @@
/* ??? ia64 gas doesn't accept standard svr4 assembler options? */
#undef ASM_SPEC
#define ASM_SPEC "-x"
/* Define this for shared library support because it isn't in the main
linux.h file. */
......
gcc/config/ia64/sysv4.h
......@@ -179,14 +179,12 @@ do { \
/* ??? Unrelated, but dwarf2out.c emits unnecessary newlines after strings,
may as well fix at the same time. */
#if 0
#undef ASM_FILE_START
#define ASM_FILE_START(STREAM) \
do { \
fputs (ASM_APP_OFF, STREAM); \
output_file_directive (STREAM, main_input_filename); \
ia64_file_start(STREAM); \
} while (0)
#endif
/* Case label alignment is handled by ADDR_VEC_ALIGN now. */
......@@ -228,7 +226,7 @@ do { \
/* Similarly for constant pool data. */
extern int ia64_section_threshold;
extern unsigned int ia64_section_threshold;
#undef SELECT_RTX_SECTION
#define SELECT_RTX_SECTION(MODE, RTX) \
{ \
......
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