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riscv-gcc-1
Commit 3aa775d6 by Walter Lee Committed by Walter Lee
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Fix some typos and coding style violations. 

	* confg/tilegx/tilegx.md: Fix code style.
	(*zero_extendsidi_truncdisi): Fix typo.
	* config/tilegx/tilegx.c: Fix code style.
	(tilegx_function_profiler): Fix typo.

From-SVN: r190739
parent a433d31f
Showing with 22 additions and 24 deletions
gcc/ChangeLog
2012-08-28 Walter Lee <walt@tilera.com>
* confg/tilegx/tilegx.md: Fix code style.
(*zero_extendsidi_truncdisi): Fix typo.
* config/tilegx/tilegx.c: Fix code style.
(tilegx_function_profiler): Fix typo.
2012-08-28 Walter Lee <walt@tilera.com>
* doc/invoke.texi: Document -mcmodel=small, -mcmodel=large.
* config/tilegx/tilegx.h: Include config/tilegx/tilegx-opts.h.
......
gcc/config/tilegx/tilegx.c
......@@ -168,7 +168,7 @@ tilegx_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
}
/* TARGET_MODE_REP_EXTENDED. */
/* Implement TARGET_MODE_REP_EXTENDED. */
static int
tilegx_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
{
......@@ -430,7 +430,7 @@ tilegx_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
addr = create_tmp_var (ptr_type_node, "va_arg");
/* if an object is dynamically sized, a pointer to it is passed
/* If an object is dynamically sized, a pointer to it is passed
instead of the object itself. */
pass_by_reference_p = pass_by_reference (NULL, TYPE_MODE (type), type,
false);
......@@ -660,7 +660,7 @@ tilegx_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
static rtx
create_temp_reg_if_possible (enum machine_mode mode, rtx default_reg)
{
return can_create_pseudo_p ()? gen_reg_rtx (mode) : default_reg;
return can_create_pseudo_p () ? gen_reg_rtx (mode) : default_reg;
}
......@@ -1413,8 +1413,8 @@ tilegx_simd_int (rtx num, enum machine_mode mode)
/* Returns true iff VAL can be moved into a register in one
instruction. And if it can, it emits the code to move the
constant into DEST_REG.
instruction. And if it can, it emits the code to move the constant
into DEST_REG.
If THREE_WIDE_ONLY is true, this insists on an instruction that
works in a bundle containing three instructions. */
......@@ -2131,6 +2131,7 @@ tilegx_expand_const_muldi (rtx op0, rtx op1, long long multiplier)
return false;
}
/* Expand the muldi pattern. */
bool
tilegx_expand_muldi (rtx op0, rtx op1, rtx op2)
......@@ -4320,6 +4321,7 @@ get_jump_target (rtx branch)
return 0;
}
/* Implement TARGET_SCHED_ADJUST_COST. */
static int
tilegx_sched_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
......@@ -5419,7 +5421,7 @@ tilegx_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
"\t{\n"
"\tmove\tr10, lr\n"
"\tjal\t%s\n"
"\t}\t\n", MCOUNT_NAME);
"\t}\n", MCOUNT_NAME);
}
tilegx_in_bundle = false;
......
gcc/config/tilegx/tilegx.md
......@@ -825,7 +825,7 @@
bit_width = INTVAL (operands[2]);
bit_offset = INTVAL (operands[3]);
/* Reject bitfields that can be done with a normal load */
/* Reject bitfields that can be done with a normal load. */
if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
FAIL;
......@@ -854,7 +854,6 @@
HOST_WIDE_INT bit_width = INTVAL (operands[2]);
HOST_WIDE_INT bit_offset = INTVAL (operands[3]);
if (MEM_P (operands[1]))
{
HOST_WIDE_INT first_byte_offset, last_byte_offset;
......@@ -862,7 +861,7 @@
if (GET_MODE (operands[1]) != QImode)
FAIL;
/* Reject bitfields that can be done with a normal load */
/* Reject bitfields that can be done with a normal load. */
if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
FAIL;
......@@ -954,7 +953,7 @@
"%1 = . + 8\n\tlnk\t%0"
[(set_attr "type" "Y1")])
;; First step of the 3-insn sequence to materialize a position
;; The next three patterns are used to to materialize a position
;; independent address by adding the difference of two labels to a
;; base label in the text segment, assuming that the difference fits
;; in 32 signed bits.
......@@ -966,10 +965,6 @@
UNSPEC_HW1_LAST_PCREL)))]
"flag_pic")
;; Second step of the 3-insn sequence to materialize a position
;; independent address by adding the difference of two labels to a
;; base label in the text segment, assuming that the difference fits
;; in 32 signed bits.
(define_expand "mov_pcrel_step2<bitsuffix>"
[(set (match_operand:I48MODE 0 "register_operand" "")
(unspec:I48MODE
......@@ -981,10 +976,6 @@
UNSPEC_INSN_ADDR_SHL16INSLI))]
"flag_pic")
;; Third step of the 3-insn sequence to materialize a position
;; independent address by adding the difference of two labels to a base
;; label in the text segment, assuming that the difference fits in 32
;; signed bits.
(define_insn "mov_pcrel_step3<bitsuffix>"
[(set (match_operand:I48MODE 0 "register_operand" "=r")
(unspec:I48MODE [(match_operand:I48MODE 1 "reg_or_0_operand" "rO")
......@@ -1442,7 +1433,6 @@
DONE;
})
(define_expand "subdf3"
[(set (match_operand:DF 0 "register_operand" "")
(minus:DF (match_operand:DF 1 "register_operand" "")
......@@ -1815,7 +1805,6 @@
"ctz\t%0, %r1"
[(set_attr "type" "Y0")])
(define_insn "popcount<mode>2"
[(set (match_operand:I48MODE 0 "register_operand" "=r")
(popcount:I48MODE (match_operand:DI 1 "reg_or_0_operand" "rO")))]
......@@ -2044,7 +2033,7 @@
(define_insn "*zero_extendsidi_truncdisi"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(truncate:SI (match_operand:DI 1 "reg_or_0_operand" "0"))))]
(truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))))]
""
"v4int_l\t%0, zero, %r1"
[(set_attr "type" "X01")])
......@@ -2320,7 +2309,8 @@
;; Loops
;;
;; Define the subtract-one-and-jump insns so loop.c knows what to generate.
;; Define the subtract-one-and-jump insns so loop.c knows what to
;; generate.
(define_expand "doloop_end"
[(use (match_operand 0 "" "")) ;; loop pseudo
(use (match_operand 1 "" "")) ;; iterations; zero if unknown
......@@ -2633,8 +2623,8 @@
[(set_attr "type" "*,*,X01")])
;; Used for move sp, r52, to pop a stack frame. We need to make sure
;; that stack frame memory operations have been issued before we do this.
;; TODO: see above TODO.
;; that stack frame memory operations have been issued before we do
;; this. TODO: see above TODO.
(define_insn "sp_restore<bitsuffix>"
[(set (match_operand:I48MODE 0 "register_operand" "=r")
(match_operand:I48MODE 1 "register_operand" "r"))
......
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